Apr 23 03:24:48.283276 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffc4fe60 Apr 23 03:24:48.283763 (XEN) Apr 23 03:24:48.283826 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:48.283890 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:48.283956 (XEN) Apr 23 03:24:48.284013 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:48.288856 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:48.288909 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:48.288953 (XEN) Apr 23 03:24:48.288992 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:48.289035 (XEN) HPFAR_EL2: 0000009010805d00 Apr 23 03:24:48.300860 (XEN) FAR_EL2: ffff8000835d0100 Apr 23 03:24:48.300918 (XEN) Apr 23 03:24:48.300958 (XEN) Xen stack trace from sp=0000800fffc4fe60: Apr 23 03:24:48.301005 (XEN) 0000800fffc4fe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:48.316864 (XEN) 0000000000000040 0000000000000000 0000000000000000 0000000000010100 Apr 23 03:24:48.316973 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.328838 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.328919 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.340744 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.340789 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.352745 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.364810 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.364881 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.376815 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.376891 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.388830 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.388906 (XEN) Xen call trace: Apr 23 03:24:48.400810 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:48.400884 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:48.412813 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:48.412916 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:48.412985 (XEN) Apr 23 03:24:48.413041 (XEN) *** Dumping CPU65 host state: *** Apr 23 03:24:48.424816 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:48.424898 (XEN) CPU: 65 Apr 23 03:24:48.424981 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:48.436833 (XEN) LR: 00000a000025d098 Apr 23 03:24:48.436904 (XEN) SP: 0000800fffc47e60 Apr 23 03:24:48.436968 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:48.448807 (XEN) X0: 0000000000000000 X1: 0000760fff94c000 X2: 0000800fffc54048 Apr 23 03:24:48.448909 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:48.460730 (XEN) X6: 00000a000033f5b0 X7: 0000800fffccdc00 X8: 0000000000000012 Apr 23 03:24:48.460771 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:48.472836 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:48.472919 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 23 03:24:48.484841 (XEN) X18: 0000000000000000 X19: 00000a000033f5b8 X20: 0000000000000041 Apr 23 03:24:48.496820 (XEN) X21: 00000a0000310000 X22: 0000000000000002 X23: 0000000000000041 Apr 23 03:24:48.496903 (XEN) X24: 0000000000000041 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:48.508816 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffc47e60 Apr 23 03:24:48.508898 (XEN) Apr 23 03:24:48.508957 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:48.520878 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:48.520956 (XEN) Apr 23 03:24:48.521021 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:48.521068 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:48.521111 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:48.532874 (XEN) Apr 23 03:24:48.532928 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:48.532997 (XEN) HPFAR_EL2: 0000008010800900 Apr 23 03:24:48.533043 (XEN) FAR_EL2: ffff800082890100 Apr 23 03:24:48.544861 (XEN) Apr 23 03:24:48.544915 (XEN) Xen stack trace from sp=0000800fffc47e60: Apr 23 03:24:48.544964 (XEN) 0000800fffc47e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:48.556860 (XEN) 0000000000000041 0000000000000000 0000000000000000 0000000000010101 Apr 23 03:24:48.556924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.568857 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.568921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.580881 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.580967 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.592863 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.592927 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.604883 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.616861 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.616945 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.628854 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.628918 (XEN) Xen call trace: Apr 23 03:24:48.628963 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:48.640768 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:48.640814 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:48.652864 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:48.652923 (XEN) Apr 23 03:24:48.652966 (XEN) *** Dumping CPU66 host state: *** Apr 23 03:24:48.664857 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:48.664943 (XEN) CPU: 66 Apr 23 03:24:48.664989 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:48.676860 (XEN) LR: 00000a000025d098 Apr 23 03:24:48.676919 (XEN) SP: 0000800ffdfdfe60 Apr 23 03:24:48.676964 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:48.688854 (XEN) X0: 0000000000000000 X1: 0000760fff94a000 X2: 0000800fffc52048 Apr 23 03:24:48.688919 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:48.700883 (XEN) X6: 00000a000033f5b0 X7: 0000800fffc50150 X8: 0000000000000012 Apr 23 03:24:48.700947 (XEN) X9: 0000000000000080 X10: 0000000000000a10 X11: 0000000000000000 Apr 23 03:24:48.712877 (XEN) X12: 0000000000000001 X13: 0000000000000069 X14: 0000000000000069 Apr 23 03:24:48.712963 (XEN) X15: 0000000000000000 X16: 0000000084cf4d40 X17: ffff8000821e0240 Apr 23 03:24:48.724864 (XEN) X18: ffff8000837fbb78 X19: 00000a000033f5b8 X20: 0000000000000042 Apr 23 03:24:48.724929 (XEN) X21: 00000a0000310080 X22: 0000000000000004 X23: 0000000000000042 Apr 23 03:24:48.736865 (XEN) X24: 0000000000000042 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:48.748858 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdfdfe60 Apr 23 03:24:48.748944 (XEN) Apr 23 03:24:48.748987 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:48.749031 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:48.760862 (XEN) Apr 23 03:24:48.760916 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:48.760984 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:48.761030 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:48.772867 (XEN) Apr 23 03:24:48.772922 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:48.772968 (XEN) HPFAR_EL2: 0000008010801500 Apr 23 03:24:48.773036 (XEN) FAR_EL2: ffff800082950100 Apr 23 03:24:48.773081 (XEN) Apr 23 03:24:48.773120 (XEN) Xen stack trace from sp=0000800ffdfdfe60: Apr 23 03:24:48.784876 (XEN) 0000800ffdfdfe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:48.784940 (XEN) 0000000000000042 0000000000000000 0000000000000000 0000000000010102 Apr 23 03:24:48.796866 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.808853 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.808917 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.820881 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.820945 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.832869 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.832932 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.844856 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.844918 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.856772 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.868763 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:48.868810 (XEN) Xen call trace: Apr 23 03:24:48.868834 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:48.880767 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:48.880802 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:48.892771 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:48.892815 (XEN) Apr 23 03:24:48.892839 (XEN) *** Dumping CPU67 host state: *** Apr 23 03:24:48.892864 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:48.904889 (XEN) CPU: 67 Apr 23 03:24:48.904944 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:48.905016 (XEN) LR: 00000a000025d098 Apr 23 03:24:48.916860 (XEN) SP: 0000800ffdfcfe60 Apr 23 03:24:48.916917 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:48.916969 (XEN) X0: 0000000000000000 X1: 0000760ffdcce000 X2: 0000800ffdfd6048 Apr 23 03:24:48.928866 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:48.940859 (XEN) X6: 00000a000033f5b0 X7: 0000800fffc50590 X8: 0000000000000012 Apr 23 03:24:48.940923 (XEN) X9: 0000000000000080 X10: 0000000000000a10 X11: 0000000000000001 Apr 23 03:24:48.952880 (XEN) X12: 0000000000000003 X13: 0000000000000000 X14: ffff000029675440 Apr 23 03:24:48.952943 (XEN) X15: 0000000000000000 X16: 1fffe0000508d0e1 X17: 0000000000000000 Apr 23 03:24:48.964865 (XEN) X18: ffff800084fe3c58 X19: 00000a000033f5b8 X20: 0000000000000043 Apr 23 03:24:48.964951 (XEN) X21: 00000a0000310100 X22: 0000000000000008 X23: 0000000000000043 Apr 23 03:24:48.976907 (XEN) X24: 0000000000000043 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:48.976972 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdfcfe60 Apr 23 03:24:48.988870 (XEN) Apr 23 03:24:48.988924 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:48.988992 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:49.000858 (XEN) Apr 23 03:24:49.000912 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:49.000959 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:49.001003 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:49.001071 (XEN) Apr 23 03:24:49.012761 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:49.012794 (XEN) HPFAR_EL2: 0000008010802100 Apr 23 03:24:49.012818 (XEN) FAR_EL2: ffff800082a10100 Apr 23 03:24:49.012852 (XEN) Apr 23 03:24:49.012887 (XEN) Xen stack trace from sp=0000800ffdfcfe60: Apr 23 03:24:49.024764 (XEN) 0000800ffdfcfe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:49.024799 (XEN) 0000000000000043 0000000000000000 0000000000000000 0000000000010103 Apr 23 03:24:49.036862 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.036926 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.048863 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.060856 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.060920 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.072856 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.072921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.084861 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.084925 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.096854 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.096917 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.108874 (XEN) Xen call trace: Apr 23 03:24:49.108952 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:49.120768 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:49.120803 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:49.132867 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:49.132927 (XEN) Apr 23 03:24:49.132989 (XEN) *** Dumping CPU68 host state: *** Apr 23 03:24:49.133036 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:49.144862 (XEN) CPU: 68 Apr 23 03:24:49.144917 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:49.144968 (XEN) LR: 00000a000025d098 Apr 23 03:24:49.156854 (XEN) SP: 0000800ffdfc7e60 Apr 23 03:24:49.156912 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:49.156964 (XEN) X0: 0000000000000000 X1: 0000760ffdcca000 X2: 0000800ffdfd2048 Apr 23 03:24:49.168862 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:49.168925 (XEN) X6: 00000a000033f5b0 X7: 0000800fffc50a50 X8: 0000000000000012 Apr 23 03:24:49.180867 (XEN) X9: 0000000000000080 X10: 0000000000000a10 X11: 0000000000000000 Apr 23 03:24:49.192864 (XEN) X12: 0000000000000001 X13: 00000000000003ef X14: 00000000000003ef Apr 23 03:24:49.192927 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 23 03:24:49.204852 (XEN) X18: 0000000000000000 X19: 00000a000033f5b8 X20: 0000000000000044 Apr 23 03:24:49.204916 (XEN) X21: 00000a0000310180 X22: 0000000000000010 X23: 0000000000000044 Apr 23 03:24:49.216866 (XEN) X24: 0000000000000044 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:49.216931 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdfc7e60 Apr 23 03:24:49.228766 (XEN) Apr 23 03:24:49.228795 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:49.228821 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:49.228845 (XEN) Apr 23 03:24:49.240857 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:49.240915 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:49.240961 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:49.241005 (XEN) Apr 23 03:24:49.241045 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:49.252858 (XEN) HPFAR_EL2: 0000008010802d00 Apr 23 03:24:49.252917 (XEN) FAR_EL2: ffff800082ad0100 Apr 23 03:24:49.252964 (XEN) Apr 23 03:24:49.253005 (XEN) Xen stack trace from sp=0000800ffdfc7e60: Apr 23 03:24:49.264851 (XEN) 0000800ffdfc7e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:49.264917 (XEN) 0000000000000044 0000000000000000 0000000000000000 0000000000010104 Apr 23 03:24:49.276890 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.276955 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.288860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.288925 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.300863 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.312854 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.312917 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.324859 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.324923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.336800 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.336834 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.348871 (XEN) Xen call trace: Apr 23 03:24:49.348928 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:49.360856 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:49.360921 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:49.360970 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:49.372864 (XEN) Apr 23 03:24:49.372917 (XEN) *** Dumping CPU69 host state: *** Apr 23 03:24:49.372964 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:49.384848 (XEN) CPU: 69 Apr 23 03:24:49.384903 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:49.384954 (XEN) LR: 00000a000025d098 Apr 23 03:24:49.384998 (XEN) SP: 0000800ffdf57e60 Apr 23 03:24:49.396858 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:49.396922 (XEN) X0: 0000000000000000 X1: 0000760ffdcc8000 X2: 0000800ffdfd0048 Apr 23 03:24:49.408860 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:49.408923 (XEN) X6: 00000a000033f5b0 X7: 0000800ffdf5e010 X8: 0000000000000012 Apr 23 03:24:49.420870 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:49.420950 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:49.432871 (XEN) X15: 0000000000000001 X16: 1fffe00004d9cbc1 X17: 0000000000000000 Apr 23 03:24:49.444775 (XEN) X18: ffff800084f1bc58 X19: 00000a000033f5b8 X20: 0000000000000045 Apr 23 03:24:49.444819 (XEN) X21: 00000a0000310200 X22: 0000000000000020 X23: 0000000000000045 Apr 23 03:24:49.456854 (XEN) X24: 0000000000000045 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:49.456917 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf57e60 Apr 23 03:24:49.468850 (XEN) Apr 23 03:24:49.468909 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:49.468969 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:49.469027 (XEN) Apr 23 03:24:49.469076 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:49.480878 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:49.480938 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:49.480985 (XEN) Apr 23 03:24:49.481025 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:49.492856 (XEN) HPFAR_EL2: 0000008010000200 Apr 23 03:24:49.492915 (XEN) FAR_EL2: ffff800082680090 Apr 23 03:24:49.492960 (XEN) Apr 23 03:24:49.493001 (XEN) Xen stack trace from sp=0000800ffdf57e60: Apr 23 03:24:49.493050 (XEN) 0000800ffdf57e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:49.504879 (XEN) 0000000000000045 0000000000000000 0000000000000000 0000000000010105 Apr 23 03:24:49.516905 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.516967 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.528846 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.528908 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.540849 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.540912 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.552914 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.564840 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.564925 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.576831 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.576915 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.588879 (XEN) Xen call trace: Apr 23 03:24:49.588937 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:49.588991 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:49.600887 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:49.600950 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:49.612871 (XEN) Apr 23 03:24:49.612927 (XEN) *** Dumping CPU70 host state: *** Apr 23 03:24:49.612976 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:49.624875 (XEN) CPU: 70 Apr 23 03:24:49.624950 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:49.625023 (XEN) LR: 00000a000025d098 Apr 23 03:24:49.625086 (XEN) SP: 0000800ffdf4fe60 Apr 23 03:24:49.636895 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:49.636980 (XEN) X0: 0000000000000000 X1: 0000760ffdc54000 Apr 23 03:24:49.646258 X2: 0000800ffdf5c048 Apr 23 03:24:49.649613 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:49.649693 (XEN) X6: 00000a000033f5b0 X7: 00 Apr 23 03:24:49.653201 00800ffdf5e410 X8: 0000000000000012 Apr 23 03:24:49.664786 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:49.664820 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:49.676757 (XEN) X15: 00003d0900000000 X16: 1fffe00004a00481 X17: 0000000000000000 Apr 23 03:24:49.676793 (XEN) X18: ffff800084ef3c58 X19: 00000a000033f5b8 X20: 0000000000000046 Apr 23 03:24:49.692777 (XEN) X21: 00000a0000310280 X22: 0000000000000040 X23: 0000000000000046 Apr 23 03:24:49.692812 (XEN) X24: 0000000000000046 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:49.692839 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf4fe60 Apr 23 03:24:49.704778 (XEN) Apr 23 03:24:49.704807 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:49.704833 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:49.716768 (XEN) Apr 23 03:24:49.716797 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:49.716822 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:49.716847 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:49.716871 (XEN) Apr 23 03:24:49.716893 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:49.728761 (XEN) HPFAR_EL2: 0000008010804500 Apr 23 03:24:49.728793 (XEN) FAR_EL2: ffff800082c50100 Apr 23 03:24:49.728818 (XEN) Apr 23 03:24:49.728839 (XEN) Xen stack trace from sp=0000800ffdf4fe60: Apr 23 03:24:49.740756 (XEN) 0000800ffdf4fe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:49.740791 (XEN) 0000000000000046 0000000000000000 0000000000000000 0000000000010106 Apr 23 03:24:49.752764 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.752800 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.764768 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.764815 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.776810 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.788855 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.788918 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.800860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.800925 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.812861 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.812924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.824864 (XEN) Xen call trace: Apr 23 03:24:49.824922 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:49.836850 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:49.836914 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:49.848887 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:49.848948 (XEN) Apr 23 03:24:49.848989 (XEN) *** Dumping CPU71 host state: *** Apr 23 03:24:49.849035 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:49.860862 (XEN) CPU: 71 Apr 23 03:24:49.860919 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:49.860970 (XEN) LR: 00000a000025d098 Apr 23 03:24:49.872879 (XEN) SP: 0000800ffdf47e60 Apr 23 03:24:49.872937 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:49.872989 (XEN) X0: 0000000000000000 X1: 0000760ffdc50000 X2: 0000800ffdf58048 Apr 23 03:24:49.884861 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:49.884925 (XEN) X6: 00000a000033f5b0 X7: 0000800ffdf5e8d0 X8: 0000000000000012 Apr 23 03:24:49.896876 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:49.908853 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:49.908916 (XEN) X15: 00003d0900000000 X16: 1fffe00004a00481 X17: 0000000000000000 Apr 23 03:24:49.920858 (XEN) X18: ffff800084ef3c58 X19: 00000a000033f5b8 X20: 0000000000000047 Apr 23 03:24:49.920922 (XEN) X21: 00000a0000310300 X22: 0000000000000080 X23: 0000000000000047 Apr 23 03:24:49.932877 (XEN) X24: 0000000000000047 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:49.932948 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf47e60 Apr 23 03:24:49.944864 (XEN) Apr 23 03:24:49.944919 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:49.944967 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:49.945012 (XEN) Apr 23 03:24:49.956773 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:49.956806 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:49.956831 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:49.956855 (XEN) Apr 23 03:24:49.956876 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:49.968762 (XEN) HPFAR_EL2: 0000008010805100 Apr 23 03:24:49.968794 (XEN) FAR_EL2: ffff800082d10100 Apr 23 03:24:49.968818 (XEN) Apr 23 03:24:49.968840 (XEN) Xen stack trace from sp=0000800ffdf47e60: Apr 23 03:24:49.980765 (XEN) 0000800ffdf47e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:49.980800 (XEN) 0000000000000047 0000000000000000 0000000000000000 0000000000010107 Apr 23 03:24:49.992765 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:49.992800 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.004863 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.004927 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.016860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.016940 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.028864 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.040858 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.040921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.052860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.052925 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.064862 (XEN) Xen call trace: Apr 23 03:24:50.064920 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:50.076858 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:50.076924 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:50.076975 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:50.088857 (XEN) Apr 23 03:24:50.088912 (XEN) *** Dumping CPU72 host state: *** Apr 23 03:24:50.088961 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:50.100874 (XEN) CPU: 72 Apr 23 03:24:50.100931 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:50.100981 (XEN) LR: 00000a000025d098 Apr 23 03:24:50.101025 (XEN) SP: 0000800ffdef7e60 Apr 23 03:24:50.112857 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:50.112922 (XEN) X0: 0000000000000000 X1: 0000760ffdbf6000 X2: 0000800ffdefe048 Apr 23 03:24:50.124872 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:50.124936 (XEN) X6: 00000a000033f5b0 X7: 0000800ffdf5ed90 X8: 0000000000000012 Apr 23 03:24:50.136873 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:50.136936 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:50.148864 (XEN) X15: 0000000000000000 X16: 1fffe00004a00481 X17: 0000000000000000 Apr 23 03:24:50.160854 (XEN) X18: ffff800084ef3c58 X19: 00000a000033f5b8 X20: 0000000000000048 Apr 23 03:24:50.160919 (XEN) X21: 00000a0000310380 X22: 0000000000000100 X23: 0000000000000048 Apr 23 03:24:50.172856 (XEN) X24: 0000000000000048 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:50.172920 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdef7e60 Apr 23 03:24:50.184850 (XEN) Apr 23 03:24:50.184904 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:50.184951 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:50.184996 (XEN) Apr 23 03:24:50.185036 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:50.196869 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:50.196929 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:50.196975 (XEN) Apr 23 03:24:50.197016 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:50.197061 (XEN) HPFAR_EL2: 0000008010805d00 Apr 23 03:24:50.208766 (XEN) FAR_EL2: ffff800082dd0100 Apr 23 03:24:50.208797 (XEN) Apr 23 03:24:50.208820 (XEN) Xen stack trace from sp=0000800ffdef7e60: Apr 23 03:24:50.208845 (XEN) 0000800ffdef7e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:50.220778 (XEN) 0000000000000048 0000000000000000 0000000000000000 0000000000010108 Apr 23 03:24:50.232768 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.232803 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.244820 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.244883 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.256857 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.256921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.268872 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.280887 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.280953 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.292856 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.292919 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.304882 (XEN) Xen call trace: Apr 23 03:24:50.304939 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:50.304991 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:50.316767 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:50.316801 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:50.328766 (XEN) Apr 23 03:24:50.328795 (XEN) *** Dumping CPU73 host state: *** Apr 23 03:24:50.328821 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:50.328848 (XEN) CPU: 73 Apr 23 03:24:50.340870 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:50.340935 (XEN) LR: 00000a000025d098 Apr 23 03:24:50.340980 (XEN) SP: 0000800ffdeefe60 Apr 23 03:24:50.352870 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:50.352935 (XEN) X0: 0000000000000000 X1: 0000760ffdbf2000 X2: 0000800ffdefa048 Apr 23 03:24:50.364880 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:50.364944 (XEN) X6: 00000a000033f5b0 X7: 0000800ffdefc280 X8: 0000000000000012 Apr 23 03:24:50.376859 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:50.376923 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:50.388861 (XEN) X15: 0000000000000000 X16: 1fffe00004a00481 X17: 0000000000000000 Apr 23 03:24:50.388925 (XEN) X18: ffff800084ef3c58 X19: 00000a000033f5b8 X20: 0000000000000049 Apr 23 03:24:50.400865 (XEN) X21: 00000a0000310400 X22: 0000000000000200 X23: 0000000000000049 Apr 23 03:24:50.412856 (XEN) X24: 0000000000000049 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:50.412921 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdeefe60 Apr 23 03:24:50.424761 (XEN) Apr 23 03:24:50.424790 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:50.424815 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:50.424839 (XEN) Apr 23 03:24:50.424861 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:50.436770 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:50.436802 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:50.436827 (XEN) Apr 23 03:24:50.436849 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:50.436873 (XEN) HPFAR_EL2: 0000009010800900 Apr 23 03:24:50.448766 (XEN) FAR_EL2: ffff800083090100 Apr 23 03:24:50.448798 (XEN) Apr 23 03:24:50.448822 (XEN) Xen stack trace from sp=0000800ffdeefe60: Apr 23 03:24:50.448848 (XEN) 0000800ffdeefe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:50.460859 (XEN) 0000000000000049 0000000000000000 0000000000000000 0000000000010109 Apr 23 03:24:50.460921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.472767 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.484767 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.484801 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.496763 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.496797 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.508860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.508922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.520860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.532870 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.532935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.544857 (XEN) Xen call trace: Apr 23 03:24:50.544913 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:50.544965 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:50.556865 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:50.556928 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:50.568856 (XEN) Apr 23 03:24:50.568910 (XEN) *** Dumping CPU74 host state: *** Apr 23 03:24:50.568958 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:50.569008 (XEN) CPU: 74 Apr 23 03:24:50.580866 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:50.580931 (XEN) LR: 00000a000025d098 Apr 23 03:24:50.580977 (XEN) SP: 0000800ffde7fe60 Apr 23 03:24:50.581022 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:50.592891 (XEN) X0: 0000000000000000 X1: 0000760ffdbde000 X2: 0000800ffdee6048 Apr 23 03:24:50.592955 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:50.604905 (XEN) X6: 00000a000033f5b0 X7: 0000800ffdefc740 X8: 0000000000000012 Apr 23 03:24:50.616851 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:50.616915 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:50.628871 (XEN) X15: 0000000000000000 X16: 1fffe00004a00481 X17: 0000000000000000 Apr 23 03:24:50.628934 (XEN) X18: ffff800084ef3c58 X19: 00000a000033f5b8 X20: 000000000000004a Apr 23 03:24:50.640862 (XEN) X21: 00000a0000310480 X22: 0000000000000400 X23: 000000000000004a Apr 23 03:24:50.640925 (XEN) X24: 000000000000004a X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:50.652867 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde7fe60 Apr 23 03:24:50.664874 (XEN) Apr 23 03:24:50.664929 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:50.664977 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:50.665022 (XEN) Apr 23 03:24:50.665062 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:50.665106 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:50.676857 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:50.676916 (XEN) Apr 23 03:24:50.676957 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:50.677001 (XEN) HPFAR_EL2: 0000009010801500 Apr 23 03:24:50.688860 (XEN) FAR_EL2: ffff800083150100 Apr 23 03:24:50.688920 (XEN) Apr 23 03:24:50.688961 (XEN) Xen stack trace from sp=0000800ffde7fe60: Apr 23 03:24:50.689008 (XEN) 0000800ffde7fe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:50.700865 (XEN) 000000000000004a 0000000000000000 0000000000000000 000000000001010a Apr 23 03:24:50.700928 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.712872 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.712936 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.724895 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.736840 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.736902 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.748859 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.748922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.760858 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.760921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.772871 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.784882 (XEN) Xen call trace: Apr 23 03:24:50.784940 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:50.784993 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:50.796765 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:50.796799 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:50.796825 (XEN) Apr 23 03:24:50.796847 (XEN) *** Dumping CPU75 host state: *** Apr 23 03:24:50.808862 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:50.808925 (XEN) CPU: 75 Apr 23 03:24:50.808967 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:50.820780 (XEN) LR: 00000a000025d098 Apr 23 03:24:50.820819 (XEN) SP: 0000800ffde77e60 Apr 23 03:24:50.820843 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:50.832764 (XEN) X0: 0000000000000000 X1: 0000760ffdbdc000 X2: 0000800ffdee4048 Apr 23 03:24:50.832799 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:50.844881 (XEN) X6: 00000a000033f5b0 X7: 0000800ffdefcc00 X8: 0000000000000012 Apr 23 03:24:50.844944 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:50.856874 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:50.868855 (XEN) X15: 0000000000000000 X16: 1fffe00004a00481 X17: 0000000000000000 Apr 23 03:24:50.868918 (XEN) X18: ffff800084ef3c58 X19: 00000a000033f5b8 X20: 000000000000004b Apr 23 03:24:50.880853 (XEN) X21: 00000a0000310500 X22: 0000000000000800 X23: 000000000000004b Apr 23 03:24:50.880916 (XEN) X24: 000000000000004b X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:50.892895 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde77e60 Apr 23 03:24:50.892958 (XEN) Apr 23 03:24:50.893000 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:50.904860 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:50.904917 (XEN) Apr 23 03:24:50.904957 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:50.905003 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:50.916853 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:50.916912 (XEN) Apr 23 03:24:50.916953 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:50.916996 (XEN) HPFAR_EL2: 0000009010802100 Apr 23 03:24:50.917041 (XEN) FAR_EL2: ffff800083210100 Apr 23 03:24:50.928857 (XEN) Apr 23 03:24:50.928910 (XEN) Xen stack trace from sp=0000800ffde77e60: Apr 23 03:24:50.928958 (XEN) 0000800ffde77e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:50.940860 (XEN) 000000000000004b 0000000000000000 0000000000000000 000000000001010b Apr 23 03:24:50.940923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.952859 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.952922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.964766 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.964800 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.976764 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.988765 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:50.988799 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.000768 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.000802 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.012780 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.012814 (XEN) Xen call trace: Apr 23 03:24:51.024762 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:51.024797 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:51.036773 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:51.036807 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:51.036833 (XEN) Apr 23 03:24:51.036854 (XEN) *** Dumping CPU76 host state: *** Apr 23 03:24:51.048787 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:51.048822 (XEN) CPU: 76 Apr 23 03:24:51.048845 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:51.060766 (XEN) LR: 00000a000025d098 Apr 23 03:24:51.060797 (XEN) SP: 0000800ffde67e60 Apr 23 03:24:51.060821 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:51.072771 (XEN) X0: 0000000000000000 X1: 0000760ffdbd8000 X2: 0000800ffdee0048 Apr 23 03:24:51.072806 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:51.084769 (XEN) X6: 00000a000033f5b0 X7: 0000800ffde6f150 X8: 0000000000000012 Apr 23 03:24:51.084804 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:51.096773 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:51.096807 (XEN) X15: 0000000000000000 X16: 1fffe00004a00481 X17: 0000000000000000 Apr 23 03:24:51.108774 (XEN) X18: ffff800084ef3c58 X19: 00000a000033f5b8 X20: 000000000000004c Apr 23 03:24:51.120786 (XEN) X21: 00000a0000310580 X22: 0000000000001000 X23: 000000000000004c Apr 23 03:24:51.120821 (XEN) X24: 000000000000004c X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:51.132767 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde67e60 Apr 23 03:24:51.132802 (XEN) Apr 23 03:24:51.132824 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:51.144860 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:51.144918 (XEN) Apr 23 03:24:51.144959 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:51.145003 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:51.145046 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:51.156857 (XEN) Apr 23 03:24:51.156910 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:51.156955 (XEN) HPFAR_EL2: 0000009010802d00 Apr 23 03:24:51.156999 (XEN) FAR_EL2: ffff8000832d0100 Apr 23 03:24:51.168856 (XEN) Apr 23 03:24:51.168910 (XEN) Xen stack trace from sp=0000800ffde67e60: Apr 23 03:24:51.168958 (XEN) 0000800ffde67e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:51.169007 (XEN) 000000000000004c 0000000000000000 0000000000000000 000000000001010c Apr 23 03:24:51.180881 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.192867 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.192929 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.204872 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.204935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.216874 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.216936 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.228880 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.240865 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.240928 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.252858 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.252920 (XEN) Xen call trace: Apr 23 03:24:51.252965 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:51.264868 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:51.264930 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:51.276870 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:51.276929 (XEN) Apr 23 03:24:51.276970 (XEN) *** Dumping CPU77 host state: *** Apr 23 03:24:51.288888 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:51.288953 (XEN) CPU: 77 Apr 23 03:24:51.288996 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:51.300857 (XEN) LR: 00000a000025d098 Apr 23 03:24:51.300915 (XEN) SP: 0000800ffd9ffe60 Apr 23 03:24:51.300960 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:51.312858 (XEN) X0: 0000000000000000 X1: 0000760ffdb64000 X2: 0000800ffde6c048 Apr 23 03:24:51.312922 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:51.324861 (XEN) X6: 00000a000033f5b0 X7: 0000800ffde6f590 X8: 0000000000000012 Apr 23 03:24:51.324925 (XEN) X9: 0000000000000080 X10: 0000000000000000 X11: 00000000000000b2 Apr 23 03:24:51.336861 (XEN) X12: 0000000000000000 X13: 000000000000024b X14: 0000000000000278 Apr 23 03:24:51.336923 (XEN) X15: 00000000be055565 X16: 000000006a391f54 X17: 0000000068941f72 Apr 23 03:24:51.348872 (XEN) X18: 0000000000000014 X19: 00000a000033f5b8 X20: 000000000000004d Apr 23 03:24:51.348935 (XEN) X21: 00000a0000310600 X22: 0000000000002000 X23: 000000000000004d Apr 23 03:24:51.360882 (XEN) X24: 000000000000004d X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:51.372851 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd9ffe60 Apr 23 03:24:51.372915 (XEN) Apr 23 03:24:51.372959 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:51.372983 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:51.384777 (XEN) Apr 23 03:24:51.384805 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:51.384830 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:51.384854 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:51.396861 (XEN) Apr 23 03:24:51.396915 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:51.396960 (XEN) HPFAR_EL2: 0000009010803900 Apr 23 03:24:51.397004 (XEN) FAR_EL2: ffff800083390100 Apr 23 03:24:51.397048 (XEN) Apr 23 03:24:51.397087 (XEN) Xen stack trace from sp=0000800ffd9ffe60: Apr 23 03:24:51.408863 (XEN) 0000800ffd9ffe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:51.408927 (XEN) 000000000000004d 0000000000000000 0000000000000000 000000000001010d Apr 23 03:24:51.420863 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.420925 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.432865 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.444878 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.444940 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.456857 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.456919 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.468851 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.468914 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.480865 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.492860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.492945 (XEN) Xen call trace: Apr 23 03:24:51.493004 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:51.504895 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:51.504929 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:51.516858 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:51.516917 (XEN) Apr 23 03:24:51.516958 (XEN) *** Dumping CPU78 host state: *** Apr 23 03:24:51.517003 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:51.528856 (XEN) CPU: 78 Apr 23 03:24:51.528911 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:51.528981 (XEN) LR: 00000a000025d098 Apr 23 03:24:51.540878 (XEN) SP: 0000800ffd9f7e60 Apr 23 03:24:51.540935 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:51.540987 (XEN) X0: 0000000000000000 X1: 0000760ffdb62000 X2: 0000800ffde6a048 Apr 23 03:24:51.552768 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:51.564857 (XEN) X6: 00000a000033f5b0 X7: 0000800ffde6fa50 X8: 0000000000000012 Apr 23 03:24:51.564921 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:51.576856 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:51.576920 (XEN) X15: 0000000000000001 X16: 00000000deadbeef X17: 3062383332303030 Apr 23 03:24:51.588861 (XEN) X18: 0000000000000001 X19: 00000a000033f5b8 X20: 000000000000004e Apr 23 03:24:51.588925 (XEN) X21: 00000a0000310680 X22: 0000000000004000 X23: 000000000000004e Apr 23 03:24:51.600873 (XEN) X24: 000000000000004e X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:51.600988 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd9f7e60 Apr 23 03:24:51.612865 (XEN) Apr 23 03:24:51.612918 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:51.612962 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:51.624865 (XEN) Apr 23 03:24:51.624918 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:51.624964 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:51.625008 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:51.625052 (XEN) Apr 23 03:24:51.625091 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:51.636869 (XEN) HPFAR_EL2: 0000009010804500 Apr 23 03:24:51.636927 (XEN) FAR_EL2: ffff800083450100 Apr 23 03:24:51.636971 (XEN) Apr 23 03:24:51.637011 (XEN) Xen stack trace from sp=0000800ffd9f7e60: Apr 23 03:24:51.648861 (XEN) 0000800ffd9f7e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:51.648924 (XEN) 000000000000004e 0000000000000000 0000000000000000 000000000001010e Apr 23 03:24:51.660860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.660922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.672877 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.684772 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.684807 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.696779 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.696814 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.708792 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.708826 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.720781 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.720814 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.732773 (XEN) Xen call trace: Apr 23 03:24:51.732804 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:51.744789 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:51.744824 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:51.756764 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:51.756797 (XEN) Apr 23 03:24:51.756819 (XEN) *** Dumping CPU79 host state: *** Apr 23 03:24:51.756844 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:51.768791 (XEN) CPU: 79 Apr 23 03:24:51.768821 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:51.768848 (XEN) LR: 00000a000025d098 Apr 23 03:24:51.780764 (XEN) SP: 0000800ffd9e7e60 Apr 23 03:24:51.780795 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:51.780834 (XEN) X0: 0000000000000000 X1: 0000760ffd6e6000 X2: 0000800ffd9ee048 Apr 23 03:24:51.792864 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:51.792927 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd9ed010 X8: 0000000000000012 Apr 23 03:24:51.804864 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:51.816856 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:51.816919 (XEN) X15: 0000000000000001 X16: 00000000deadbeef X17: 3032393332303030 Apr 23 03:24:51.828871 (XEN) X18: 0000000000000001 X19: 00000a000033f5b8 X20: 000000000000004f Apr 23 03:24:51.828934 (XEN) X21: 00000a0000310700 X22: 0000000000008000 X23: 000000000000004f Apr 23 03:24:51.840861 (XEN) X24: 000000000000004f X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:51.840923 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd9e7e60 Apr 23 03:24:51.852860 (XEN) Apr 23 03:24:51.852913 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:51.852959 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:51.853002 (XEN) Apr 23 03:24:51.864853 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:51.864911 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:51.864956 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:51.865000 (XEN) Apr 23 03:24:51.865040 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:51.876865 (XEN) HPFAR_EL2: 0000009010805300 Apr 23 03:24:51.876923 (XEN) FAR_EL2: ffff800083530100 Apr 23 03:24:51.876969 (XEN) Apr 23 03:24:51.877008 (XEN) Xen stack trace from sp=0000800ffd9e7e60: Apr 23 03:24:51.888863 (XEN) 0000800ffd9e7e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:51.888926 (XEN) 000000000000004f 0000000000000000 0000000000000000 000000000001010f Apr 23 03:24:51.900860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.900923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.912859 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.912921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.924865 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.936852 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.936915 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.948854 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.948916 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.960869 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.960932 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:51.972789 (XEN) Xen call trace: Apr 23 03:24:51.972819 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:51.984766 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:51.984801 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:51.984828 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:51.996862 (XEN) Apr 23 03:24:51.996915 (XEN) *** Dumping CPU80 host state: *** Apr 23 03:24:51.996961 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:52.008874 (XEN) CPU: 80 Apr 23 03:24:52.008930 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:52.008980 (XEN) LR: 00000a000025d098 Apr 23 03:24:52.009023 (XEN) SP: 0000800ffd97fe60 Apr 23 03:24:52.020861 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:52.020925 (XEN) X0: 0000000000000000 X1: 0000760ffd6e2000 X2: 0000800ffd9ea048 Apr 23 03:24:52.032862 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:52.032943 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd9ed410 X8: 0000000000000012 Apr 23 03:24:52.044870 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:52.044932 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:52.056863 (XEN) X15: 0000000000000001 X16: 00000000deadbeef X17: 3038393332303030 Apr 23 03:24:52.068856 (XEN) X18: 0000000000000001 X19: 00000a000033f5b8 X20: 0000000000000050 Apr 23 03:24:52.068919 (XEN) X21: 00000a0000310780 X22: 0000000000010000 X23: 0000000000000050 Apr 23 03:24:52.080881 (XEN) X24: 0000000000000050 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:52.080944 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd97fe60 Apr 23 03:24:52.092876 (XEN) Apr 23 03:24:52.092929 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:52.092975 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:52.093019 (XEN) Apr 23 03:24:52.093058 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:52.104857 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:52.104916 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:52.104961 (XEN) Apr 23 03:24:52.105001 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:52.116844 (XEN) HPFAR_EL2: 0000009010805f00 Apr 23 03:24:52.116904 (XEN) FAR_EL2: ffff8000835f0100 Apr 23 03:24:52.116949 (XEN) Apr 23 03:24:52.116989 (XEN) Xen stack trace from sp=0000800ffd97fe60: Apr 23 03:24:52.117035 (XEN) 0000800ffd97fe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:52.128876 (XEN) 0000000000000050 0000000000000000 0000000000000000 0000000000010200 Apr 23 03:24:52.140854 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.140917 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.152858 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.152920 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.164860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.164922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.176856 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.188865 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.188928 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.200857 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.200919 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.212869 (XEN) Xen call trace: Apr 23 03:24:52.212925 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:52.212977 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:52.224871 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:52.224933 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:52.236870 (XEN) Apr 23 03:24:52.236922 (XEN) *** Dumping CPU81 host state: *** Apr 23 03:24:52.236968 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:52.248853 (XEN) CPU: 81 Apr 23 03:24:52.248909 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:52.248960 (XEN) LR: 00000a000025d098 Apr 23 03:24:52.249003 (XEN) SP: 0000800ffd96fe60 Apr 23 03:24:52.260856 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:52.260920 (XEN) X0: 0000000000000000 X1: 0000760ffd6e0000 X2: 0000800ffd9e8048 Apr 23 03:24:52.272891 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:52.272985 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd9ed8d0 X8: 0000000000000012 Apr 23 03:24:52.284868 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:52.284931 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:52.296878 (XEN) X15: 0000000000000001 X16: 1fffe0000508d781 X17: 0000000000000000 Apr 23 03:24:52.296942 (XEN) X18: ffff800084f2bc58 X19: 00000a000033f5b8 X20: 0000000000000051 Apr 23 03:24:52.308862 (XEN) X21: 00000a0000310800 X22: 0000000000020000 X23: 0000000000000051 Apr 23 03:24:52.320856 (XEN) X24: 0000000000000051 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:52.320920 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd96fe60 Apr 23 03:24:52.332857 (XEN) Apr 23 03:24:52.332910 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:52.332956 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:52.333001 (XEN) Apr 23 03:24:52.333040 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:52.344855 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:52.344913 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:52.344959 (XEN) Apr 23 03:24:52.344998 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:52.345041 (XEN) HPFAR_EL2: 0000008010800b00 Apr 23 03:24:52.356873 (XEN) FAR_EL2: ffff8000828b0100 Apr 23 03:24:52.356931 (XEN) Apr 23 03:24:52.356972 (XEN) Xen stack trace from sp=0000800ffd96fe60: Apr 23 03:24:52.357020 (XEN) 0000800ffd96fe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:52.368767 (XEN) 0000000000000051 0000000000000000 0000000000000000 0000000000010201 Apr 23 03:24:52.368801 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.380770 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.392764 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.392799 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.404763 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.404797 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.416766 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.416800 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.428769 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.440764 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.440798 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.452774 (XEN) Xen call trace: Apr 23 03:24:52.452804 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:52.452832 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:52.464863 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:52.464925 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:52.476868 (XEN) Apr 23 03:24:52.476922 (XEN) *** Dumping CPU82 host state: *** Apr 23 03:24:52.476969 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:52.477019 (XEN) CPU: 82 Apr 23 03:24:52.488857 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:52.488921 (XEN) LR: 00000a000025d098 Apr 23 03:24:52.488966 (XEN) SP: 0000800ffd967e60 Apr 23 03:24:52.489009 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:52.500885 (XEN) X0: 0000000000000000 X1: 0000760ffd66c000 X2: 0000800ffd974048 Apr 23 03:24:52.512859 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:52.512923 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd9edd90 X8: 0000000000000012 Apr 23 03:24:52.524857 (XEN) X9: 0000000000000080 X10: 0000000000000a10 X11: 0000000000000000 Apr 23 03:24:52.524920 (XEN) X12: 0000000000000003 X13: 0000000000000000 X14: ffff800081a1ef00 Apr 23 03:24:52.536865 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 23 03:24:52.536929 (XEN) X18: 0000000000000000 X19: 00000a000033f5b8 X20: 0000000000000052 Apr 23 03:24:52.548891 (XEN) X21: 00000a0000310880 X22: 0000000000040000 X23: 0000000000000052 Apr 23 03:24:52.548956 (XEN) X24: 0000000000000052 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:52.560861 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd967e60 Apr 23 03:24:52.572787 (XEN) Apr 23 03:24:52.572817 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:52.572842 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:52.572866 (XEN) Apr 23 03:24:52.572887 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:52.572911 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:52.584765 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:52.584797 (XEN) Apr 23 03:24:52.584819 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:52.584842 (XEN) HPFAR_EL2: 0000008010801700 Apr 23 03:24:52.596762 (XEN) FAR_EL2: ffff800082970100 Apr 23 03:24:52.596794 (XEN) Apr 23 03:24:52.596816 (XEN) Xen stack trace from sp=0000800ffd967e60: Apr 23 03:24:52.596842 (XEN) 0000800ffd967e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:52.608866 (XEN) 0000000000000052 0000000000000000 0000000000000000 0000000000010202 Apr 23 03:24:52.608900 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.620774 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.620809 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.632875 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.644859 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.644922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.656858 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.656920 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.668861 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.668923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.680863 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.692852 (XEN) Xen call trace: Apr 23 03:24:52.692908 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:52.692959 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:52.704860 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:52.704923 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:52.704970 (XEN) Apr 23 03:24:52.705010 (XEN) *** Dumping CPU83 host state: *** Apr 23 03:24:52.716889 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:52.716952 (XEN) CPU: 83 Apr 23 03:24:52.716995 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:52.728880 (XEN) LR: 00000a000025d098 Apr 23 03:24:52.728937 (XEN) SP: 0000800ffd8ffe60 Apr 23 03:24:52.728982 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:52.740876 (XEN) X0: 0000000000000000 X1: 0000760ffd668000 X2: 0000800ffd970048 Apr 23 03:24:52.740939 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:52.752866 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd973280 X8: 0000000000000012 Apr 23 03:24:52.752929 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:52.764885 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:52.776869 (XEN) X15: 00000000000001f7 X16: 1fffe0000520ba81 X17: 0000000000000000 Apr 23 03:24:52.776932 (XEN) X18: ffff800084f7bc58 X19: 00000a000033f5b8 X20: 0000000000000053 Apr 23 03:24:52.788853 (XEN) X21: 00000a0000310900 X22: 0000000000080000 X23: 0000000000000053 Apr 23 03:24:52.788915 (XEN) X24: 0000000000000053 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:52.800884 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd8ffe60 Apr 23 03:24:52.800949 (XEN) Apr 23 03:24:52.800990 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:52.812862 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:52.812920 (XEN) Apr 23 03:24:52.812960 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:52.813004 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:52.824906 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:52.824965 (XEN) Apr 23 03:24:52.825006 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:52.825051 (XEN) HPFAR_EL2: 0000008010802300 Apr 23 03:24:52.825095 (XEN) FAR_EL2: ffff800082a30100 Apr 23 03:24:52.836860 (XEN) Apr 23 03:24:52.836914 (XEN) Xen stack trace from sp=0000800ffd8ffe60: Apr 23 03:24:52.836961 (XEN) 0000800ffd8ffe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:52.848762 (XEN) 0000000000000053 0000000000000000 0000000000000000 0000000000010203 Apr 23 03:24:52.848797 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.860860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.860921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.872861 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.872923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.884857 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.896867 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.896930 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.908858 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.908920 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.920860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:52.920923 (XEN) Xen call trace: Apr 23 03:24:52.932852 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:52.932916 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:52.944772 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:52.944806 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:52.944831 (XEN) Apr 23 03:24:52.944853 (XEN) *** Dumping CPU84 host state: *** Apr 23 03:24:52.956875 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:52.956938 (XEN) CPU: 84 Apr 23 03:24:52.956980 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:52.968780 (XEN) LR: 00000a000025d098 Apr 23 03:24:52.968812 (XEN) SP: 0000800ffd8efe60 Apr 23 03:24:52.968836 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:52.980770 (XEN) X0: 0000000000000000 X1: 0000760ffd5ee000 X2: 0000800ffd8f6048 Apr 23 03:24:52.980805 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:52.992780 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd973740 X8: 0000000000000012 Apr 23 03:24:52.992815 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:53.004768 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:53.004802 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 23 03:24:53.016767 (XEN) X18: 0000000000000000 X19: 00000a000033f5b8 X20: 0000000000000054 Apr 23 03:24:53.028857 (XEN) X21: 00000a0000310980 X22: 0000000000100000 X23: 0000000000000054 Apr 23 03:24:53.028920 (XEN) X24: 0000000000000054 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:53.040883 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd8efe60 Apr 23 03:24:53.040947 (XEN) Apr 23 03:24:53.040988 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:53.052877 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:53.052937 (XEN) Apr 23 03:24:53.052979 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:53.053023 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:53.053067 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:53.064859 (XEN) Apr 23 03:24:53.064912 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:53.064957 (XEN) HPFAR_EL2: 0000008010802f00 Apr 23 03:24:53.065001 (XEN) FAR_EL2: ffff800082af0100 Apr 23 03:24:53.076856 (XEN) Apr 23 03:24:53.076910 (XEN) Xen stack trace from sp=0000800ffd8efe60: Apr 23 03:24:53.076958 (XEN) 0000800ffd8efe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:53.088844 (XEN) 0000000000000054 0000000000000000 0000000000000000 0000000000010204 Apr 23 03:24:53.088908 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.100856 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.100919 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.112860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.112922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.124859 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.124921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.139084 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.151081 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.151081 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.163040 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.163040 (XEN) Xen call trace: Apr 23 03:24:53.163040 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:53.175012 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:53.175012 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:53.187014 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:53.187014 (XEN) Apr 23 03:24:53.187014 (XEN) *** Dumping CPU85 host state: *** Apr 23 03:24:53.199069 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:53.199069 (XEN) CPU: 85 Apr 23 03:24:53.199069 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:53.211084 (XEN) LR: 00000a000025d098 Apr 23 03:24:53.211084 (XEN) SP: 0000800ffd8e7e60 Apr 23 03:24:53.211084 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:53.223088 (XEN) X0: 0000000000000000 X1: 0000760ffd5ea000 X2: 0000800ffd8f2048 Apr 23 03:24:53.223088 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:53.235174 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd973c00 X8: 0000000000000012 Apr 23 03:24:53.235248 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:53.247081 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:53.247081 (XEN) X15: 0000000000000000 X16: 1fffe0000534dce1 X17: 0000000000000000 Apr 23 03:24:53.259089 (XEN) X18: ffff800085aabc58 X19: 00000a000033f5b8 X20: 0000000000000055 Apr 23 03:24:53.259089 (XEN) X21: 00000a0000310a00 X22: 0000000000200000 X23: 0000000000000055 Apr 23 03:24:53.271086 (XEN) X24: 0000000000000055 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:53.283067 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd8e7e60 Apr 23 03:24:53.283067 (XEN) Apr 23 03:24:53.283067 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:53.283067 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:53.295077 (XEN) Apr 23 03:24:53.295077 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:53.295077 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:53.295077 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:53.307031 (XEN) Apr 23 03:24:53.307031 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:53.307031 (XEN) HPFAR_EL2: 0000008010000200 Apr 23 03:24:53.307031 (XEN) FAR_EL2: ffff800082680090 Apr 23 03:24:53.307031 (XEN) Apr 23 03:24:53.307031 (XEN) Xen stack trace from sp=0000800ffd8e7e60: Apr 23 03:24:53.319033 (XEN) 0000800ffd8e7e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:53.319033 (XEN) 0000000000000055 0000000000000000 0000000000000000 0000000000010205 Apr 23 03:24:53.331032 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.343027 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.343027 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.355051 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.355051 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.367086 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.367086 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.379081 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.379081 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.391081 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.403080 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.403080 (XEN) Xen call trace: Apr 23 03:24:53.403080 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:53.415084 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:53.415084 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:53.427083 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:53.427083 (XEN) Apr 23 03:24:53.427083 (XEN) *** Dumping CPU86 host state: *** Apr 23 03:24:53.427083 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:53.439052 (XEN) CPU: 86 Apr 23 03:24:53.439052 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:53.439052 (XEN) LR: 00000a000025d098 Apr 23 03:24:53.451083 (XEN) SP: 0000800ffd877e60 Apr 23 03:24:53.451083 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:53.451083 (XEN) X0: 0000000000000000 X1: 0000760ffd5e8000 X2: 0000800ffd8f0048 Apr 23 03:24:53.463082 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:53.475083 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd87e150 X8: 0000000000000012 Apr 23 03:24:53.475083 (XEN) X9: 0000000000000080 X10: 0000000000000a10 X11: 0000000000000000 Apr 23 03:24:53.487079 (XEN) X12: 0000000000000001 X13: 000000000000038c X14: 000000000000038c Apr 23 03:24:53.487079 (XEN) X15: 00003d0900000000 X16: 0000000000000000 X17: 0000000000000000 Apr 23 03:24:53.499082 (XEN) X18: 0000000000000001 X19: 00000a000033f5b8 X20: 0000000000000056 Apr 23 03:24:53.499082 (XEN) X21: 00000a0000310a80 X22: 0000000000400000 X23: 0000000000000056 Apr 23 03:24:53.511086 (XEN) X24: 0000000000000056 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:53.511086 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd877e60 Apr 23 03:24:53.523055 (XEN) Apr 23 03:24:53.523055 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:53.523055 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:53.535039 (XEN) Apr 23 03:24:53.535039 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:53.535039 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:53.535039 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:53.535039 (XEN) Apr 23 03:24:53.547084 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:53.547084 (XEN) HPFAR_EL2: 0000008010804700 Apr 23 03:24:53.547084 (XEN) FAR_EL2: ffff800082c70100 Apr 23 03:24:53.547084 (XEN) Apr 23 03:24:53.547084 (XEN) Xen stack trace from sp=0000800ffd877e60: Apr 23 03:24:53.559087 (XEN) 0000800ffd877e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:53.559087 (XEN) 0000000000000056 0000000000000000 0000000000000000 0000000000010206 Apr 23 03:24:53.571043 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.571043 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.583085 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.594975 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.594975 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.607051 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.607051 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.619064 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.619064 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.631073 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.631073 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.643082 (XEN) Xen call trace: Apr 23 03:24:53.643082 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:53.655088 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:53.655088 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:53.667080 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:53.667080 (XEN) Apr 23 03:24:53.667080 (XEN) *** Dumping CPU87 host state: *** Apr 23 03:24:53.667080 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:53.679087 (XEN) CPU: 87 Apr 23 03:24:53.679087 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:53.679087 (XEN) LR: 00000a000025d098 Apr 23 03:24:53.691178 (XEN) SP: 0000800ffd86fe60 Apr 23 03:24:53.691240 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:53.691291 (XEN) X0: 0000000000000000 X1: 0000760ffd574000 X2: 0000800ffd87c048 Apr 23 03:24:53.703084 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:53.703084 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd87e590 X8: 0000000000000012 Apr 23 03:24:53.715054 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:53.727021 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:53.727021 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 23 03:24:53.739021 (XEN) X18: 0000000000000000 X19: 00000a000033f5b8 X20: 0000000000000057 Apr 23 03:24:53.739021 (XEN) X21: 00000a0000310b00 X22: 0000000000800000 X23: 0000000000000057 Apr 23 03:24:53.751028 (XEN) X24: 0000000000000057 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:53.751028 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd86fe60 Apr 23 03:24:53.763017 (XEN) Apr 23 03:24:53.763017 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:53.763017 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:53.763017 (XEN) Apr 23 03:24:53.775018 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:53.775018 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:53.775018 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:53.775018 (XEN) Apr 23 03:24:53.775018 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:53.787082 (XEN) HPFAR_EL2: 0000008010805300 Apr 23 03:24:53.787082 (XEN) FAR_EL2: ffff800082d30100 Apr 23 03:24:53.787082 (XEN) Apr 23 03:24:53.787082 (XEN) Xen stack trace from sp=0000800ffd86fe60: Apr 23 03:24:53.799084 (XEN) 0000800ffd86fe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:53.799084 (XEN) 0000000000000057 0000000000000000 0000000000000000 0000000000010207 Apr 23 03:24:53.811089 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.811089 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.823057 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.823057 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.835081 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.847065 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.847065 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.859078 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.859078 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.871080 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.871080 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:53.883085 (XEN) Xen call trace: Apr 23 03:24:53.883085 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:53.895081 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:53.895081 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:53.895081 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:53.907011 (XEN) Apr 23 03:24:53.907011 (XEN) *** Dumping CPU88 host state: *** Apr 23 03:24:53.907011 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:53.918976 (XEN) CPU: 88 Apr 23 03:24:53.918976 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:53.918976 (XEN) LR: 00000a000025d098 Apr 23 03:24:53.918976 (XEN) SP: 0000800ffd867e60 Apr 23 03:24:53.931011 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:53.931011 (XEN) X0: 0000000000000000 X1: 0000760ffd570000 X2: 0000800ffd878048 Apr 23 03:24:53.943044 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:53.943044 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd87ea50 X8: 0000000000000012 Apr 23 03:24:53.955044 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:53.955044 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:53.967044 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 23 03:24:53.979048 (XEN) X18: 0000000000000000 X19: 00000a000033f5b8 X20: 0000000000000058 Apr 23 03:24:53.979048 (XEN) X21: 00000a0000310b80 X22: 0000000001000000 X23: 0000000000000058 Apr 23 03:24:53.991058 (XEN) X24: 0000000000000058 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:53.991058 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd867e60 Apr 23 03:24:54.003084 (XEN) Apr 23 03:24:54.003084 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:54.003084 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:54.003084 (XEN) Apr 23 03:24:54.003084 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:54.015083 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:54.015083 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:54.015083 (XEN) Apr 23 03:24:54.015083 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:54.027080 (XEN) HPFAR_EL2: 0000008010805f00 Apr 23 03:24:54.027080 (XEN) FAR_EL2: ffff800082df0100 Apr 23 03:24:54.027080 (XEN) Apr 23 03:24:54.027080 (XEN) Xen stack trace from sp=0000800ffd867e60: Apr 23 03:24:54.027080 (XEN) 0000800ffd867e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:54.039060 (XEN) 0000000000000058 0000000000000000 0000000000000000 0000000000010208 Apr 23 03:24:54.051046 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.051046 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.063048 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.063048 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.075052 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.075052 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.087045 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.099083 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.099083 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.111039 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.111039 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.122973 (XEN) Xen call trace: Apr 23 03:24:54.122973 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:54.122973 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:54.134958 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:54.134958 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:54.146957 (XEN) Apr 23 03:24:54.146957 (XEN) *** Dumping CPU89 host state: *** Apr 23 03:24:54.146957 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:54.158956 (XEN) CPU: 89 Apr 23 03:24:54.158956 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:54.158956 (XEN) LR: 00000a000025d098 Apr 23 03:24:54.158956 (XEN) SP: 0000800ffd817e60 Apr 23 03:24:54.171041 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:54.171041 (XEN) X0: 0000000000000000 X1: 0000760ffd516000 X2: 0000800ffd81e048 Apr 23 03:24:54.183049 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:54.183049 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd81c010 X8: 0000000000000012 Apr 23 03:24:54.195055 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:54.195055 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:54.207048 (XEN) X15: 0000000000000200 X16: 0000000000000000 X17: 0000000000000000 Apr 23 03:24:54.207048 (XEN) X18: 0000000000000000 X19: 00000a000033f5b8 X20: 0000000000000059 Apr 23 03:24:54.219087 (XEN) X21: 00000a0000310c00 X22: 0000000002000000 X23: 0000000000000059 Apr 23 03:24:54.231029 (XEN) X24: 0000000000000059 X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:54.231029 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd817e60 Apr 23 03:24:54.243014 (XEN) Apr 23 03:24:54.243014 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:54.243014 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:54.243014 (XEN) Apr 23 03:24:54.243014 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:54.255044 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:54.255044 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:54.255044 (XEN) Apr 23 03:24:54.255044 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:54.255044 (XEN) HPFAR_EL2: 0000009010800b00 Apr 23 03:24:54.267040 (XEN) FAR_EL2: ffff8000830b0100 Apr 23 03:24:54.267040 (XEN) Apr 23 03:24:54.267040 (XEN) Xen stack trace from sp=0000800ffd817e60: Apr 23 03:24:54.267040 (XEN) 0000800ffd817e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:54.279040 (XEN) 0000000000000059 0000000000000000 0000000000000000 0000000000010209 Apr 23 03:24:54.279040 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.291043 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.303047 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.303047 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.315078 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.315078 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.327047 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.327047 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.339017 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.350989 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.350989 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.362959 (XEN) Xen call trace: Apr 23 03:24:54.362959 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:54.362959 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:54.375017 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:54.375017 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:54.387016 (XEN) Apr 23 03:24:54.387016 (XEN) *** Dumping CPU90 host state: *** Apr 23 03:24:54.387016 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:54.387016 (XEN) CPU: 90 Apr 23 03:24:54.399018 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:54.399018 (XEN) LR: 00000a000025d098 Apr 23 03:24:54.399018 (XEN) SP: 0000800ffd80fe60 Apr 23 03:24:54.399018 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:54.411084 (XEN) X0: 0000000000000000 X1: 0000760ffd512000 X2: 0000800ffd81a048 Apr 23 03:24:54.423076 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:54.423076 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd81c410 X8: 0000000000000012 Apr 23 03:24:54.435074 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:54.435074 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:54.447079 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 23 03:24:54.447079 (XEN) X18: 0000000000000000 X19: 00000a000033f5b8 X20: 000000000000005a Apr 23 03:24:54.459074 (XEN) X21: 00000a0000310c80 X22: 0000000004000000 X23: 000000000000005a Apr 23 03:24:54.459074 (XEN) X24: 000000000000005a X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:54.471073 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd80fe60 Apr 23 03:24:54.483079 (XEN) Apr 23 03:24:54.483079 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:54.483079 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:54.483079 (XEN) Apr 23 03:24:54.483079 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:54.483079 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:54.495084 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:54.495084 (XEN) Apr 23 03:24:54.495084 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:54.495084 (XEN) HPFAR_EL2: 0000009010801700 Apr 23 03:24:54.507083 (XEN) FAR_EL2: ffff800083170100 Apr 23 03:24:54.507083 (XEN) Apr 23 03:24:54.507083 (XEN) Xen stack trace from sp=0000800ffd80fe60: Apr 23 03:24:54.507083 (XEN) 0000800ffd80fe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:54.519029 (XEN) 000000000000005a 0000000000000000 0000000000000000 000000000001020a Apr 23 03:24:54.519029 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.531084 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.531084 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.543082 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.555079 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.555079 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.567082 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.567082 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.579083 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.579083 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.591073 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.603081 (XEN) Xen call trace: Apr 23 03:24:54.603081 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:54.603081 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:54.615086 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:54.615086 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:54.615086 (XEN) Apr 23 03:24:54.627083 (XEN) *** Dumping CPU91 host state: *** Apr 23 03:24:54.627083 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:54.627083 (XEN) CPU: 91 Apr 23 03:24:54.627083 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:54.639081 (XEN) LR: 00000a000025d098 Apr 23 03:24:54.639081 (XEN) SP: 0000800feb79fe60 Apr 23 03:24:54.639081 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:54.651081 (XEN) X0: 0000000000000000 X1: 0000760ffd4fe000 X2: 0000800ffd806048 Apr 23 03:24:54.651081 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:54.663083 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd81c8d0 X8: 0000000000000012 Apr 23 03:24:54.675064 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:54.675064 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:54.686999 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 23 03:24:54.686999 (XEN) X18: 0000000000000000 X19: 00000a000033f5b8 X20: 000000000000005b Apr 23 03:24:54.699094 (XEN) X21: 00000a0000310d00 X22: 0000000008000000 X23: 000000000000005b Apr 23 03:24:54.699162 (XEN) X24: 000000000000005b X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:54.710995 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800feb79fe60 Apr 23 03:24:54.710995 (XEN) Apr 23 03:24:54.710995 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:54.723050 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:54.723050 (XEN) Apr 23 03:24:54.723050 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:54.723050 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:54.735037 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:54.735037 (XEN) Apr 23 03:24:54.735037 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:54.735037 (XEN) HPFAR_EL2: 0000009010802300 Apr 23 03:24:54.735037 (XEN) FAR_EL2: ffff800083230100 Apr 23 03:24:54.747036 (XEN) Apr 23 03:24:54.747036 (XEN) Xen stack trace from sp=0000800feb79fe60: Apr 23 03:24:54.747036 (XEN) 0000800feb79fe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:54.759082 (XEN) 000000000000005b 0000000000000000 0000000000000000 000000000001020b Apr 23 03:24:54.759082 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.771076 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.771076 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.783076 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.783076 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.795080 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.807084 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.807084 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.819087 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.819087 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.831076 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:54.831076 (XEN) Xen call trace: Apr 23 03:24:54.843084 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:54.843084 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:54.855050 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:54.855050 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:54.855050 (XEN) Apr 23 03:24:54.855050 (XEN) *** Dumping CPU92 host state: *** Apr 23 03:24:54.867018 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:54.867018 (XEN) CPU: 92 Apr 23 03:24:54.867018 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:54.879030 (XEN) LR: 00000a000025d098 Apr 23 03:24:54.879030 (XEN) SP: 0000800feb797e60 Apr 23 03:24:54.879030 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:54.891021 (XEN) X0: 0000000000000000 X1: 0000760ffd4fc000 X2: 0000800ffd804048 Apr 23 03:24:54.891021 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:54.903040 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd81cd90 X8: 0000000000000012 Apr 23 03:24:54.903040 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:54.915070 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:54.927081 (XEN) X15: 0000000000000001 X16: 00000000deadbeef X17: 3030383332303030 Apr 23 03:24:54.927081 (XEN) X18: 0000000000000001 X19: 00000a000033f5b8 X20: 000000000000005c Apr 23 03:24:54.939082 (XEN) X21: 00000a0000310d80 X22: 0000000010000000 X23: 000000000000005c Apr 23 03:24:54.939082 (XEN) X24: 000000000000005c X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:54.951083 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800feb797e60 Apr 23 03:24:54.951083 (XEN) Apr 23 03:24:54.951083 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:54.963077 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:54.963077 (XEN) Apr 23 03:24:54.963077 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:54.963077 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:54.963077 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:54.975076 (XEN) Apr 23 03:24:54.975076 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:54.975076 (XEN) HPFAR_EL2: 0000009010802f00 Apr 23 03:24:54.975076 (XEN) FAR_EL2: ffff8000832f0100 Apr 23 03:24:54.987076 (XEN) Apr 23 03:24:54.987076 (XEN) Xen stack trace from sp=0000800feb797e60: Apr 23 03:24:54.987076 (XEN) 0000800feb797e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:54.999184 (XEN) 000000000000005c 0000000000000000 0000000000000000 000000000001020c Apr 23 03:24:54.999252 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.011090 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.011090 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.023045 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.023045 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.035048 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.035048 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.047076 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.059077 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.059077 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.071050 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.071050 (XEN) Xen call trace: Apr 23 03:24:55.071050 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:55.083079 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:55.083079 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:55.095084 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:55.095084 (XEN) Apr 23 03:24:55.095084 (XEN) *** Dumping CPU93 host state: *** Apr 23 03:24:55.107074 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:55.107074 (XEN) CPU: 93 Apr 23 03:24:55.107074 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:55.119029 (XEN) LR: 00000a000025d098 Apr 23 03:24:55.119029 (XEN) SP: 0000800feb787e60 Apr 23 03:24:55.119029 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:55.130996 (XEN) X0: 0000000000000000 X1: 0000760ffd4f8000 X2: 0000800ffd800048 Apr 23 03:24:55.130996 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:55.143030 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd802280 X8: 0000000000000012 Apr 23 03:24:55.143030 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:55.155030 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:55.155030 (XEN) X15: 0000000000000001 X16: 00000000deadbeef X17: 3036383332303030 Apr 23 03:24:55.167033 (XEN) X18: 0000000000000001 X19: 00000a000033f5b8 X20: 000000000000005d Apr 23 03:24:55.167033 (XEN) X21: 00000a0000310e00 X22: 0000000020000000 X23: 000000000000005d Apr 23 03:24:55.179072 (XEN) X24: 000000000000005d X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:55.191063 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800feb787e60 Apr 23 03:24:55.191063 (XEN) Apr 23 03:24:55.191063 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:55.191063 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:55.203072 (XEN) Apr 23 03:24:55.203072 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:55.203072 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:55.203072 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:55.215042 (XEN) Apr 23 03:24:55.215042 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:55.215042 (XEN) HPFAR_EL2: 0000009010803b00 Apr 23 03:24:55.215042 (XEN) FAR_EL2: ffff8000833b0100 Apr 23 03:24:55.215042 (XEN) Apr 23 03:24:55.215042 (XEN) Xen stack trace from sp=0000800feb787e60: Apr 23 03:24:55.227076 (XEN) 0000800feb787e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:55.227076 (XEN) 000000000000005d 0000000000000000 0000000000000000 000000000001020d Apr 23 03:24:55.239072 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.251082 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.251082 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.263092 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.263159 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.275146 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.275203 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.284874 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.284941 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.296827 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.310277 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.310277 (XEN) Xen call trace: Apr 23 03:24:55.310277 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:55.321186 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:55.321186 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:55.335121 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:55.335185 (XEN) Apr 23 03:24:55.335227 (XEN) *** Dumping CPU94 host state: *** Apr 23 03:24:55.335274 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:55.346179 (XEN) CPU: 94 Apr 23 03:24:55.346179 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:55.346179 (XEN) LR: 00000a000025d098 Apr 23 03:24:55.358479 (XEN) SP: 0000800feb71fe60 Apr 23 03:24:55.358479 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:55.358479 (XEN) X0: 0000000000000000 X1: 0000760feb484000 X2: 0000800feb78c048 Apr 23 03:24:55.370845 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:55.383004 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd802740 X8: 0000000000000012 Apr 23 03:24:55.383004 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:55.393018 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:55.393079 (XEN) X15: 0000000000000001 X16: 00000000deadbeef X17: 3063383332303030 Apr 23 03:24:55.404863 (XEN) X18: 0000000000000001 X19: 00000a000033f5b8 X20: 000000000000005e Apr 23 03:24:55.404927 (XEN) X21: 00000a0000310e80 X22: 0000000040000000 X23: 000000000000005e Apr 23 03:24:55.416854 (XEN) X24: 000000000000005e X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:55.416917 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800feb71fe60 Apr 23 03:24:55.428862 (XEN) Apr 23 03:24:55.428916 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:55.428961 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:55.443129 (XEN) Apr 23 03:24:55.443204 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:55.443254 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:55.443299 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:55.443343 (XEN) Apr 23 03:24:55.455227 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:55.455282 (XEN) HPFAR_EL2: 0000009010804700 Apr 23 03:24:55.455328 (XEN) FAR_EL2: ffff800083470100 Apr 23 03:24:55.455372 (XEN) Apr 23 03:24:55.455412 (XEN) Xen stack trace from sp=0000800feb71fe60: Apr 23 03:24:55.464879 (XEN) 0000800feb71fe70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:55.464948 (XEN) 000000000000005e 0000000000000000 0000000000000000 000000000001020e Apr 23 03:24:55.476842 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.476905 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.488866 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.503131 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.503206 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.515115 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.515176 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.527128 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.527184 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.539114 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.539170 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.551117 (XEN) Xen call trace: Apr 23 03:24:55.551166 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:55.561001 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:55.561093 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:55.575033 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:55.575033 (XEN) Apr 23 03:24:55.575033 (XEN) *** Dumping CPU95 host state: *** Apr 23 03:24:55.575033 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 23 03:24:55.584889 (XEN) CPU: 95 Apr 23 03:24:55.584945 (XEN) PC: 00000a000025d0b4 domain.c#idle_loop+0x128/0x190 Apr 23 03:24:55.584995 (XEN) LR: 00000a000025d098 Apr 23 03:24:55.596894 (XEN) SP: 0000800feb717e60 Apr 23 03:24:55.596952 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 23 03:24:55.597004 (XEN) X0: 0000000000000000 X1: 0000760feb482000 X2: 0000800feb78a048 Apr 23 03:24:55.608865 (XEN) X3: ffffffffffffff92 X4: 0000000000000000 X5: 00000a000033f5a8 Apr 23 03:24:55.608928 (XEN) X6: 00000a000033f5b0 X7: 0000800ffd802c00 X8: 0000000000000012 Apr 23 03:24:55.620853 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 23 03:24:55.632837 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 23 03:24:55.635122 (XEN) X15: 0000000000000001 X16: 00000000deadbeef X17: 3031393332303030 Apr 23 03:24:55.644854 (XEN) X18: 0000000000000001 X19: 00000a000033f5b8 X20: 000000000000005f Apr 23 03:24:55.644918 (XEN) X21: 00000a0000310f00 X22: 0000000080000000 X23: 000000000000005f Apr 23 03:24:55.656855 (XEN) X24: 000000000000005f X25: 0000000000000000 X26: 0000000000000000 Apr 23 03:24:55.656918 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800feb717e60 Apr 23 03:24:55.675034 (XEN) Apr 23 03:24:55.675034 (XEN) VTCR_EL2: 00000000800d3590 Apr 23 03:24:55.675034 (XEN) VTTBR_EL2: 00010107eb706000 Apr 23 03:24:55.675034 (XEN) Apr 23 03:24:55.675034 (XEN) SCTLR_EL2: 0000000030cd183d Apr 23 03:24:55.675034 (XEN) HCR_EL2: 00000000807c663f Apr 23 03:24:55.684842 (XEN) TTBR0_EL2: 000001071e3fd000 Apr 23 03:24:55.684899 (XEN) Apr 23 03:24:55.684940 (XEN) ESR_EL2: 0000000007e00000 Apr 23 03:24:55.684985 (XEN) HPFAR_EL2: 0000009010805100 Apr 23 03:24:55.699014 (XEN) FAR_EL2: ffff800083510100 Apr 23 03:24:55.699014 (XEN) Apr 23 03:24:55.699014 (XEN) Xen stack trace from sp=0000800feb717e60: Apr 23 03:24:55.699014 (XEN) 0000800feb717e70 00000a0000269890 00000a0000309320 00000a000033f5d8 Apr 23 03:24:55.710736 (XEN) 000000000000005f 0000000000000000 0000000000000000 000000000001020f Apr 23 03:24:55.710736 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.722816 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.734650 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.734650 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.747133 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.747208 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.759098 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.759155 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.771064 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.771121 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.782991 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 23 03:24:55.795070 (XEN) Xen call trace: Apr 23 03:24:55.795120 (XEN) [<00000a000025d0b4>] domain.c#idle_loop+0x128/0x190 (PC) Apr 23 03:24:55.795171 (XEN) [<00000a000025d098>] domain.c#idle_loop+0x10c/0x190 (LR) Apr 23 03:24:55.807075 (XEN) [<00000a0000269890>] start_secondary+0x21c/0x220 Apr 23 03:24:55.807131 (XEN) [<00000a000033f5d8>] 00000a000033f5d8 Apr 23 03:24:55.807177 (XEN) Apr 23 03:24:55.818999 Apr 23 03:25:01.662388 (XEN) 'q' pressed -> dumping domain info (now = 89616703040) Apr 23 03:25:01.687206 (XEN) General information for domain 0: Apr 23 03:25:01.687206 (XEN) refcnt=3 dying=0 pau Apr 23 03:25:01.689490 se_count=0 Apr 23 03:25:01.698961 (XEN) nr_pages=131072 xenheap_pages=2 dirty_cpus={} max_pages=131072 Apr 23 03:25:01.698961 (XEN) handle=00000000-0000-0000-0000-000000000000 vm_assist=00000020 Apr 23 03:25:01.711027 (XEN) p2m mappings for domain 0 (vmid 1): Apr 23 03:25:01.711027 (XEN) 1G mappings: 4984 (shattered 3) Apr 23 03:25:01.711027 (XEN) 2M mappings: 1444547 (shattered 3) Apr 23 03:25:01.721394 (XEN) 4K mappings: 1552 Apr 23 03:25:01.721456 (XEN) Rangesets belonging to domain 0: Apr 23 03:25:01.721502 (XEN) Interrupts { 32, 38, 48-51 } Apr 23 03:25:01.721547 (XEN) I/O Memory { 802000000-808000000, 810000000-820000000, 838000000-844000000, 846000000-848002000, 849000000-849002000, 84a000000-84a002000, 84b000000-84b002000, 868000000-880000000, 88001f000-880058000, 881010000-883000010, 902000000-908000000, 910000000-920000000, 938000000-944000000, 946000000-948002000, 949000000-949002000, 94a000000-94a002000, 94b000000-94b002000, 968000000-980000000 } Apr 23 03:25:01.763030 (XEN) NODE affinity for domain 0: [0] Apr 23 03:25:01.763062 (XEN) VCPU information and callbacks for domain 0: Apr 23 03:25:01.775195 (XEN) UNIT0 affinities: hard={0-95} soft={0-95} Apr 23 03:25:01.775255 (XEN) VCPU0: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:01.775306 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:01.787159 (XEN) GICH_LRs (vcpu 0) mask=0 Apr 23 03:25:01.787217 (XEN) VCPU_LR[0]=0 Apr 23 03:25:01.787260 (XEN) VCPU_LR[1]=0 Apr 23 03:25:01.787301 (XEN) VCPU_LR[2]=0 Apr 23 03:25:01.787342 (XEN) VCPU_LR[3]=0 Apr 23 03:25:01.799118 (XEN) VCPU_LR[4]=0 Apr 23 03:25:01.799174 (XEN) VCPU_LR[5]=0 Apr 23 03:25:01.799216 (XEN) VCPU_LR[6]=0 Apr 23 03:25:01.799257 (XEN) VCPU_LR[7]=0 Apr 23 03:25:01.799298 (XEN) VCPU_LR[8]=0 Apr 23 03:25:01.811115 (XEN) VCPU_LR[9]=0 Apr 23 03:25:01.811171 (XEN) VCPU_LR[10]=0 Apr 23 03:25:01.811214 (XEN) VCPU_LR[11]=0 Apr 23 03:25:01.811254 (XEN) VCPU_LR[12]=0 Apr 23 03:25:01.811295 (XEN) VCPU_LR[13]=0 Apr 23 03:25:01.811335 (XEN) VCPU_LR[14]=0 Apr 23 03:25:01.823136 (XEN) VCPU_LR[15]=0 Apr 23 03:25:01.823191 (XEN) No periodic timer Apr 23 03:25:01.823234 (XEN) UNIT1 affinities: hard={0-95} soft={0-95} Apr 23 03:25:01.823281 (XEN) VCPU1: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:01.835136 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:01.835194 (XEN) GICH_LRs (vcpu 1) mask=0 Apr 23 03:25:01.835239 (XEN) VCPU_LR[0]=0 Apr 23 03:25:01.847074 (XEN) VCPU_LR[1]=0 Apr 23 03:25:01.847074 (XEN) VCPU_LR[2]=0 Apr 23 03:25:01.847074 (XEN) VCPU_LR[3]=0 Apr 23 03:25:01.847074 (XEN) VCPU_LR[4]=0 Apr 23 03:25:01.847074 (XEN) VCPU_LR[5]=0 Apr 23 03:25:01.847074 (XEN) VCPU_LR[6]=0 Apr 23 03:25:01.859058 (XEN) VCPU_LR[7]=0 Apr 23 03:25:01.859094 (XEN) VCPU_LR[8]=0 Apr 23 03:25:01.859117 (XEN) VCPU_LR[9]=0 Apr 23 03:25:01.859140 (XEN) VCPU_LR[10]=0 Apr 23 03:25:01.859189 (XEN) VCPU_LR[11]=0 Apr 23 03:25:01.859230 (XEN) VCPU_LR[12]=0 Apr 23 03:25:01.871129 (XEN) VCPU_LR[13]=0 Apr 23 03:25:01.871185 (XEN) VCPU_LR[14]=0 Apr 23 03:25:01.871228 (XEN) VCPU_LR[15]=0 Apr 23 03:25:01.871269 (XEN) No periodic timer Apr 23 03:25:01.871311 (XEN) UNIT2 affinities: hard={0-95} soft={0-95} Apr 23 03:25:01.883160 (XEN) VCPU2: CPU34 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:01.883225 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:01.883271 (XEN) GICH_LRs (vcpu 2) mask=0 Apr 23 03:25:01.895163 (XEN) VCPU_LR[0]=0 Apr 23 03:25:01.895218 (XEN) VCPU_LR[1]=0 Apr 23 03:25:01.895261 (XEN) VCPU_LR[2]=0 Apr 23 03:25:01.895302 (XEN) VCPU_LR[3]=0 Apr 23 03:25:01.895343 (XEN) VCPU_LR[4]=0 Apr 23 03:25:01.895383 (XEN) VCPU_LR[5]=0 Apr 23 03:25:01.907154 (XEN) VCPU_LR[6]=0 Apr 23 03:25:01.907229 (XEN) VCPU_LR[7]=0 Apr 23 03:25:01.907274 (XEN) VCPU_LR[8]=0 Apr 23 03:25:01.907316 (XEN) VCPU_LR[9]=0 Apr 23 03:25:01.907356 (XEN) VCPU_LR[10]=0 Apr 23 03:25:01.919144 (XEN) VCPU_LR[11]=0 Apr 23 03:25:01.919202 (XEN) VCPU_LR[12]=0 Apr 23 03:25:01.919246 (XEN) VCPU_LR[13]=0 Apr 23 03:25:01.919287 (XEN) VCPU_LR[14]=0 Apr 23 03:25:01.919328 (XEN) VCPU_LR[15]=0 Apr 23 03:25:01.931153 (XEN) No periodic timer Apr 23 03:25:01.931210 (XEN) UNIT3 affinities: hard={0-95} soft={0-95} Apr 23 03:25:01.931259 (XEN) VCPU3: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:01.943167 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:01.943226 (XEN) GICH_LRs (vcpu 3) mask=0 Apr 23 03:25:01.943271 (XEN) VCPU_LR[0]=0 Apr 23 03:25:01.943313 (XEN) VCPU_LR[1]=0 Apr 23 03:25:01.943354 (XEN) VCPU_LR[2]=0 Apr 23 03:25:01.955171 (XEN) VCPU_LR[3]=0 Apr 23 03:25:01.955227 (XEN) VCPU_LR[4]=0 Apr 23 03:25:01.955270 (XEN) VCPU_LR[5]=0 Apr 23 03:25:01.955311 (XEN) VCPU_LR[6]=0 Apr 23 03:25:01.955353 (XEN) VCPU_LR[7]=0 Apr 23 03:25:01.955394 (XEN) VCPU_LR[8]=0 Apr 23 03:25:01.967135 (XEN) VCPU_LR[9]=0 Apr 23 03:25:01.967196 (XEN) VCPU_LR[10]=0 Apr 23 03:25:01.967239 (XEN) VCPU_LR[11]=0 Apr 23 03:25:01.967291 (XEN) VCPU_LR[12]=0 Apr 23 03:25:01.967335 (XEN) VCPU_LR[13]=0 Apr 23 03:25:01.967376 (XEN) VCPU_LR[14]=0 Apr 23 03:25:01.979070 (XEN) VCPU_LR[15]=0 Apr 23 03:25:01.979127 (XEN) No periodic timer Apr 23 03:25:01.979170 (XEN) UNIT4 affinities: hard={0-95} soft={0-95} Apr 23 03:25:01.979217 (XEN) VCPU4: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:01.991049 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:01.991099 (XEN) GICH_LRs (vcpu 4) mask=0 Apr 23 03:25:01.991142 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.003170 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.003228 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.003271 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.003312 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.003353 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.003394 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.015153 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.015209 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.015252 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.015293 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.015335 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.015376 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.027163 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.027220 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.027263 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.027304 (XEN) No periodic timer Apr 23 03:25:02.027346 (XEN) UNIT5 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.039156 (XEN) VCPU5: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.039220 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.039266 (XEN) GICH_LRs (vcpu 5) mask=0 Apr 23 03:25:02.051147 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.051203 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.051246 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.051287 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.051329 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.063165 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.063221 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.063264 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.063306 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.063347 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.063388 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.075157 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.075213 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.075256 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.075297 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.075339 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.075379 (XEN) No periodic timer Apr 23 03:25:02.087163 (XEN) UNIT6 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.087224 (XEN) VCPU6: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.099164 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.099223 (XEN) GICH_LRs (vcpu 6) mask=0 Apr 23 03:25:02.099269 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.099310 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.099351 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.111178 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.111235 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.111278 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.111320 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.111361 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.111401 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.123167 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.123223 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.123266 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.123319 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.123342 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.123364 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.135157 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.135212 (XEN) No periodic timer Apr 23 03:25:02.135256 (XEN) UNIT7 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.135303 (XEN) VCPU7: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.147081 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.147140 (XEN) GICH_LRs (vcpu 7) mask=0 Apr 23 03:25:02.147190 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.147233 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.159095 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.159142 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.159183 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.159225 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.159266 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.159307 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.171109 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.171169 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.171213 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.171258 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.171300 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.183104 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.183159 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.183202 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.183244 (XEN) No periodic timer Apr 23 03:25:02.183286 (XEN) UNIT8 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.195174 (XEN) VCPU8: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.195242 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.207138 (XEN) GICH_LRs (vcpu 8) mask=0 Apr 23 03:25:02.207190 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.207232 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.207273 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.207314 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.207355 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.219111 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.219160 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.219202 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.219244 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.219285 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.219326 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.231129 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.231185 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.231228 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.231270 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.231311 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.231352 (XEN) No periodic timer Apr 23 03:25:02.243130 (XEN) UNIT9 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.243191 (XEN) VCPU9: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.255135 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.255195 (XEN) GICH_LRs (vcpu 9) mask=0 Apr 23 03:25:02.255241 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.255283 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.255325 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.267129 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.267186 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.267229 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.267272 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.267312 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.267353 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.279136 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.279192 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.279236 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.279277 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.279319 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.279360 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.291130 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.291186 (XEN) No periodic timer Apr 23 03:25:02.291230 (XEN) UNIT10 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.291277 (XEN) VCPU10: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.303137 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.303214 (XEN) GICH_LRs (vcpu 10) mask=0 Apr 23 03:25:02.303261 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.315133 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.315189 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.315231 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.315272 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.315313 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.315353 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.327129 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.327184 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.327227 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.327269 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.327310 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.327351 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.339131 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.339187 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.339229 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.339271 (XEN) No periodic timer Apr 23 03:25:02.339314 (XEN) UNIT11 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.351159 (XEN) VCPU11: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.351223 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.363017 (XEN) GICH_LRs (vcpu 11) mask=0 Apr 23 03:25:02.363049 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.363073 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.363095 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.363118 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.363140 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.375118 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.375168 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.375209 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.375251 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.375291 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.375333 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.387104 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.387159 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.387203 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.387244 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.387286 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.387326 (XEN) No periodic timer Apr 23 03:25:02.399131 (XEN) UNIT12 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.399193 (XEN) VCPU12: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.411128 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.411187 (XEN) GICH_LRs (vcpu 12) mask=0 Apr 23 03:25:02.411232 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.411274 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.411314 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.423158 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.423229 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.423275 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.423317 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.423358 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.423399 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.435117 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.435173 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.435216 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.435258 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.435299 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.447128 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.447184 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.447228 (XEN) No periodic timer Apr 23 03:25:02.447270 (XEN) UNIT13 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.447316 (XEN) VCPU13: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.459148 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.459206 (XEN) GICH_LRs (vcpu 13) mask=0 Apr 23 03:25:02.459253 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.471128 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.471185 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.471227 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.471268 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.471308 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.471349 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.483164 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.483219 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.483261 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.483302 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.483344 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.495155 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.495213 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.495256 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.495298 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.495339 (XEN) No periodic timer Apr 23 03:25:02.495400 (XEN) UNIT14 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.507178 (XEN) VCPU14: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.507242 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.519050 (XEN) GICH_LRs (vcpu 14) mask=0 Apr 23 03:25:02.519081 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.519104 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.519127 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.519149 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.519171 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.531035 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.531087 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.531129 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.531170 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.531211 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.531252 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.543153 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.543205 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.543248 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.543270 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.543292 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.543314 (XEN) No periodic timer Apr 23 03:25:02.555072 (XEN) UNIT15 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.555101 (XEN) VCPU15: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.567147 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.567209 (XEN) GICH_LRs (vcpu 15) mask=0 Apr 23 03:25:02.567250 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.567273 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.579170 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.579201 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.579224 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.579247 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.579269 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.579291 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.591157 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.591213 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.591255 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.591296 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.591337 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.591377 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.603155 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.603211 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.603254 (XEN) No periodic timer Apr 23 03:25:02.603296 (XEN) UNIT16 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.603343 (XEN) VCPU16: CPU67 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.615192 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.615250 (XEN) GICH_LRs (vcpu 16) mask=0 Apr 23 03:25:02.627148 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.627205 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.627254 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.627296 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.627355 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.627412 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.639117 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.639173 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.639216 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.639257 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.639298 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.639339 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.651172 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.651228 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.651271 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.651313 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.651354 (XEN) No periodic timer Apr 23 03:25:02.651396 (XEN) UNIT17 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.663175 (XEN) VCPU17: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.663239 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.675163 (XEN) GICH_LRs (vcpu 17) mask=0 Apr 23 03:25:02.675221 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.675264 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.675305 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.675346 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.675387 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.687151 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.687206 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.687249 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.687291 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.687332 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.699077 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.699107 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.699130 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.699203 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.699247 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.711163 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.711221 (XEN) No periodic timer Apr 23 03:25:02.711265 (XEN) UNIT18 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.711312 (XEN) VCPU18: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.723160 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.723218 (XEN) GICH_LRs (vcpu 18) mask=0 Apr 23 03:25:02.723263 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.723305 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.735162 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.735217 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.735260 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.735301 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.735342 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.735382 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.747158 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.747213 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.747256 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.747297 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.747338 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.747379 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.759171 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.759228 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.759270 (XEN) No periodic timer Apr 23 03:25:02.759312 (XEN) UNIT19 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.771168 (XEN) VCPU19: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.771233 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.771279 (XEN) GICH_LRs (vcpu 19) mask=0 Apr 23 03:25:02.783161 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.783217 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.783260 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.783301 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.783342 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.783383 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.795159 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.795215 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.795258 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.795299 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.795340 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.795381 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.807158 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.807214 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.807257 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.807298 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.807339 (XEN) No periodic timer Apr 23 03:25:02.819132 (XEN) UNIT20 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.819194 (XEN) VCPU20: CPU36 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.819245 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.831019 (XEN) GICH_LRs (vcpu 20) mask=0 Apr 23 03:25:02.831050 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.831073 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.831095 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.831118 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.843157 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.843211 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.843254 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.843295 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.843336 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.843377 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.855157 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.855213 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.855255 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.855296 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.855338 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.867149 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.867206 (XEN) No periodic timer Apr 23 03:25:02.867249 (XEN) UNIT21 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.867297 (XEN) VCPU21: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.879160 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.879219 (XEN) GICH_LRs (vcpu 21) mask=0 Apr 23 03:25:02.879264 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.879305 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.891169 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.891224 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.891267 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.891308 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.891350 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.891391 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.903181 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.903238 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.903281 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.903322 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.903363 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.903404 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.915160 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.915215 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.915258 (XEN) No periodic timer Apr 23 03:25:02.915300 (XEN) UNIT22 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.927149 (XEN) VCPU22: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.927213 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.927259 (XEN) GICH_LRs (vcpu 22) mask=0 Apr 23 03:25:02.939098 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.939154 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.939197 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.939238 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.939278 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.951149 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.951205 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.951247 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.951288 (XEN) VCPU_LR[8]=0 Apr 23 03:25:02.951328 (XEN) VCPU_LR[9]=0 Apr 23 03:25:02.951369 (XEN) VCPU_LR[10]=0 Apr 23 03:25:02.963163 (XEN) VCPU_LR[11]=0 Apr 23 03:25:02.963218 (XEN) VCPU_LR[12]=0 Apr 23 03:25:02.963261 (XEN) VCPU_LR[13]=0 Apr 23 03:25:02.963302 (XEN) VCPU_LR[14]=0 Apr 23 03:25:02.963343 (XEN) VCPU_LR[15]=0 Apr 23 03:25:02.963383 (XEN) No periodic timer Apr 23 03:25:02.975149 (XEN) UNIT23 affinities: hard={0-95} soft={0-95} Apr 23 03:25:02.975210 (XEN) VCPU23: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:02.987147 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:02.987207 (XEN) GICH_LRs (vcpu 23) mask=0 Apr 23 03:25:02.987252 (XEN) VCPU_LR[0]=0 Apr 23 03:25:02.987294 (XEN) VCPU_LR[1]=0 Apr 23 03:25:02.987335 (XEN) VCPU_LR[2]=0 Apr 23 03:25:02.999154 (XEN) VCPU_LR[3]=0 Apr 23 03:25:02.999211 (XEN) VCPU_LR[4]=0 Apr 23 03:25:02.999254 (XEN) VCPU_LR[5]=0 Apr 23 03:25:02.999295 (XEN) VCPU_LR[6]=0 Apr 23 03:25:02.999336 (XEN) VCPU_LR[7]=0 Apr 23 03:25:02.999378 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.011159 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.011215 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.011258 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.011299 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.011340 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.011381 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.023175 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.023231 (XEN) No periodic timer Apr 23 03:25:03.023275 (XEN) UNIT24 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.023322 (XEN) VCPU24: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.035021 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.035052 (XEN) GICH_LRs (vcpu 24) mask=0 Apr 23 03:25:03.035093 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.035135 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.047160 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.047215 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.047258 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.047300 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.047359 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.047381 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.059165 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.059220 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.059262 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.059303 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.059345 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.070987 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.070987 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.070987 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.070987 (XEN) No periodic timer Apr 23 03:25:03.070987 (XEN) UNIT25 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.083028 (XEN) VCPU25: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.083028 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.095032 (XEN) GICH_LRs (vcpu 25) mask=0 Apr 23 03:25:03.095032 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.095032 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.095032 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.095032 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.095032 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.107042 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.107042 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.107042 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.107042 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.107042 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.107042 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.119030 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.119030 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.119030 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.119030 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.119030 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.119030 (XEN) No periodic timer Apr 23 03:25:03.130997 (XEN) UNIT26 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.131034 (XEN) VCPU26: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.143164 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.143215 (XEN) GICH_LRs (vcpu 26) mask=0 Apr 23 03:25:03.143259 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.143301 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.143343 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.155124 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.155171 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.155213 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.155250 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.155273 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.155296 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.167156 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.167212 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.167255 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.167296 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.167342 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.167385 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.179082 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.179138 (XEN) No periodic timer Apr 23 03:25:03.179182 (XEN) UNIT27 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.179229 (XEN) VCPU27: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.191051 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.191103 (XEN) GICH_LRs (vcpu 27) mask=0 Apr 23 03:25:03.202966 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.202993 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.203015 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.203038 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.203060 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.203082 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.214932 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.214932 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.214932 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.214932 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.214932 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.214932 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.226926 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.226926 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.226926 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.226926 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.226926 (XEN) No periodic timer Apr 23 03:25:03.226926 (XEN) UNIT28 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.239017 (XEN) VCPU28: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.239017 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.251011 (XEN) GICH_LRs (vcpu 28) mask=0 Apr 23 03:25:03.251011 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.251011 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.251011 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.251011 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.251011 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.262948 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.262948 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.262948 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.262948 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.262948 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.262948 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.275030 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.275030 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.275030 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.275030 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.275030 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.287005 (XEN) No periodic timer Apr 23 03:25:03.287005 (XEN) UNIT29 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.287005 (XEN) VCPU29: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.299008 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.299008 (XEN) GICH_LRs (vcpu 29) mask=0 Apr 23 03:25:03.299008 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.299008 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.299008 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.311018 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.311018 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.311018 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.311018 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.311018 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.311018 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.323010 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.323010 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.323010 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.323010 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.323010 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.335019 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.335019 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.335019 (XEN) No periodic timer Apr 23 03:25:03.335019 (XEN) UNIT30 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.347047 (XEN) VCPU30: CPU6 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.347047 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.347047 (XEN) GICH_LRs (vcpu 30) mask=0 Apr 23 03:25:03.359053 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.359053 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.359053 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.359053 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.359053 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.359053 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.371047 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.371047 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.371047 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.371047 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.371047 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.371047 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.383054 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.383054 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.383054 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.383054 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.383054 (XEN) No periodic timer Apr 23 03:25:03.383054 (XEN) UNIT31 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.395036 (XEN) VCPU31: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.395036 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.406982 (XEN) GICH_LRs (vcpu 31) mask=0 Apr 23 03:25:03.406982 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.406982 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.406982 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.406982 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.406982 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.418980 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.418980 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.418980 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.418980 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.418980 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.418980 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.430977 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.430977 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.430977 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.430977 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.430977 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.443025 (XEN) No periodic timer Apr 23 03:25:03.443025 (XEN) UNIT32 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.443025 (XEN) VCPU32: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.454980 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.454980 (XEN) GICH_LRs (vcpu 32) mask=0 Apr 23 03:25:03.454980 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.454980 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.467011 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.467011 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.467011 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.467011 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.467011 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.467011 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.478979 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.478979 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.478979 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.478979 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.478979 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.478979 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.490981 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.490981 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.490981 (XEN) No periodic timer Apr 23 03:25:03.490981 (XEN) UNIT33 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.503023 (XEN) VCPU33: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.503023 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.503023 (XEN) GICH_LRs (vcpu 33) mask=0 Apr 23 03:25:03.514974 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.514974 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.514974 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.514974 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.514974 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.514974 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.526978 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.526978 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.526978 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.526978 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.526978 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.526978 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.538968 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.538968 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.538968 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.538968 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.538968 (XEN) No periodic timer Apr 23 03:25:03.538968 (XEN) UNIT34 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.551014 (XEN) VCPU34: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.551014 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.563018 (XEN) GICH_LRs (vcpu 34) mask=0 Apr 23 03:25:03.563018 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.563018 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.563018 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.563018 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.575032 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.575032 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.575032 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.575032 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.575032 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.587042 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.587042 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.587042 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.587042 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.587042 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.587042 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.599044 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.599044 (XEN) No periodic timer Apr 23 03:25:03.599044 (XEN) UNIT35 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.599044 (XEN) VCPU35: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.611045 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.611045 (XEN) GICH_LRs (vcpu 35) mask=0 Apr 23 03:25:03.611045 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.611045 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.623020 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.623020 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.623020 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.623020 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.623020 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.623020 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.634988 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.634988 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.634988 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.634988 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.634988 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.634988 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.647001 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.647001 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.647001 (XEN) No periodic timer Apr 23 03:25:03.647001 (XEN) UNIT36 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.659008 (XEN) VCPU36: CPU7 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.659008 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.659008 (XEN) GICH_LRs (vcpu 36) mask=0 Apr 23 03:25:03.671032 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.671032 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.671032 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.671032 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.671032 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.671032 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.683046 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.683046 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.683046 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.683046 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.683046 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.683046 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.695031 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.695031 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.695031 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.695031 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.695031 (XEN) No periodic timer Apr 23 03:25:03.707039 (XEN) UNIT37 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.707039 (XEN) VCPU37: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.719036 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.719036 (XEN) GICH_LRs (vcpu 37) mask=0 Apr 23 03:25:03.719036 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.719036 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.719036 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.730991 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.730991 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.730991 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.730991 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.730991 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.730991 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.743058 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.743058 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.743058 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.743058 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.743058 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.743058 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.755035 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.755035 (XEN) No periodic timer Apr 23 03:25:03.755035 (XEN) UNIT38 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.755035 (XEN) VCPU38: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.766980 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.766980 (XEN) GICH_LRs (vcpu 38) mask=0 Apr 23 03:25:03.766980 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.766980 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.779046 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.779046 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.779046 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.779046 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.779046 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.779046 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.791039 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.791039 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.791039 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.791039 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.791039 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.802993 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.802993 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.802993 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.802993 (XEN) No periodic timer Apr 23 03:25:03.802993 (XEN) UNIT39 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.815042 (XEN) VCPU39: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.815042 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.815042 (XEN) GICH_LRs (vcpu 39) mask=0 Apr 23 03:25:03.827030 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.827030 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.827030 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.827030 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.827030 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.839029 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.839029 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.839029 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.839029 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.839029 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.839029 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.851041 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.851041 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.851041 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.851041 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.851041 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.851041 (XEN) No periodic timer Apr 23 03:25:03.863057 (XEN) UNIT40 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.863057 (XEN) VCPU40: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.875048 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.875048 (XEN) GICH_LRs (vcpu 40) mask=0 Apr 23 03:25:03.875048 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.875048 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.875048 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.887042 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.887042 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.887042 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.887042 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.887042 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.887042 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.899045 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.899045 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.899045 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.899045 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.899045 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.899045 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.911046 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.911046 (XEN) No periodic timer Apr 23 03:25:03.911046 (XEN) UNIT41 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.911046 (XEN) VCPU41: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.923055 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.923055 (XEN) GICH_LRs (vcpu 41) mask=0 Apr 23 03:25:03.923055 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.935046 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.935046 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.935046 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.935046 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.935046 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.935046 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.947043 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.947043 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.947043 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.947043 (XEN) VCPU_LR[10]=0 Apr 23 03:25:03.947043 (XEN) VCPU_LR[11]=0 Apr 23 03:25:03.947043 (XEN) VCPU_LR[12]=0 Apr 23 03:25:03.959032 (XEN) VCPU_LR[13]=0 Apr 23 03:25:03.959032 (XEN) VCPU_LR[14]=0 Apr 23 03:25:03.959032 (XEN) VCPU_LR[15]=0 Apr 23 03:25:03.959032 (XEN) No periodic timer Apr 23 03:25:03.959032 (XEN) UNIT42 affinities: hard={0-95} soft={0-95} Apr 23 03:25:03.971045 (XEN) VCPU42: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:03.971045 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:03.983046 (XEN) GICH_LRs (vcpu 42) mask=0 Apr 23 03:25:03.983046 (XEN) VCPU_LR[0]=0 Apr 23 03:25:03.983046 (XEN) VCPU_LR[1]=0 Apr 23 03:25:03.983046 (XEN) VCPU_LR[2]=0 Apr 23 03:25:03.983046 (XEN) VCPU_LR[3]=0 Apr 23 03:25:03.983046 (XEN) VCPU_LR[4]=0 Apr 23 03:25:03.995049 (XEN) VCPU_LR[5]=0 Apr 23 03:25:03.995049 (XEN) VCPU_LR[6]=0 Apr 23 03:25:03.995049 (XEN) VCPU_LR[7]=0 Apr 23 03:25:03.995049 (XEN) VCPU_LR[8]=0 Apr 23 03:25:03.995049 (XEN) VCPU_LR[9]=0 Apr 23 03:25:03.995049 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.007047 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.007047 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.007047 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.007047 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.007047 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.019028 (XEN) No periodic timer Apr 23 03:25:04.019028 (XEN) UNIT43 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.019028 (XEN) VCPU43: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.031042 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.031042 (XEN) GICH_LRs (vcpu 43) mask=0 Apr 23 03:25:04.031042 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.031042 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.031042 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.043031 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.043031 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.043031 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.043031 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.043031 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.043031 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.055045 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.055045 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.055045 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.055045 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.055045 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.055045 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.067041 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.067041 (XEN) No periodic timer Apr 23 03:25:04.067041 (XEN) UNIT44 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.067041 (XEN) VCPU44: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.079034 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.079034 (XEN) GICH_LRs (vcpu 44) mask=0 Apr 23 03:25:04.091040 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.091040 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.091040 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.091040 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.091040 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.091040 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.103048 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.103048 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.103048 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.103048 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.103048 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.103048 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.115041 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.115041 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.115041 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.115041 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.115041 (XEN) No periodic timer Apr 23 03:25:04.115041 (XEN) UNIT45 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.127040 (XEN) VCPU45: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.127040 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.139045 (XEN) GICH_LRs (vcpu 45) mask=0 Apr 23 03:25:04.139045 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.139045 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.139045 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.139045 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.151043 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.151043 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.151043 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.151043 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.151043 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.151043 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.163049 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.163049 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.163049 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.163049 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.163049 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.163049 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.175042 (XEN) No periodic timer Apr 23 03:25:04.175042 (XEN) UNIT46 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.175042 (XEN) VCPU46: CPU72 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.187046 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.187046 (XEN) GICH_LRs (vcpu 46) mask=0 Apr 23 03:25:04.187046 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.187046 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.187046 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.199046 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.199046 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.199046 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.199046 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.199046 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.199046 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.211099 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.211161 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.211161 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.211161 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.211161 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.223051 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.223051 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.223051 (XEN) No periodic timer Apr 23 03:25:04.223051 (XEN) UNIT47 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.235039 (XEN) VCPU47: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.235039 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.235039 (XEN) GICH_LRs (vcpu 47) mask=0 Apr 23 03:25:04.247048 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.247048 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.247048 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.247048 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.247048 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.247048 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.259048 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.259048 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.259048 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.259048 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.259048 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.259048 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.271041 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.271041 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.271041 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.271041 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.271041 (XEN) No periodic timer Apr 23 03:25:04.271041 (XEN) UNIT48 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.283051 (XEN) VCPU48: CPU9 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.283051 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.295051 (XEN) GICH_LRs (vcpu 48) mask=0 Apr 23 03:25:04.295051 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.295051 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.295051 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.295051 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.307045 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.307045 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.307045 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.307045 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.307045 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.307045 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.319043 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.319043 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.319043 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.319043 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.319043 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.319043 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.331019 (XEN) No periodic timer Apr 23 03:25:04.331019 (XEN) UNIT49 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.331019 (XEN) VCPU49: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.343005 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.343005 (XEN) GICH_LRs (vcpu 49) mask=0 Apr 23 03:25:04.343005 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.343005 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.355010 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.355010 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.355010 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.355010 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.355010 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.355010 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.367011 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.367011 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.367011 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.367011 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.367011 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.367011 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.379042 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.379042 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.379042 (XEN) No periodic timer Apr 23 03:25:04.379042 (XEN) UNIT50 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.391041 (XEN) VCPU50: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.391041 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.391041 (XEN) GICH_LRs (vcpu 50) mask=0 Apr 23 03:25:04.403042 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.403042 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.403042 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.403042 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.403042 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.403042 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.415055 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.415055 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.415055 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.415055 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.415055 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.415055 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.427043 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.427043 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.427043 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.427043 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.427043 (XEN) No periodic timer Apr 23 03:25:04.427043 (XEN) UNIT51 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.439047 (XEN) VCPU51: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.439047 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.451038 (XEN) GICH_LRs (vcpu 51) mask=0 Apr 23 03:25:04.451038 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.451038 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.451038 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.451038 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.463038 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.463038 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.463038 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.463038 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.463038 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.475046 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.475046 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.475046 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.475046 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.475046 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.475046 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.487046 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.487046 (XEN) No periodic timer Apr 23 03:25:04.487046 (XEN) UNIT52 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.487046 (XEN) VCPU52: CPU73 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.499053 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.499053 (XEN) GICH_LRs (vcpu 52) mask=0 Apr 23 03:25:04.499053 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.511046 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.511046 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.511046 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.511046 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.511046 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.511046 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.523047 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.523047 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.523047 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.523047 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.523047 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.523047 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.535051 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.535051 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.535051 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.535051 (XEN) No periodic timer Apr 23 03:25:04.535051 (XEN) UNIT53 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.547047 (XEN) VCPU53: CPU89 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.547047 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.547047 (XEN) GICH_LRs (vcpu 53) mask=0 Apr 23 03:25:04.559047 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.559047 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.559047 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.559047 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.559047 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.559047 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.571048 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.571048 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.571048 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.571048 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.571048 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.571048 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.583048 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.583048 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.583048 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.583048 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.583048 (XEN) No periodic timer Apr 23 03:25:04.595042 (XEN) UNIT54 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.595042 (XEN) VCPU54: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.607044 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.607044 (XEN) GICH_LRs (vcpu 54) mask=0 Apr 23 03:25:04.607044 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.607044 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.607044 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.619043 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.619043 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.619043 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.619043 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.619043 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.619043 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.631029 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.631029 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.631029 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.631029 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.631029 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.631029 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.643019 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.643019 (XEN) No periodic timer Apr 23 03:25:04.643019 (XEN) UNIT55 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.643019 (XEN) VCPU55: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.655037 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.655037 (XEN) GICH_LRs (vcpu 55) mask=0 Apr 23 03:25:04.655037 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.667049 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.667049 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.667049 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.667049 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.667049 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.667049 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.679045 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.679045 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.679045 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.679045 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.679045 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.679045 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.691040 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.691040 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.691040 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.691040 (XEN) No periodic timer Apr 23 03:25:04.691040 (XEN) UNIT56 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.703052 (XEN) VCPU56: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.703052 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.703052 (XEN) GICH_LRs (vcpu 56) mask=0 Apr 23 03:25:04.715037 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.715037 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.715037 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.715037 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.715037 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.727039 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.727039 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.727039 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.727039 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.727039 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.727039 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.739042 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.739042 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.739042 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.739042 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.739042 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.751039 (XEN) No periodic timer Apr 23 03:25:04.751039 (XEN) UNIT57 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.751039 (XEN) VCPU57: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.763041 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.763041 (XEN) GICH_LRs (vcpu 57) mask=0 Apr 23 03:25:04.763041 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.763041 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.763041 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.775046 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.775046 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.775046 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.775046 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.775046 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.775046 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.787045 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.787045 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.787045 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.787045 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.787045 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.787045 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.799051 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.799051 (XEN) No periodic timer Apr 23 03:25:04.799051 (XEN) UNIT58 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.799051 (XEN) VCPU58: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.811039 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.811039 (XEN) GICH_LRs (vcpu 58) mask=0 Apr 23 03:25:04.811039 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.823035 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.823035 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.823035 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.823035 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.823035 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.823035 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.835039 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.835039 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.835039 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.835039 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.835039 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.835039 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.847029 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.847029 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.847029 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.847029 (XEN) No periodic timer Apr 23 03:25:04.847029 (XEN) UNIT59 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.859043 (XEN) VCPU59: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.859043 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.871044 (XEN) GICH_LRs (vcpu 59) mask=0 Apr 23 03:25:04.871044 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.871044 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.871044 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.871044 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.883038 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.883038 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.883038 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.883038 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.883038 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.883038 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.895037 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.895037 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.895037 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.895037 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.895037 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.895037 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.907055 (XEN) No periodic timer Apr 23 03:25:04.907055 (XEN) UNIT60 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.907055 (XEN) VCPU60: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.919049 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.919049 (XEN) GICH_LRs (vcpu 60) mask=0 Apr 23 03:25:04.919049 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.919049 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.919049 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.931041 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.931041 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.931041 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.931041 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.931041 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.931041 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.943039 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.943039 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.943039 (XEN) VCPU_LR[11]=0 Apr 23 03:25:04.943039 (XEN) VCPU_LR[12]=0 Apr 23 03:25:04.943039 (XEN) VCPU_LR[13]=0 Apr 23 03:25:04.955032 (XEN) VCPU_LR[14]=0 Apr 23 03:25:04.955032 (XEN) VCPU_LR[15]=0 Apr 23 03:25:04.955032 (XEN) No periodic timer Apr 23 03:25:04.955032 (XEN) UNIT61 affinities: hard={0-95} soft={0-95} Apr 23 03:25:04.955032 (XEN) VCPU61: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:04.967038 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:04.967038 (XEN) GICH_LRs (vcpu 61) mask=0 Apr 23 03:25:04.979043 (XEN) VCPU_LR[0]=0 Apr 23 03:25:04.979043 (XEN) VCPU_LR[1]=0 Apr 23 03:25:04.979043 (XEN) VCPU_LR[2]=0 Apr 23 03:25:04.979043 (XEN) VCPU_LR[3]=0 Apr 23 03:25:04.979043 (XEN) VCPU_LR[4]=0 Apr 23 03:25:04.979043 (XEN) VCPU_LR[5]=0 Apr 23 03:25:04.991043 (XEN) VCPU_LR[6]=0 Apr 23 03:25:04.991043 (XEN) VCPU_LR[7]=0 Apr 23 03:25:04.991043 (XEN) VCPU_LR[8]=0 Apr 23 03:25:04.991043 (XEN) VCPU_LR[9]=0 Apr 23 03:25:04.991043 (XEN) VCPU_LR[10]=0 Apr 23 03:25:04.991043 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.003039 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.003039 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.003039 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.003039 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.003039 (XEN) No periodic timer Apr 23 03:25:05.003039 (XEN) UNIT62 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.015040 (XEN) VCPU62: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.015040 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.027042 (XEN) GICH_LRs (vcpu 62) mask=0 Apr 23 03:25:05.027042 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.027042 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.027042 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.027042 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.039052 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.039052 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.039052 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.039052 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.039052 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.039052 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.051040 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.051040 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.051040 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.051040 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.051040 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.051040 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.063043 (XEN) No periodic timer Apr 23 03:25:05.063043 (XEN) UNIT63 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.063043 (XEN) VCPU63: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.075043 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.075043 (XEN) GICH_LRs (vcpu 63) mask=0 Apr 23 03:25:05.075043 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.075043 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.087041 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.087041 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.087041 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.087041 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.087041 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.087041 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.099023 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.099174 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.099228 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.099231 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.099231 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.111050 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.111050 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.111050 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.111050 (XEN) No periodic timer Apr 23 03:25:05.111050 (XEN) UNIT64 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.123052 (XEN) VCPU64: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.123052 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.123052 (XEN) GICH_LRs (vcpu 64) mask=0 Apr 23 03:25:05.135041 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.135041 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.135041 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.135041 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.135041 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.135041 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.147018 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.147018 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.147018 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.147018 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.147018 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.147018 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.159042 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.159042 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.159042 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.159042 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.159042 (XEN) No periodic timer Apr 23 03:25:05.171044 (XEN) UNIT65 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.171044 (XEN) VCPU65: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.171044 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.183042 (XEN) GICH_LRs (vcpu 65) mask=0 Apr 23 03:25:05.183042 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.183042 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.183042 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.183042 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.195043 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.195043 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.195043 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.195043 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.195043 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.195043 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.206987 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.206987 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.206987 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.206987 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.206987 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.206987 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.219052 (XEN) No periodic timer Apr 23 03:25:05.219052 (XEN) UNIT66 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.219052 (XEN) VCPU66: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.231034 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.231034 (XEN) GICH_LRs (vcpu 66) mask=0 Apr 23 03:25:05.231034 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.243050 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.243050 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.243050 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.243050 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.243050 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.243050 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.255031 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.255031 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.255031 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.255031 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.255031 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.255031 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.267043 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.267043 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.267043 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.267043 (XEN) No periodic timer Apr 23 03:25:05.267043 (XEN) UNIT67 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.279048 (XEN) VCPU67: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.279048 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.279048 (XEN) GICH_LRs (vcpu 67) mask=0 Apr 23 03:25:05.291046 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.291046 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.291046 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.291046 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.291046 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.291046 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.303038 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.303038 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.303038 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.303038 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.303038 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.315044 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.315044 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.315044 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.315044 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.315044 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.315044 (XEN) No periodic timer Apr 23 03:25:05.327053 (XEN) UNIT68 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.327053 (XEN) VCPU68: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.327053 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.339047 (XEN) GICH_LRs (vcpu 68) mask=0 Apr 23 03:25:05.339047 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.339047 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.339047 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.339047 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.351033 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.351033 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.351033 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.351033 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.351033 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.362932 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.362932 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.362932 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.362932 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.362932 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.362932 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.375001 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.375001 (XEN) No periodic timer Apr 23 03:25:05.375001 (XEN) UNIT69 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.375001 (XEN) VCPU69: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.387020 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.387020 (XEN) GICH_LRs (vcpu 69) mask=0 Apr 23 03:25:05.387020 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.399003 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.399003 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.399003 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.399003 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.399003 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.399003 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.410993 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.410993 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.410993 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.410993 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.410993 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.410993 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.423006 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.423006 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.423006 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.423006 (XEN) No periodic timer Apr 23 03:25:05.423006 (XEN) UNIT70 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.435000 (XEN) VCPU70: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.435000 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.435000 (XEN) GICH_LRs (vcpu 70) mask=0 Apr 23 03:25:05.446988 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.446988 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.446988 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.446988 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.446988 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.458986 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.458986 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.458986 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.458986 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.458986 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.458986 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.470989 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.470989 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.470989 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.470989 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.470989 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.470989 (XEN) No periodic timer Apr 23 03:25:05.482978 (XEN) UNIT71 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.482978 (XEN) VCPU71: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.494998 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.494998 (XEN) GICH_LRs (vcpu 71) mask=0 Apr 23 03:25:05.494998 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.494998 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.494998 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.506989 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.506989 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.506989 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.506989 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.506989 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.506989 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.519211 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.519260 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.519260 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.519260 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.519260 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.531170 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.531250 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.531294 (XEN) No periodic timer Apr 23 03:25:05.531337 (XEN) UNIT72 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.531385 (XEN) VCPU72: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.543126 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.543177 (XEN) GICH_LRs (vcpu 72) mask=0 Apr 23 03:25:05.543222 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.555117 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.555164 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.555206 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.555248 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.555290 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.555331 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.567118 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.567165 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.567206 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.567248 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.567289 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.567331 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.579118 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.579164 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.579207 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.579248 (XEN) No periodic timer Apr 23 03:25:05.579291 (XEN) UNIT73 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.591119 (XEN) VCPU73: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.591174 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.591219 (XEN) GICH_LRs (vcpu 73) mask=0 Apr 23 03:25:05.603107 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.603154 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.603195 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.603237 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.615108 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.615155 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.615197 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.615239 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.615281 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.615322 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.627112 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.627159 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.627201 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.627242 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.627283 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.627325 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.639155 (XEN) No periodic timer Apr 23 03:25:05.639211 (XEN) UNIT74 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.639259 (XEN) VCPU74: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.651172 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.651231 (XEN) GICH_LRs (vcpu 74) mask=0 Apr 23 03:25:05.651277 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.651319 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.663160 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.663216 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.663261 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.663302 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.663344 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.663385 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.675153 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.675210 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.675253 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.675294 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.675336 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.675377 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.687191 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.687249 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.687292 (XEN) No periodic timer Apr 23 03:25:05.687335 (XEN) UNIT75 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.687383 (XEN) VCPU75: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.699168 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.699227 (XEN) GICH_LRs (vcpu 75) mask=0 Apr 23 03:25:05.699273 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.711163 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.711218 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.711261 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.711303 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.711344 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.711385 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.723177 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.723233 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.723276 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.723317 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.723358 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.723399 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.735149 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.735205 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.735248 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.735290 (XEN) No periodic timer Apr 23 03:25:05.747147 (XEN) UNIT76 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.747211 (XEN) VCPU76: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.747262 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.759160 (XEN) GICH_LRs (vcpu 76) mask=0 Apr 23 03:25:05.759219 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.759262 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.759304 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.759346 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.771121 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.771178 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.771220 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.771262 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.771304 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.771345 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.783057 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.783057 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.783057 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.783057 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.783057 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.783057 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.795048 (XEN) No periodic timer Apr 23 03:25:05.795048 (XEN) UNIT77 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.795048 (XEN) VCPU77: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.807045 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.807045 (XEN) GICH_LRs (vcpu 77) mask=0 Apr 23 03:25:05.807045 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.807045 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.819046 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.819046 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.819046 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.819046 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.819046 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.819046 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.831047 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.831047 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.831047 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.831047 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.831047 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.831047 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.843063 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.843063 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.843063 (XEN) No periodic timer Apr 23 03:25:05.843063 (XEN) UNIT78 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.843063 (XEN) VCPU78: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.855083 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.855083 (XEN) GICH_LRs (vcpu 78) mask=0 Apr 23 03:25:05.867039 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.867039 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.867039 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.867039 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.867039 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.867039 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.879046 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.879046 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.879046 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.879046 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.879046 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.879046 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.891054 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.891054 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.891054 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.891054 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.891054 (XEN) No periodic timer Apr 23 03:25:05.903066 (XEN) UNIT79 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.903066 (XEN) VCPU79: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.903066 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.915051 (XEN) GICH_LRs (vcpu 79) mask=0 Apr 23 03:25:05.915051 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.915051 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.915051 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.915051 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.927049 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.927049 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.927049 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.927049 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.927049 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.927049 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.939051 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.939051 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.939051 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.939051 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.939051 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.939051 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.951046 (XEN) No periodic timer Apr 23 03:25:05.951046 (XEN) UNIT80 affinities: hard={0-95} soft={0-95} Apr 23 03:25:05.951046 (XEN) VCPU80: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:05.963068 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:05.963068 (XEN) GICH_LRs (vcpu 80) mask=0 Apr 23 03:25:05.963068 (XEN) VCPU_LR[0]=0 Apr 23 03:25:05.963068 (XEN) VCPU_LR[1]=0 Apr 23 03:25:05.975052 (XEN) VCPU_LR[2]=0 Apr 23 03:25:05.975052 (XEN) VCPU_LR[3]=0 Apr 23 03:25:05.975052 (XEN) VCPU_LR[4]=0 Apr 23 03:25:05.975052 (XEN) VCPU_LR[5]=0 Apr 23 03:25:05.975052 (XEN) VCPU_LR[6]=0 Apr 23 03:25:05.975052 (XEN) VCPU_LR[7]=0 Apr 23 03:25:05.987029 (XEN) VCPU_LR[8]=0 Apr 23 03:25:05.987029 (XEN) VCPU_LR[9]=0 Apr 23 03:25:05.987029 (XEN) VCPU_LR[10]=0 Apr 23 03:25:05.987029 (XEN) VCPU_LR[11]=0 Apr 23 03:25:05.987029 (XEN) VCPU_LR[12]=0 Apr 23 03:25:05.999058 (XEN) VCPU_LR[13]=0 Apr 23 03:25:05.999058 (XEN) VCPU_LR[14]=0 Apr 23 03:25:05.999058 (XEN) VCPU_LR[15]=0 Apr 23 03:25:05.999058 (XEN) No periodic timer Apr 23 03:25:05.999058 (XEN) UNIT81 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.011047 (XEN) VCPU81: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.011047 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.011047 (XEN) GICH_LRs (vcpu 81) mask=0 Apr 23 03:25:06.023123 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.023183 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.023226 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.023267 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.023308 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.035159 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.035215 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.035259 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.035300 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.035340 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.035381 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.047157 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.047213 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.047256 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.047298 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.047338 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.047360 (XEN) No periodic timer Apr 23 03:25:06.059158 (XEN) UNIT82 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.059220 (XEN) VCPU82: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.059271 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.071162 (XEN) GICH_LRs (vcpu 82) mask=0 Apr 23 03:25:06.071220 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.071263 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.071304 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.071344 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.083091 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.083132 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.083157 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.083179 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.083202 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.083224 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.095160 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.095215 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.095258 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.095300 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.095340 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.107155 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.107211 (XEN) No periodic timer Apr 23 03:25:06.107254 (XEN) UNIT83 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.107301 (XEN) VCPU83: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.119150 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.119208 (XEN) GICH_LRs (vcpu 83) mask=0 Apr 23 03:25:06.119253 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.131160 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.131215 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.131258 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.131298 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.131339 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.131380 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.143096 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.143126 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.143149 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.143196 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.143237 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.143278 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.155157 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.155213 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.155256 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.155298 (XEN) No periodic timer Apr 23 03:25:06.155340 (XEN) UNIT84 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.167158 (XEN) VCPU84: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.167222 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.167267 (XEN) GICH_LRs (vcpu 84) mask=0 Apr 23 03:25:06.179162 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.179217 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.179260 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.179301 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.179342 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.191158 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.191214 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.191257 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.191297 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.191338 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.191379 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.203100 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.203131 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.203154 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.203176 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.203224 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.203265 (XEN) No periodic timer Apr 23 03:25:06.215163 (XEN) UNIT85 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.215224 (XEN) VCPU85: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.227155 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.227216 (XEN) GICH_LRs (vcpu 85) mask=0 Apr 23 03:25:06.227261 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.227303 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.227344 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.239144 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.239200 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.239243 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.239284 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.239325 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.251163 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.251221 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.251264 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.251305 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.251347 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.251388 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.263162 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.263218 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.263261 (XEN) No periodic timer Apr 23 03:25:06.263303 (XEN) UNIT86 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.263349 (XEN) VCPU86: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.275168 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.275226 (XEN) GICH_LRs (vcpu 86) mask=0 Apr 23 03:25:06.275291 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.287157 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.287213 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.287256 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.287298 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.287339 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.287380 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.299164 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.299220 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.299263 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.299304 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.299345 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.299386 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.311167 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.311223 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.311266 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.311307 (XEN) No periodic timer Apr 23 03:25:06.311349 (XEN) UNIT87 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.323156 (XEN) VCPU87: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.323220 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.335156 (XEN) GICH_LRs (vcpu 87) mask=0 Apr 23 03:25:06.335215 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.335258 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.335300 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.335340 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.335381 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.347157 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.347213 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.347256 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.347298 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.347339 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.347380 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.359160 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.359215 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.359258 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.359299 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.359340 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.359381 (XEN) No periodic timer Apr 23 03:25:06.371146 (XEN) UNIT88 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.371207 (XEN) VCPU88: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.383146 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.383204 (XEN) GICH_LRs (vcpu 88) mask=0 Apr 23 03:25:06.383249 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.383291 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.395130 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.395186 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.395229 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.395271 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.395324 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.395346 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.407155 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.407212 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.407255 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.407297 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.407339 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.407381 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.419158 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.419214 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.419257 (XEN) No periodic timer Apr 23 03:25:06.419300 (XEN) UNIT89 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.419349 (XEN) VCPU89: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.431165 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.431223 (XEN) GICH_LRs (vcpu 89) mask=0 Apr 23 03:25:06.443142 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.443200 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.443244 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.443286 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.443327 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.443369 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.443410 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.455162 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.455217 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.455259 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.455301 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.455342 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.467169 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.467226 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.467269 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.467311 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.467353 (XEN) No periodic timer Apr 23 03:25:06.467396 (XEN) UNIT90 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.479179 (XEN) VCPU90: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.479245 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.491135 (XEN) GICH_LRs (vcpu 90) mask=0 Apr 23 03:25:06.491193 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.491236 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.491277 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.491319 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.503111 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.503179 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.503222 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.503264 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.503305 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.503347 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.515166 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.515223 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.515266 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.515307 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.515347 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.515388 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.527166 (XEN) No periodic timer Apr 23 03:25:06.527222 (XEN) UNIT91 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.527270 (XEN) VCPU91: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.539164 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.539222 (XEN) GICH_LRs (vcpu 91) mask=0 Apr 23 03:25:06.539267 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.539308 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.551158 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.551214 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.551257 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.551298 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.551338 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.551379 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.563130 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.563198 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.563241 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.563281 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.563321 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.563362 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.575158 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.575214 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.575257 (XEN) No periodic timer Apr 23 03:25:06.575299 (XEN) UNIT92 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.575346 (XEN) VCPU92: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.587171 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.587229 (XEN) GICH_LRs (vcpu 92) mask=0 Apr 23 03:25:06.599158 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.599214 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.599257 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.599298 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.599339 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.599380 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.611151 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.611207 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.611250 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.611292 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.611332 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.611372 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.623134 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.623165 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.623188 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.623211 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.623233 (XEN) No periodic timer Apr 23 03:25:06.635155 (XEN) UNIT93 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.635216 (XEN) VCPU93: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.635268 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.647176 (XEN) GICH_LRs (vcpu 93) mask=0 Apr 23 03:25:06.647234 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.647277 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.647318 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.647359 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.659162 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.659217 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.659260 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.659301 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.659342 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.659383 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.671157 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.671212 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.671255 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.671296 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.671355 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.683149 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.683194 (XEN) No periodic timer Apr 23 03:25:06.683237 (XEN) UNIT94 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.683285 (XEN) VCPU94: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.695163 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.695221 (XEN) GICH_LRs (vcpu 94) mask=0 Apr 23 03:25:06.695266 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.695308 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.707160 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.707216 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.707258 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.707299 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.707344 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.707366 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.719169 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.719225 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.719267 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.719309 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.719351 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.719392 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.731158 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.731214 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.731257 (XEN) No periodic timer Apr 23 03:25:06.731299 (XEN) UNIT95 affinities: hard={0-95} soft={0-95} Apr 23 03:25:06.743160 (XEN) VCPU95: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 23 03:25:06.743195 (XEN) pause_count=0 pause_flags=1 Apr 23 03:25:06.743252 (XEN) GICH_LRs (vcpu 95) mask=0 Apr 23 03:25:06.755155 (XEN) VCPU_LR[0]=0 Apr 23 03:25:06.755211 (XEN) VCPU_LR[1]=0 Apr 23 03:25:06.755254 (XEN) VCPU_LR[2]=0 Apr 23 03:25:06.755294 (XEN) VCPU_LR[3]=0 Apr 23 03:25:06.755335 (XEN) VCPU_LR[4]=0 Apr 23 03:25:06.767168 (XEN) VCPU_LR[5]=0 Apr 23 03:25:06.767224 (XEN) VCPU_LR[6]=0 Apr 23 03:25:06.767267 (XEN) VCPU_LR[7]=0 Apr 23 03:25:06.767308 (XEN) VCPU_LR[8]=0 Apr 23 03:25:06.767350 (XEN) VCPU_LR[9]=0 Apr 23 03:25:06.767390 (XEN) VCPU_LR[10]=0 Apr 23 03:25:06.779164 (XEN) VCPU_LR[11]=0 Apr 23 03:25:06.779220 (XEN) VCPU_LR[12]=0 Apr 23 03:25:06.779263 (XEN) VCPU_LR[13]=0 Apr 23 03:25:06.779304 (XEN) VCPU_LR[14]=0 Apr 23 03:25:06.779344 (XEN) VCPU_LR[15]=0 Apr 23 03:25:06.779384 (XEN) No periodic timer Apr 23 03:25:06.791153 (XEN) Notifying guest 0:0 (virq 1, port 0) Apr 23 03:25:06.791213 (XEN) Notifying guest 0:1 (virq 1, port 0) Apr 23 03:25:06.791259 (XEN) Notifying guest 0:2 (virq 1, port 0) Apr 23 03:25:06.803159 (XEN) Notifying guest 0:3 (virq 1, port 0) Apr 23 03:25:06.803207 (XEN) Notifying guest 0:4 (virq 1, port 0) Apr 23 03:25:06.803249 (XEN) Notifying guest 0:5 (virq 1, port 0) Apr 23 03:25:06.815164 (XEN) Notifying guest 0:6 (virq 1, port 0) Apr 23 03:25:06.815226 (XEN) Notifying guest 0:7 (virq 1, port 0) Apr 23 03:25:06.815272 (XEN) Notifying guest 0:8 (virq 1, port 0) Apr 23 03:25:06.815316 (XEN) Notifying guest 0:9 (virq 1, port 0) Apr 23 03:25:06.827164 (XEN) Notifying guest 0:10 (virq 1, port 0) Apr 23 03:25:06.827222 (XEN) Notifying guest 0:11 (virq 1, port 0) Apr 23 03:25:06.827268 (XEN) Notifying guest 0:12 (virq 1, port 0) Apr 23 03:25:06.839183 (XEN) Notifying guest 0:13 (virq 1, port 0) Apr 23 03:25:06.839242 (XEN) Notifying guest 0:14 (virq 1, port 0) Apr 23 03:25:06.839287 (XEN) Notifying guest 0:15 (virq 1, port 0) Apr 23 03:25:06.851165 (XEN) Notifying guest 0:16 (virq 1, port 0) Apr 23 03:25:06.851223 (XEN) Notifying guest 0:17 (virq 1, port 0) Apr 23 03:25:06.851269 (XEN) Notifying guest 0:18 (virq 1, port 0) Apr 23 03:25:06.863158 (XEN) Notifying guest 0:19 (virq 1, port 0) Apr 23 03:25:06.863216 (XEN) Notifying guest 0:20 (virq 1, port 0) Apr 23 03:25:06.863241 (XEN) Notifying guest 0:21 (virq 1, port 0) Apr 23 03:25:06.875150 (XEN) Notifying guest 0:22 (virq 1, port 0) Apr 23 03:25:06.875209 (XEN) Notifying guest 0:23 (virq 1, port 0) Apr 23 03:25:06.875255 (XEN) Notifying guest 0:24 (virq 1, port 0) Apr 23 03:25:06.887166 (XEN) Notifying guest 0:25 (virq 1, port 0) Apr 23 03:25:06.887224 (XEN) Notifying guest 0:26 (virq 1, port 0) Apr 23 03:25:06.887291 (XEN) Notifying guest 0:27 (virq 1, port 0) Apr 23 03:25:06.899168 (XEN) Notifying guest 0:28 (virq 1, port 0) Apr 23 03:25:06.899227 (XEN) Notifying guest 0:29 (virq 1, port 0) Apr 23 03:25:06.899273 (XEN) Notifying guest 0:30 (virq 1, port 0) Apr 23 03:25:06.911162 (XEN) Notifying guest 0:31 (virq 1, port 0) Apr 23 03:25:06.911221 (XEN) Notifying guest 0:32 (virq 1, port 0) Apr 23 03:25:06.911266 (XEN) Notifying guest 0:33 (virq 1, port 0) Apr 23 03:25:06.923158 (XEN) Notifying guest 0:34 (virq 1, port 0) Apr 23 03:25:06.923228 (XEN) Notifying guest 0:35 (virq 1, port 0) Apr 23 03:25:06.923253 (XEN) Notifying guest 0:36 (virq 1, port 0) Apr 23 03:25:06.935161 (XEN) Notifying guest 0:37 (virq 1, port 0) Apr 23 03:25:06.935220 (XEN) Notifying guest 0:38 (virq 1, port 0) Apr 23 03:25:06.935266 (XEN) Notifying guest 0:39 (virq 1, port 0) Apr 23 03:25:06.947166 (XEN) Notifying guest 0:40 (virq 1, port 0) Apr 23 03:25:06.947225 (XEN) Notifying guest 0:41 (virq 1, port 0) Apr 23 03:25:06.947271 (XEN) Notifying guest 0:42 (virq 1, port 0) Apr 23 03:25:06.959156 (XEN) Notifying guest 0:43 (virq 1, port 0) Apr 23 03:25:06.959215 (XEN) Notifying guest 0:44 (virq 1, port 0) Apr 23 03:25:06.959261 (XEN) Notifying guest 0:45 (virq 1, port 0) Apr 23 03:25:06.971154 (XEN) Notifying guest 0:46 (virq 1, port 0) Apr 23 03:25:06.971213 (XEN) Notifying guest 0:47 (virq 1, port 0) Apr 23 03:25:06.971260 (XEN) Notifying guest 0:48 (virq 1, port 0) Apr 23 03:25:06.983140 (XEN) Notifying guest 0:49 (virq 1, port 0) Apr 23 03:25:06.983140 (XEN) Notifying guest 0:50 (virq 1, port 0) Apr 23 03:25:06.983140 (XEN) Notifying guest 0:51 (virq 1, port 0) Apr 23 03:25:06.995174 (XEN) Notifying guest 0:52 (virq 1, port 0) Apr 23 03:25:06.995239 (XEN) Notifying guest 0:53 (virq 1, port 0) Apr 23 03:25:06.995285 (XEN) Notifying guest 0:54 (virq 1, port 0) Apr 23 03:25:07.007145 (XEN) Notifying guest 0:55 (virq 1, port 0) Apr 23 03:25:07.007205 (XEN) Notifying guest 0:56 (virq 1, port 0) Apr 23 03:25:07.007252 (XEN) Notifying guest 0:57 (virq 1, port 0) Apr 23 03:25:07.019171 (XEN) Notifying guest 0:58 (virq 1, port 0) Apr 23 03:25:07.019230 (XEN) Notifying guest 0:59 (virq 1, port 0) Apr 23 03:25:07.019276 (XEN) Notifying guest 0:60 (virq 1, port 0) Apr 23 03:25:07.031163 (XEN) Notifying guest 0:61 (virq 1, port 0) Apr 23 03:25:07.031222 (XEN) Notifying guest 0:62 (virq 1, port 0) Apr 23 03:25:07.031268 (XEN) Notifying guest 0:63 (virq 1, port 0) Apr 23 03:25:07.043155 (XEN) Notifying guest 0:64 (virq 1, port 0) Apr 23 03:25:07.043214 (XEN) Notifying guest 0:65 (virq 1, port 0) Apr 23 03:25:07.043273 (XEN) Notifying guest 0:66 (virq 1, port 0) Apr 23 03:25:07.055158 (XEN) Notifying guest 0:67 (virq 1, port 0) Apr 23 03:25:07.055217 (XEN) Notifying guest 0:68 (virq 1, port 0) Apr 23 03:25:07.055263 (XEN) Notifying guest 0:69 (virq 1, port 0) Apr 23 03:25:07.067154 (XEN) Notifying guest 0:70 (virq 1, port 0) Apr 23 03:25:07.067214 (XEN) Notifying guest 0:71 (virq 1, port 0) Apr 23 03:25:07.067260 (XEN) Notifying guest 0:72 (virq 1, port 0) Apr 23 03:25:07.079155 (XEN) Notifying guest 0:73 (virq 1, port 0) Apr 23 03:25:07.079215 (XEN) Notifying guest 0:74 (virq 1, port 0) Apr 23 03:25:07.079261 (XEN) Notifying guest 0:75 (virq 1, port 0) Apr 23 03:25:07.091156 (XEN) Notifying guest 0:76 (virq 1, port 0) Apr 23 03:25:07.091216 (XEN) Notifying guest 0:77 (virq 1, port 0) Apr 23 03:25:07.091262 (XEN) Notifying guest 0:78 (virq 1, port 0) Apr 23 03:25:07.103163 (XEN) Notifying guest 0:79 (virq 1, port 0) Apr 23 03:25:07.103224 (XEN) Notifying guest 0:80 (virq 1, port 0) Apr 23 03:25:07.103270 (XEN) Notifying guest 0:81 (virq 1, port 0) Apr 23 03:25:07.115151 (XEN) Notifying guest 0:82 (virq 1, port 0) Apr 23 03:25:07.115213 (XEN) Notifying guest 0:83 (virq 1, port 0) Apr 23 03:25:07.115259 (XEN) Notifying guest 0:84 (virq 1, port 0) Apr 23 03:25:07.115305 (XEN) Notifying guest 0:85 (virq 1, port 0) Apr 23 03:25:07.127154 (XEN) Notifying guest 0:86 (virq 1, port 0) Apr 23 03:25:07.127233 (XEN) Notifying guest 0:87 (virq 1, port 0) Apr 23 03:25:07.139152 (XEN) Notifying guest 0:88 (virq 1, port 0) Apr 23 03:25:07.139212 (XEN) Notifying guest 0:89 (virq 1, port 0) Apr 23 03:25:07.139258 (XEN) Notifying guest 0:90 (virq 1, port 0) Apr 23 03:25:07.151168 (XEN) Notifying guest 0:91 (virq 1, port 0) Apr 23 03:25:07.151228 (XEN) Notifying guest 0:92 (virq 1, port 0) Apr 23 03:25:07.151274 (XEN) Notifying guest 0:93 (virq 1, port 0) Apr 23 03:25:07.163138 (XEN) Notifying guest 0:94 (virq 1, port 0) Apr 23 03:25:07.163198 (XEN) Notifying guest 0:95 (virq 1, port 0) Apr 23 03:25:07.163245 Apr 23 03:25:13.663816 (XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input) Apr 23 03:25:13.683147 Apr 23 03:25:13.683200 rochester0 login: Apr 23 03:25:13.684946