Apr 23 15:08:23.699197 (XEN) GICH_LRs (vcpu 23) mask=0
Apr 23 15:08:23.699365 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:23.699390 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:23.699432 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:23.699455 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:23.708650 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:23.708650 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:23.708650 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:23.708650 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:23.708650 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:23.708650 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:23.720684 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:23.720684 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:23.720684 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:23.720684 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:23.720684 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:23.720684 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:23.732650 (XEN) No periodic timer
Apr 23 15:08:23.732650 (XEN)   UNIT24 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:23.732650 (XEN)     VCPU24: CPU6 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:23.744648 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:23.744648 (XEN) GICH_LRs (vcpu 24) mask=0
Apr 23 15:08:23.744648 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:23.744648 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:23.756709 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:23.756709 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:23.756709 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:23.756709 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:23.756709 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:23.756709 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:23.768647 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:23.768647 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:23.768647 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:23.768647 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:23.768647 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:23.768647 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:23.780644 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:23.780644 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:23.780644 (XEN) No periodic timer
Apr 23 15:08:23.780644 (XEN)   UNIT25 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:23.780644 (XEN)     VCPU25: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:23.792640 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:23.792640 (XEN) GICH_LRs (vcpu 25) mask=0
Apr 23 15:08:23.804647 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:23.804647 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:23.804647 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:23.804647 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:23.804647 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:23.804647 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:23.816645 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:23.816645 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:23.816645 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:23.816645 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:23.816645 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:23.816645 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:23.828781 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:23.828837 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:23.828862 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:23.828884 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:23.828907 (XEN) No periodic timer
Apr 23 15:08:23.840934 (XEN)   UNIT26 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:23.840987 (XEN)     VCPU26: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:23.841016 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:23.852907 (XEN) GICH_LRs (vcpu 26) mask=0
Apr 23 15:08:23.852966 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:23.853009 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:23.853073 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:23.853115 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:23.868946 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:23.869003 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:23.869046 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:23.869109 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:23.869151 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:23.869194 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:23.869235 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:23.869276 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:23.876898 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:23.876954 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:23.876997 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:23.877039 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:23.888926 (XEN) No periodic timer
Apr 23 15:08:23.889005 (XEN)   UNIT27 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:23.889075 (XEN)     VCPU27: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:23.900924 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:23.900984 (XEN) GICH_LRs (vcpu 27) mask=0
Apr 23 15:08:23.901029 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:23.901096 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:23.912905 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:23.912964 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:23.913006 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:23.913049 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:23.913114 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:23.924925 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:23.924982 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:23.925026 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:23.925070 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:23.925134 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:23.925177 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:23.936919 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:23.936978 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:23.937022 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:23.937088 (XEN) No periodic timer
Apr 23 15:08:23.937133 (XEN)   UNIT28 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:23.948923 (XEN)     VCPU28: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:23.948989 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:23.949036 (XEN) GICH_LRs (vcpu 28) mask=0
Apr 23 15:08:23.960912 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:23.960971 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:23.961015 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:23.961058 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:23.961102 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:23.961167 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:23.972918 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:23.972975 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:23.973019 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:23.973062 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:23.973127 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:23.973170 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:23.984927 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:23.984984 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:23.985028 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:23.985094 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:23.985136 (XEN) No periodic timer
Apr 23 15:08:23.996920 (XEN)   UNIT29 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:23.996984 (XEN)     VCPU29: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:23.997037 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.008926 (XEN) GICH_LRs (vcpu 29) mask=0
Apr 23 15:08:24.009008 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.009054 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.009096 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.009138 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.020922 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.021000 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.021044 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.021086 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.021127 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.021170 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.032917 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.032974 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.033018 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.033062 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.033105 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.033169 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.044916 (XEN) No periodic timer
Apr 23 15:08:24.044975 (XEN)   UNIT30 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.045026 (XEN)     VCPU30: CPU72 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.056886 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.056960 (XEN) GICH_LRs (vcpu 30) mask=0
Apr 23 15:08:24.057006 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.068909 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.068968 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.069012 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.069078 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.069120 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.069163 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.080915 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.080973 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.081040 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.081084 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.081127 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.081171 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.092938 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.093019 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.093064 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.093107 (XEN) No periodic timer
Apr 23 15:08:24.093150 (XEN)   UNIT31 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.104832 (XEN)     VCPU31: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.104832 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.104832 (XEN) GICH_LRs (vcpu 31) mask=0
Apr 23 15:08:24.116943 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.117004 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.117047 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.117112 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.117155 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.128912 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.128970 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.129015 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.129080 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.129123 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.129166 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.140914 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.140972 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.141040 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.141083 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.141127 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.141169 (XEN) No periodic timer
Apr 23 15:08:24.152915 (XEN)   UNIT32 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.153000 (XEN)     VCPU32: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.153054 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.164905 (XEN) GICH_LRs (vcpu 32) mask=0
Apr 23 15:08:24.164965 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.165009 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.165075 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.176925 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.176981 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.177024 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.177065 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.177106 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.177147 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.188915 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.188972 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.189016 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.189059 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.189101 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.189144 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.200931 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.200988 (XEN) No periodic timer
Apr 23 15:08:24.201031 (XEN)   UNIT33 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.201079 (XEN)     VCPU33: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.212920 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.212979 (XEN) GICH_LRs (vcpu 33) mask=0
Apr 23 15:08:24.213024 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.224916 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.224972 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.225015 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.225057 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.225098 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.225139 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.236919 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.236975 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.237018 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.237060 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.237101 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.237143 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.248914 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.248970 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.249013 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.249055 (XEN) No periodic timer
Apr 23 15:08:24.249097 (XEN)   UNIT34 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.260923 (XEN)     VCPU34: CPU7 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.260988 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.261034 (XEN) GICH_LRs (vcpu 34) mask=0
Apr 23 15:08:24.272919 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.272975 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.273018 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.273060 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.273102 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.284888 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.284945 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.284988 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.285029 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.285088 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.285133 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.296907 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.296964 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.297007 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.297049 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.297091 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.308915 (XEN) No periodic timer
Apr 23 15:08:24.308973 (XEN)   UNIT35 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.309021 (XEN)     VCPU35: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.320917 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.320976 (XEN) GICH_LRs (vcpu 35) mask=0
Apr 23 15:08:24.321022 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.321064 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.321105 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.332920 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.332975 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.333018 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.333058 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.333100 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.333141 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.344927 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.344982 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.345024 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.345065 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.345106 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.356914 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.356971 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.357014 (XEN) No periodic timer
Apr 23 15:08:24.357056 (XEN)   UNIT36 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.357103 (XEN)     VCPU36: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.368935 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.368993 (XEN) GICH_LRs (vcpu 36) mask=0
Apr 23 15:08:24.369038 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.380920 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.380976 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.381019 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.381060 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.381101 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.381142 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.392914 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.392970 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.393012 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.393053 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.393094 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.393135 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.404913 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.404968 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.405010 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.405052 (XEN) No periodic timer
Apr 23 15:08:24.405093 (XEN)   UNIT37 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.416908 (XEN)     VCPU37: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.416972 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.428927 (XEN) GICH_LRs (vcpu 37) mask=0
Apr 23 15:08:24.428985 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.429028 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.429069 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.429110 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.440919 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.440975 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.441017 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.441058 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.441099 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.441139 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.452918 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.452974 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.453017 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.453059 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.453100 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.453141 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.464916 (XEN) No periodic timer
Apr 23 15:08:24.464959 (XEN)   UNIT38 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.464997 (XEN)     VCPU38: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.476915 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.476974 (XEN) GICH_LRs (vcpu 38) mask=0
Apr 23 15:08:24.477019 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.477060 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.488916 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.488972 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.489033 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.489077 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.489118 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.489159 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.500876 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.500932 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.500974 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.501016 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.501057 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.501098 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.512917 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.512974 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.513017 (XEN) No periodic timer
Apr 23 15:08:24.513059 (XEN)   UNIT39 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.513106 (XEN)     VCPU39: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.524925 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.524983 (XEN) GICH_LRs (vcpu 39) mask=0
Apr 23 15:08:24.525028 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.536918 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.536973 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.537015 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.537057 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.537097 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.537139 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.548921 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.548977 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.549019 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.549060 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.549101 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.560916 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.560972 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.561014 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.561055 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.561096 (XEN) No periodic timer
Apr 23 15:08:24.572912 (XEN)   UNIT40 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.572973 (XEN)     VCPU40: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.573025 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.584918 (XEN) GICH_LRs (vcpu 40) mask=0
Apr 23 15:08:24.584976 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.585018 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.585059 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.585100 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.596927 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.596982 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.597024 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.597065 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.597105 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.597145 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.608922 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.608978 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.609021 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.609062 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.609103 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.609144 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.620922 (XEN) No periodic timer
Apr 23 15:08:24.620978 (XEN)   UNIT41 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.621026 (XEN)     VCPU41: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.632923 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.632981 (XEN) GICH_LRs (vcpu 41) mask=0
Apr 23 15:08:24.633026 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.633067 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.644912 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.644968 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.645010 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.645051 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.645092 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.645133 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.656916 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.656972 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.657015 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.657056 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.657097 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.657139 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.668926 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.668982 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.669024 (XEN) No periodic timer
Apr 23 15:08:24.669066 (XEN)   UNIT42 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.669113 (XEN)     VCPU42: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.680921 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.680979 (XEN) GICH_LRs (vcpu 42) mask=0
Apr 23 15:08:24.692943 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.693000 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.693043 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.693083 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.693124 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.704913 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.704971 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.705014 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.705055 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.705096 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.705137 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.716903 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.716960 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.717003 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.717045 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.717086 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.717127 (XEN) No periodic timer
Apr 23 15:08:24.728920 (XEN)   UNIT43 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.728981 (XEN)     VCPU43: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.729033 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.740924 (XEN) GICH_LRs (vcpu 43) mask=0
Apr 23 15:08:24.740982 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.741024 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.741065 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.741106 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.752917 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.752972 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.753014 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.753056 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.753097 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.753138 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.764922 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.764978 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.765020 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.765061 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.765102 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.765143 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.776918 (XEN) No periodic timer
Apr 23 15:08:24.776974 (XEN)   UNIT44 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.777024 (XEN)     VCPU44: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.788924 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.788983 (XEN) GICH_LRs (vcpu 44) mask=0
Apr 23 15:08:24.789028 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.789071 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.800911 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.800968 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.801011 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.801052 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.801093 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.812906 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.812962 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.813006 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.813047 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.813089 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.813130 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.824890 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.824946 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.824988 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.825030 (XEN) No periodic timer
Apr 23 15:08:24.825072 (XEN)   UNIT45 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.836919 (XEN)     VCPU45: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.836985 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.837032 (XEN) GICH_LRs (vcpu 45) mask=0
Apr 23 15:08:24.848931 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.848987 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.849031 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.849073 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.849115 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.860909 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.860967 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.861011 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.861054 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.861098 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.861139 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.872823 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.872854 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.872878 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.872900 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.872923 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.872946 (XEN) No periodic timer
Apr 23 15:08:24.884910 (XEN)   UNIT46 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.884996 (XEN)     VCPU46: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.885051 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.896924 (XEN) GICH_LRs (vcpu 46) mask=0
Apr 23 15:08:24.896982 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.897025 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.897067 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.897108 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.908912 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.908968 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.909010 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.909051 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.909092 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.909133 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.920926 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.920982 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.921027 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.921068 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.921110 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.932900 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.932956 (XEN) No periodic timer
Apr 23 15:08:24.933000 (XEN)   UNIT47 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.933047 (XEN)     VCPU47: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.944922 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:24.944981 (XEN) GICH_LRs (vcpu 47) mask=0
Apr 23 15:08:24.945026 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:24.956921 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:24.956977 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:24.957020 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:24.957063 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:24.957106 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:24.957148 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:24.968841 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:24.968897 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:24.968939 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:24.968981 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:24.969022 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:24.969064 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:24.980857 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:24.980913 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:24.980956 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:24.980997 (XEN) No periodic timer
Apr 23 15:08:24.981039 (XEN)   UNIT48 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:24.992858 (XEN)     VCPU48: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:24.992922 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.004851 (XEN) GICH_LRs (vcpu 48) mask=0
Apr 23 15:08:25.004911 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.004954 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.004995 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.005036 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.005077 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.016855 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.016911 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.016954 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.016995 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.017036 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.017077 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.028851 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.028908 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.028951 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.028992 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.029032 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.029073 (XEN) No periodic timer
Apr 23 15:08:25.040848 (XEN)   UNIT49 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.040910 (XEN)     VCPU49: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.052852 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.052911 (XEN) GICH_LRs (vcpu 49) mask=0
Apr 23 15:08:25.052957 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.052998 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.064852 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.064910 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.064953 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.064994 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.065035 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.065076 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.076851 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.076908 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.076952 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.076993 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.077035 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.077075 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.088874 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.088931 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.088975 (XEN) No periodic timer
Apr 23 15:08:25.089017 (XEN)   UNIT50 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.089064 (XEN)     VCPU50: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.100872 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.100930 (XEN) GICH_LRs (vcpu 50) mask=0
Apr 23 15:08:25.100975 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.112862 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.112917 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.112959 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.113001 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.113041 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.113082 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.124853 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.124909 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.124952 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.124994 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.125037 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.125080 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.136856 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.136913 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.136957 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.136999 (XEN) No periodic timer
Apr 23 15:08:25.137042 (XEN)   UNIT51 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.148866 (XEN)     VCPU51: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.148931 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.160855 (XEN) GICH_LRs (vcpu 51) mask=0
Apr 23 15:08:25.160914 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.160958 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.161000 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.161040 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.161081 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.172854 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.172910 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.172953 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.172994 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.173036 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.173078 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.184845 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.184900 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.184943 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.184984 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.185026 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.196863 (XEN) No periodic timer
Apr 23 15:08:25.196919 (XEN)   UNIT52 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.196968 (XEN)     VCPU52: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.208859 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.208919 (XEN) GICH_LRs (vcpu 52) mask=0
Apr 23 15:08:25.208965 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.209007 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.220859 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.220916 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.220959 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.221000 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.221042 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.221084 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.232853 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.232910 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.232953 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.232994 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.233035 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.233077 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.244856 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.244911 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.244955 (XEN) No periodic timer
Apr 23 15:08:25.244998 (XEN)   UNIT53 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.245046 (XEN)     VCPU53: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.256864 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.256922 (XEN) GICH_LRs (vcpu 53) mask=0
Apr 23 15:08:25.268850 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.268907 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.268950 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.268991 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.269033 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.269074 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.280849 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.280906 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.280949 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.281009 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.281053 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.281094 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.292852 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.292908 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.292952 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.292993 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.293034 (XEN) No periodic timer
Apr 23 15:08:25.293076 (XEN)   UNIT54 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.304857 (XEN)     VCPU54: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.304921 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.316848 (XEN) GICH_LRs (vcpu 54) mask=0
Apr 23 15:08:25.316907 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.316949 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.316991 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.317031 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.328862 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.328918 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.328961 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.329002 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.329043 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.329084 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.340852 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.340908 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.340950 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.340992 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.341033 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.341074 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.352822 (XEN) No periodic timer
Apr 23 15:08:25.352869 (XEN)   UNIT55 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.352869 (XEN)     VCPU55: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.364812 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.364812 (XEN) GICH_LRs (vcpu 55) mask=0
Apr 23 15:08:25.364812 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.364812 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.376874 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.376936 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.376979 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.377020 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.377061 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.377102 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.388859 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.388915 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.388958 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.389000 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.389041 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.389082 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.400863 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.400919 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.400961 (XEN) No periodic timer
Apr 23 15:08:25.401003 (XEN)   UNIT56 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.412857 (XEN)     VCPU56: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.412922 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.412968 (XEN) GICH_LRs (vcpu 56) mask=0
Apr 23 15:08:25.424859 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.424915 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.424959 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.425000 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.425041 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.425082 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.436842 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.436899 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.436942 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.436983 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.437024 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.448850 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.448906 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.448949 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.448990 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.449031 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.449073 (XEN) No periodic timer
Apr 23 15:08:25.460859 (XEN)   UNIT57 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.460921 (XEN)     VCPU57: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.460972 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.472858 (XEN) GICH_LRs (vcpu 57) mask=0
Apr 23 15:08:25.472916 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.472959 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.473000 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.473041 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.484858 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.484939 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.484985 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.485026 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.485066 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.485107 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.496854 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.496909 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.496952 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.496993 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.497034 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.508851 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.508908 (XEN) No periodic timer
Apr 23 15:08:25.508951 (XEN)   UNIT58 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.508999 (XEN)     VCPU58: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.520862 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.520921 (XEN) GICH_LRs (vcpu 58) mask=0
Apr 23 15:08:25.520966 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.521009 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.532810 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.532844 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.532867 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.532890 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.532912 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.532935 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.544829 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.544829 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.544829 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.544829 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.544829 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.544829 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.556838 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.556900 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.556943 (XEN) No periodic timer
Apr 23 15:08:25.556985 (XEN)   UNIT59 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.568847 (XEN)     VCPU59: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.568912 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.568958 (XEN) GICH_LRs (vcpu 59) mask=0
Apr 23 15:08:25.580862 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.580918 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.580960 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.581002 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.581042 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.592853 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.592908 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.592952 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.592993 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.593035 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.593076 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.604856 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.604913 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.604956 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.604998 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.605039 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.605081 (XEN) No periodic timer
Apr 23 15:08:25.616864 (XEN)   UNIT60 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.616925 (XEN)     VCPU60: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.628847 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.628908 (XEN) GICH_LRs (vcpu 60) mask=0
Apr 23 15:08:25.628954 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.628996 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.629038 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.640854 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.640912 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.640956 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.640997 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.641040 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.641083 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.652859 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.652915 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.652959 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.653001 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.653043 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.653085 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.664858 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.664914 (XEN) No periodic timer
Apr 23 15:08:25.664959 (XEN)   UNIT61 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.665007 (XEN)     VCPU61: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.676867 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.676926 (XEN) GICH_LRs (vcpu 61) mask=0
Apr 23 15:08:25.677001 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.677046 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.688841 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.688898 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.688940 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.688982 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.689024 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.700883 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.700955 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.701000 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.701043 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.701085 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.701127 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.712848 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.712904 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.712947 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.712989 (XEN) No periodic timer
Apr 23 15:08:25.713033 (XEN)   UNIT62 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.724865 (XEN)     VCPU62: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.724930 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.736856 (XEN) GICH_LRs (vcpu 62) mask=0
Apr 23 15:08:25.736915 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.736958 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.737000 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.737042 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.737083 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.748845 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.748900 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.748942 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.748984 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.749025 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.749066 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.760803 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.760833 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.760856 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.760879 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.760902 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.760925 (XEN) No periodic timer
Apr 23 15:08:25.772858 (XEN)   UNIT63 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.772919 (XEN)     VCPU63: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.784851 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.784910 (XEN) GICH_LRs (vcpu 63) mask=0
Apr 23 15:08:25.784956 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.784998 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.785040 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.796863 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.796919 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.796962 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.797004 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.797045 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.797086 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.808856 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.808912 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.808956 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.808998 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.809040 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.809081 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.820850 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.820906 (XEN) No periodic timer
Apr 23 15:08:25.820949 (XEN)   UNIT64 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.820997 (XEN)     VCPU64: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.832867 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.832925 (XEN) GICH_LRs (vcpu 64) mask=0
Apr 23 15:08:25.844889 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.844889 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.844889 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.844889 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.844889 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.844889 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.856929 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.856992 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.857035 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.857076 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.857117 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.857157 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.868930 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.868987 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.869029 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.869071 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.869113 (XEN) No periodic timer
Apr 23 15:08:25.869155 (XEN)   UNIT65 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.880946 (XEN)     VCPU65: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.881011 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.892917 (XEN) GICH_LRs (vcpu 65) mask=0
Apr 23 15:08:25.892976 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.893020 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.893063 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.893106 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.893148 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.904911 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.904970 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.905013 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.905057 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.905100 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.905142 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.916912 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.916970 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.917013 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.917055 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.917098 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.928928 (XEN) No periodic timer
Apr 23 15:08:25.928988 (XEN)   UNIT66 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.929039 (XEN)     VCPU66: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.940919 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.940980 (XEN) GICH_LRs (vcpu 66) mask=0
Apr 23 15:08:25.941028 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:25.941071 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:25.941113 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:25.952908 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:25.952965 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:25.953008 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:25.953050 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:25.953091 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:25.964883 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:25.964941 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:25.964984 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:25.965027 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:25.965069 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:25.965111 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:25.976920 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:25.976978 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:25.977020 (XEN) No periodic timer
Apr 23 15:08:25.977064 (XEN)   UNIT67 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:25.988921 (XEN)     VCPU67: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:25.988989 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:25.989036 (XEN) GICH_LRs (vcpu 67) mask=0
Apr 23 15:08:26.000920 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.000977 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.001021 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.001064 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.001107 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.001150 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.012923 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.012980 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.013025 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.013067 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.013109 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.013152 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.024919 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.024977 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.025021 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.025062 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.025103 (XEN) No periodic timer
Apr 23 15:08:26.025145 (XEN)   UNIT68 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.036920 (XEN)     VCPU68: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.036985 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.048858 (XEN) GICH_LRs (vcpu 68) mask=0
Apr 23 15:08:26.048916 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.048960 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.049002 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.049043 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.060860 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.060918 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.060961 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.061003 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.061043 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.061084 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.072815 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.072864 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.072905 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.072946 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.073007 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.084816 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.084863 (XEN) No periodic timer
Apr 23 15:08:26.084906 (XEN)   UNIT69 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.084953 (XEN)     VCPU69: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.096834 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.096885 (XEN) GICH_LRs (vcpu 69) mask=0
Apr 23 15:08:26.096928 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.096969 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.108758 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.108784 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.108807 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.108829 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.108851 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.108873 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.120855 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.120911 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.120953 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.120995 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.121036 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.121077 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.132856 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.132912 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.132954 (XEN) No periodic timer
Apr 23 15:08:26.132997 (XEN)   UNIT70 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.144848 (XEN)     VCPU70: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.144912 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.144957 (XEN) GICH_LRs (vcpu 70) mask=0
Apr 23 15:08:26.156908 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.156964 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.157006 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.157048 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.157088 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.157129 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.168909 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.168965 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.169008 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.169049 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.169089 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.169130 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.180924 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.180980 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.181022 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.181063 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.181103 (XEN) No periodic timer
Apr 23 15:08:26.181145 (XEN)   UNIT71 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.192904 (XEN)     VCPU71: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.192969 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.204905 (XEN) GICH_LRs (vcpu 71) mask=0
Apr 23 15:08:26.204963 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.205005 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.205047 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.216917 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.216973 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.217016 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.217057 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.217099 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.217140 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.228914 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.228969 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.229012 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.229053 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.229094 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.229135 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.240919 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.240975 (XEN) No periodic timer
Apr 23 15:08:26.241018 (XEN)   UNIT72 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.241065 (XEN)     VCPU72: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.252876 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.252934 (XEN) GICH_LRs (vcpu 72) mask=0
Apr 23 15:08:26.252978 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.253019 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.264917 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.264973 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.265015 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.265056 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.265097 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.265137 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.276921 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.276976 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.277038 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.277082 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.277123 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.277163 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.288921 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.288977 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.289019 (XEN) No periodic timer
Apr 23 15:08:26.289061 (XEN)   UNIT73 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.300917 (XEN)     VCPU73: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.300981 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.301026 (XEN) GICH_LRs (vcpu 73) mask=0
Apr 23 15:08:26.312914 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.312970 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.313012 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.313053 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.313094 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.313135 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.324796 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.324826 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.324849 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.324872 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.324894 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.336906 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.336963 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.337006 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.337048 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.337089 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.337131 (XEN) No periodic timer
Apr 23 15:08:26.348921 (XEN)   UNIT74 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.348983 (XEN)     VCPU74: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.360908 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.360967 (XEN) GICH_LRs (vcpu 74) mask=0
Apr 23 15:08:26.361013 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.361055 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.361096 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.372921 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.372977 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.373020 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.373061 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.373102 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.373142 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.384910 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.384967 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.385010 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.385051 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.385092 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.385133 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.396916 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.396971 (XEN) No periodic timer
Apr 23 15:08:26.397015 (XEN)   UNIT75 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.397062 (XEN)     VCPU75: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.408914 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.408972 (XEN) GICH_LRs (vcpu 75) mask=0
Apr 23 15:08:26.409017 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.420963 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.421019 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.421063 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.421105 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.421145 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.421186 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.432910 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.432967 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.433010 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.433052 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.433093 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.433135 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.444917 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.444975 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.445017 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.445060 (XEN) No periodic timer
Apr 23 15:08:26.445102 (XEN)   UNIT76 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.456909 (XEN)     VCPU76: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.456975 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.468917 (XEN) GICH_LRs (vcpu 76) mask=0
Apr 23 15:08:26.468975 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.469019 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.469060 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.469100 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.469142 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.480938 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.480995 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.481037 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.481077 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.481118 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.481158 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.492926 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.492982 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.493024 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.493065 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.493108 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.493149 (XEN) No periodic timer
Apr 23 15:08:26.504915 (XEN)   UNIT77 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.504976 (XEN)     VCPU77: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.516874 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.516933 (XEN) GICH_LRs (vcpu 77) mask=0
Apr 23 15:08:26.516977 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.517019 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.517059 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.528919 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.528975 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.529018 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.529059 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.529101 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.529143 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.540919 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.540975 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.541017 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.541059 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.541101 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.541142 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.552925 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.552981 (XEN) No periodic timer
Apr 23 15:08:26.553025 (XEN)   UNIT78 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.553072 (XEN)     VCPU78: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.564923 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.564981 (XEN) GICH_LRs (vcpu 78) mask=0
Apr 23 15:08:26.565026 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.576913 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.576969 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.577013 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.577054 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.577095 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.577136 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.588904 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.588960 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.589002 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.589044 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.589085 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.600919 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.600976 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.601019 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.601060 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.601101 (XEN) No periodic timer
Apr 23 15:08:26.601143 (XEN)   UNIT79 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.612932 (XEN)     VCPU79: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.612996 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.624918 (XEN) GICH_LRs (vcpu 79) mask=0
Apr 23 15:08:26.624976 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.625019 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.625060 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.625102 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.625142 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.636922 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.636978 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.637020 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.637060 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.637101 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.637142 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.648921 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.648976 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.649018 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.649059 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.649100 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.660910 (XEN) No periodic timer
Apr 23 15:08:26.660967 (XEN)   UNIT80 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.661015 (XEN)     VCPU80: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.672924 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.672983 (XEN) GICH_LRs (vcpu 80) mask=0
Apr 23 15:08:26.673056 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.673101 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.673142 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.684920 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.684975 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.685018 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.685059 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.685100 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.685141 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.696927 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.696983 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.697025 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.697066 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.697108 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.697149 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.708910 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.708966 (XEN) No periodic timer
Apr 23 15:08:26.709009 (XEN)   UNIT81 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.720918 (XEN)     VCPU81: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.720982 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.721027 (XEN) GICH_LRs (vcpu 81) mask=0
Apr 23 15:08:26.732913 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.732969 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.733012 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.733053 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.733094 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.733135 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.744909 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.744965 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.745009 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.745050 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.745091 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.745132 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.756910 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.756966 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.757009 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.757050 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.757091 (XEN) No periodic timer
Apr 23 15:08:26.757132 (XEN)   UNIT82 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.768936 (XEN)     VCPU82: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.769001 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.780918 (XEN) GICH_LRs (vcpu 82) mask=0
Apr 23 15:08:26.780977 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.781020 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.781060 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.781102 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.792914 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.792971 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.793013 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.793054 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.793095 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.793136 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.804913 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.804970 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.805012 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.805053 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.805094 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.805134 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.816916 (XEN) No periodic timer
Apr 23 15:08:26.816973 (XEN)   UNIT83 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.817021 (XEN)     VCPU83: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.828915 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.828973 (XEN) GICH_LRs (vcpu 83) mask=0
Apr 23 15:08:26.829018 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.829060 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.829101 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.840884 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.840939 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.840981 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.841021 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.841061 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.852926 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.852982 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.853023 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.853064 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.853105 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.853146 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.864918 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.864974 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.865017 (XEN) No periodic timer
Apr 23 15:08:26.865059 (XEN)   UNIT84 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.876946 (XEN)     VCPU84: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.877011 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.877056 (XEN) GICH_LRs (vcpu 84) mask=0
Apr 23 15:08:26.888924 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.888980 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.889022 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.889063 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.889102 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.889142 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.900919 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.900975 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.901017 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.901057 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.901098 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.901139 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.912908 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.912964 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.913006 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.913048 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.913089 (XEN) No periodic timer
Apr 23 15:08:26.913130 (XEN)   UNIT85 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.924931 (XEN)     VCPU85: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.924996 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.936921 (XEN) GICH_LRs (vcpu 85) mask=0
Apr 23 15:08:26.936979 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.937022 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.937063 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.937104 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.948920 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.948976 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.949019 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.949060 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:26.949101 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:26.949141 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:26.960907 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:26.960963 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:26.961005 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:26.961046 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:26.961087 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:26.972918 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:26.972974 (XEN) No periodic timer
Apr 23 15:08:26.973018 (XEN)   UNIT86 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:26.973065 (XEN)     VCPU86: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:26.984917 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:26.984975 (XEN) GICH_LRs (vcpu 86) mask=0
Apr 23 15:08:26.985020 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:26.985061 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:26.996925 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:26.996981 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:26.997023 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:26.997064 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:26.997104 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:26.997144 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:27.008927 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:27.008983 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:27.009025 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:27.009066 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:27.009106 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:27.020918 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:27.020974 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:27.021017 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:27.021059 (XEN) No periodic timer
Apr 23 15:08:27.021101 (XEN)   UNIT87 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:27.032916 (XEN)     VCPU87: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:27.032980 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:27.033026 (XEN) GICH_LRs (vcpu 87) mask=0
Apr 23 15:08:27.044915 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:27.044971 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:27.045014 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:27.045055 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:27.045096 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:27.045137 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:27.056927 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:27.056982 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:27.057024 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:27.057065 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:27.057106 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:27.057147 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:27.068924 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:27.068980 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:27.069023 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:27.069083 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:27.069127 (XEN) No periodic timer
Apr 23 15:08:27.080908 (XEN)   UNIT88 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:27.080970 (XEN)     VCPU88: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:27.081022 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:27.092905 (XEN) GICH_LRs (vcpu 88) mask=0
Apr 23 15:08:27.092963 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:27.093006 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:27.093046 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:27.104916 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:27.104972 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:27.105015 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:27.105055 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:27.105096 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:27.105137 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:27.116927 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:27.116983 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:27.117026 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:27.117068 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:27.117109 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:27.117150 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:27.128917 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:27.128973 (XEN) No periodic timer
Apr 23 15:08:27.129016 (XEN)   UNIT89 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:27.129064 (XEN)     VCPU89: CPU67 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:27.140927 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:27.140985 (XEN) GICH_LRs (vcpu 89) mask=0
Apr 23 15:08:27.141030 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:27.152910 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:27.152967 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:27.153009 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:27.153051 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:27.153092 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:27.153133 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:27.164906 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:27.164964 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:27.165008 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:27.165050 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:27.165092 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:27.165133 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:27.176924 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:27.176981 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:27.177023 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:27.177065 (XEN) No periodic timer
Apr 23 15:08:27.177107 (XEN)   UNIT90 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:27.188918 (XEN)     VCPU90: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:27.188982 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:27.189028 (XEN) GICH_LRs (vcpu 90) mask=0
Apr 23 15:08:27.200927 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:27.200983 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:27.201027 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:27.201068 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:27.201110 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:27.201153 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:27.212905 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:27.212961 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:27.213003 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:27.213045 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:27.213086 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:27.224910 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:27.224966 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:27.225009 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:27.225050 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:27.225092 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:27.236885 (XEN) No periodic timer
Apr 23 15:08:27.236920 (XEN)   UNIT91 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:27.236947 (XEN)     VCPU91: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:27.248921 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:27.248981 (XEN) GICH_LRs (vcpu 91) mask=0
Apr 23 15:08:27.249027 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:27.249068 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:27.249110 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:27.260918 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:27.260976 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:27.261020 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:27.261061 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:27.261105 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:27.261146 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:27.272918 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:27.272999 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:27.273045 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:27.273086 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:27.273128 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:27.273169 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:27.284910 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:27.284966 (XEN) No periodic timer
Apr 23 15:08:27.285010 (XEN)   UNIT92 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:27.285058 (XEN)     VCPU92: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:27.296919 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:27.296978 (XEN) GICH_LRs (vcpu 92) mask=0
Apr 23 15:08:27.297024 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:27.308910 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:27.308966 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:27.309009 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:27.309050 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:27.309091 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:27.309132 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:27.320911 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:27.320967 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:27.321010 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:27.321052 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:27.321093 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:27.321134 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:27.332905 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:27.332961 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:27.333004 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:27.333046 (XEN) No periodic timer
Apr 23 15:08:27.333088 (XEN)   UNIT93 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:27.344899 (XEN)     VCPU93: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:27.344964 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:27.356918 (XEN) GICH_LRs (vcpu 93) mask=0
Apr 23 15:08:27.356977 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:27.357020 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:27.357062 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:27.357103 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:27.357143 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:27.368923 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:27.368979 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:27.369021 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:27.369062 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:27.369103 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:27.369144 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:27.380920 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:27.380975 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:27.381018 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:27.381059 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:27.381100 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:27.392910 (XEN) No periodic timer
Apr 23 15:08:27.392967 (XEN)   UNIT94 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:27.393016 (XEN)     VCPU94: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:27.404912 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:27.404971 (XEN) GICH_LRs (vcpu 94) mask=0
Apr 23 15:08:27.405016 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:27.405058 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:27.405100 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:27.416913 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:27.416968 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:27.417013 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:27.417054 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:27.417097 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:27.417139 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:27.428928 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:27.428984 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:27.429027 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:27.429068 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:27.429110 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:27.429151 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:27.440884 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:27.440940 (XEN) No periodic timer
Apr 23 15:08:27.440984 (XEN)   UNIT95 affinities: hard={0-95} soft={0-95}
Apr 23 15:08:27.441031 (XEN)     VCPU95: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 23 15:08:27.452863 (XEN)     pause_count=0 pause_flags=1
Apr 23 15:08:27.452921 (XEN) GICH_LRs (vcpu 95) mask=0
Apr 23 15:08:27.452966 (XEN)    VCPU_LR[0]=0
Apr 23 15:08:27.464852 (XEN)    VCPU_LR[1]=0
Apr 23 15:08:27.464908 (XEN)    VCPU_LR[2]=0
Apr 23 15:08:27.464950 (XEN)    VCPU_LR[3]=0
Apr 23 15:08:27.464991 (XEN)    VCPU_LR[4]=0
Apr 23 15:08:27.465055 (XEN)    VCPU_LR[5]=0
Apr 23 15:08:27.465100 (XEN)    VCPU_LR[6]=0
Apr 23 15:08:27.476846 (XEN)    VCPU_LR[7]=0
Apr 23 15:08:27.476901 (XEN)    VCPU_LR[8]=0
Apr 23 15:08:27.476944 (XEN)    VCPU_LR[9]=0
Apr 23 15:08:27.476985 (XEN)    VCPU_LR[10]=0
Apr 23 15:08:27.477026 (XEN)    VCPU_LR[11]=0
Apr 23 15:08:27.488853 (XEN)    VCPU_LR[12]=0
Apr 23 15:08:27.488910 (XEN)    VCPU_LR[13]=0
Apr 23 15:08:27.488953 (XEN)    VCPU_LR[14]=0
Apr 23 15:08:27.488995 (XEN)    VCPU_LR[15]=0
Apr 23 15:08:27.489036 (XEN) No periodic timer
Apr 23 15:08:27.489078 (XEN) Notifying guest 0:0 (virq 1, port 0)
Apr 23 15:08:27.500862 (XEN) Notifying guest 0:1 (virq 1, port 0)
Apr 23 15:08:27.500921 (XEN) Notifying guest 0:2 (virq 1, port 0)
Apr 23 15:08:27.500967 (XEN) Notifying guest 0:3 (virq 1, port 0)
Apr 23 15:08:27.512854 (XEN) Notifying guest 0:4 (virq 1, port 0)
Apr 23 15:08:27.512913 (XEN) Notifying guest 0:5 (virq 1, port 0)
Apr 23 15:08:27.512958 (XEN) Notifying guest 0:6 (virq 1, port 0)
Apr 23 15:08:27.524892 (XEN) Notifying guest 0:7 (virq 1, port 0)
Apr 23 15:08:27.524952 (XEN) Notifying guest 0:8 (virq 1, port 0)
Apr 23 15:08:27.525000 (XEN) Notifying guest 0:9 (virq 1, port 0)
Apr 23 15:08:27.536889 (XEN) Notifying guest 0:10 (virq 1, port 0)
Apr 23 15:08:27.536951 (XEN) Notifying guest 0:11 (virq 1, port 0)
Apr 23 15:08:27.536998 (XEN) Notifying guest 0:12 (virq 1, port 0)
Apr 23 15:08:27.548900 (XEN) Notifying guest 0:13 (virq 1, port 0)
Apr 23 15:08:27.548962 (XEN) Notifying guest 0:14 (virq 1, port 0)
Apr 23 15:08:27.549009 (XEN) Notifying guest 0:15 (virq 1, port 0)
Apr 23 15:08:27.560921 (XEN) Notifying guest 0:16 (virq 1, port 0)
Apr 23 15:08:27.560981 (XEN) Notifying guest 0:17 (virq 1, port 0)
Apr 23 15:08:27.561029 (XEN) Notifying guest 0:18 (virq 1, port 0)
Apr 23 15:08:27.572917 (XEN) Notifying guest 0:19 (virq 1, port 0)
Apr 23 15:08:27.572979 (XEN) Notifying guest 0:20 (virq 1, port 0)
Apr 23 15:08:27.573027 (XEN) Notifying guest 0:21 (virq 1, port 0)
Apr 23 15:08:27.584910 (XEN) Notifying guest 0:22 (virq 1, port 0)
Apr 23 15:08:27.584972 (XEN) Notifying guest 0:23 (virq 1, port 0)
Apr 23 15:08:27.585020 (XEN) Notifying guest 0:24 (virq 1, port 0)
Apr 23 15:08:27.596894 (XEN) Notifying guest 0:25 (virq 1, port 0)
Apr 23 15:08:27.596956 (XEN) Notifying guest 0:26 (virq 1, port 0)
Apr 23 15:08:27.597004 (XEN) Notifying guest 0:27 (virq 1, port 0)
Apr 23 15:08:27.608836 (XEN) Notifying guest 0:28 (virq 1, port 0)
Apr 23 15:08:27.608836 (XEN) Notifying guest 0:29 (virq 1, port 0)
Apr 23 15:08:27.608836 (XEN) Notifying guest 0:30 (virq 1, port 0)
Apr 23 15:08:27.620936 (XEN) Notifying guest 0:31 (virq 1, port 0)
Apr 23 15:08:27.621001 (XEN) Notifying guest 0:32 (virq 1, port 0)
Apr 23 15:08:27.621049 (XEN) Notifying guest 0:33 (virq 1, port 0)
Apr 23 15:08:27.632918 (XEN) Notifying guest 0:34 (virq 1, port 0)
Apr 23 15:08:27.632980 (XEN) Notifying guest 0:35 (virq 1, port 0)
Apr 23 15:08:27.633028 (XEN) Notifying guest 0:36 (virq 1, port 0)
Apr 23 15:08:27.644918 (XEN) Notifying guest 0:37 (virq 1, port 0)
Apr 23 15:08:27.644978 (XEN) Notifying guest 0:38 (virq 1, port 0)
Apr 23 15:08:27.645027 (XEN) Notifying guest 0:39 (virq 1, port 0)
Apr 23 15:08:27.656916 (XEN) Notifying guest 0:40 (virq 1, port 0)
Apr 23 15:08:27.656978 (XEN) Notifying guest 0:41 (virq 1, port 0)
Apr 23 15:08:27.657027 (XEN) Notifying guest 0:42 (virq 1, port 0)
Apr 23 15:08:27.668907 (XEN) Notifying guest 0:43 (virq 1, port 0)
Apr 23 15:08:27.668971 (XEN) Notifying guest 0:44 (virq 1, port 0)
Apr 23 15:08:27.669017 (XEN) Notifying guest 0:45 (virq 1, port 0)
Apr 23 15:08:27.680926 (XEN) Notifying guest 0:46 (virq 1, port 0)
Apr 23 15:08:27.680989 (XEN) Notifying guest 0:47 (virq 1, port 0)
Apr 23 15:08:27.681038 (XEN) Notifying guest 0:48 (virq 1, port 0)
Apr 23 15:08:27.681083 (XEN) Notifying guest 0:49 (virq 1, port 0)
Apr 23 15:08:27.692924 (XEN) Notifying guest 0:50 (virq 1, port 0)
Apr 23 15:08:27.692984 (XEN) Notifying guest 0:51 (virq 1, port 0)
Apr 23 15:08:27.693032 (XEN) Notifying guest 0:52 (virq 1, port 0)
Apr 23 15:08:27.704952 (XEN) Notifying guest 0:53 (virq 1, port 0)
Apr 23 15:08:27.705012 (XEN) Notifying guest 0:54 (virq 1, port 0)
Apr 23 15:08:27.705059 (XEN) Notifying guest 0:55 (virq 1, port 0)
Apr 23 15:08:27.716921 (XEN) Notifying guest 0:56 (virq 1, port 0)
Apr 23 15:08:27.716980 (XEN) Notifying guest 0:57 (virq 1, port 0)
Apr 23 15:08:27.717028 (XEN) Notifying guest 0:58 (virq 1, port 0)
Apr 23 15:08:27.728910 (XEN) Notifying guest 0:59 (virq 1, port 0)
Apr 23 15:08:27.728972 (XEN) Notifying guest 0:60 (virq 1, port 0)
Apr 23 15:08:27.740911 (XEN) Notifying guest 0:61 (virq 1, port 0)
Apr 23 15:08:27.740973 (XEN) Notifying guest 0:62 (virq 1, port 0)
Apr 23 15:08:27.741019 (XEN) Notifying guest 0:63 (virq 1, port 0)
Apr 23 15:08:27.752919 (XEN) Notifying guest 0:64 (virq 1, port 0)
Apr 23 15:08:27.752981 (XEN) Notifying guest 0:65 (virq 1, port 0)
Apr 23 15:08:27.753029 (XEN) Notifying guest 0:66 (virq 1, port 0)
Apr 23 15:08:27.753075 (XEN) Notifying guest 0:67 (virq 1, port 0)
Apr 23 15:08:27.764934 (XEN) Notifying guest 0:68 (virq 1, port 0)
Apr 23 15:08:27.764993 (XEN) Notifying guest 0:69 (virq 1, port 0)
Apr 23 15:08:27.765039 (XEN) Notifying guest 0:70 (virq 1, port 0)
Apr 23 15:08:27.776924 (XEN) Notifying guest 0:71 (virq 1, port 0)
Apr 23 15:08:27.776984 (XEN) Notifying guest 0:72 (virq 1, port 0)
Apr 23 15:08:27.777030 (XEN) Notifying guest 0:73 (virq 1, port 0)
Apr 23 15:08:27.788915 (XEN) Notifying guest 0:74 (virq 1, port 0)
Apr 23 15:08:27.788975 (XEN) Notifying guest 0:75 (virq 1, port 0)
Apr 23 15:08:27.789021 (XEN) Notifying guest 0:76 (virq 1, port 0)
Apr 23 15:08:27.800936 (XEN) Notifying guest 0:77 (virq 1, port 0)
Apr 23 15:08:27.800997 (XEN) Notifying guest 0:78 (virq 1, port 0)
Apr 23 15:08:27.801043 (XEN) Notifying guest 0:79 (virq 1, port 0)
Apr 23 15:08:27.812921 (XEN) Notifying guest 0:80 (virq 1, port 0)
Apr 23 15:08:27.812981 (XEN) Notifying guest 0:81 (virq 1, port 0)
Apr 23 15:08:27.813029 (XEN) Notifying guest 0:82 (virq 1, port 0)
Apr 23 15:08:27.824920 (XEN) Notifying guest 0:83 (virq 1, port 0)
Apr 23 15:08:27.824980 (XEN) Notifying guest 0:84 (virq 1, port 0)
Apr 23 15:08:27.825027 (XEN) Notifying guest 0:85 (virq 1, port 0)
Apr 23 15:08:27.836896 (XEN) Notifying guest 0:86 (virq 1, port 0)
Apr 23 15:08:27.836956 (XEN) Notifying guest 0:87 (virq 1, port 0)
Apr 23 15:08:27.837002 (XEN) Notifying guest 0:88 (virq 1, port 0)
Apr 23 15:08:27.848913 (XEN) Notifying guest 0:89 (virq 1, port 0)
Apr 23 15:08:27.848974 (XEN) Notifying guest 0:90 (virq 1, port 0)
Apr 23 15:08:27.849022 (XEN) Notifying guest 0:91 (virq 1, port 0)
Apr 23 15:08:27.860922 (XEN) Notifying guest 0:92 (virq 1, port 0)
Apr 23 15:08:27.860982 (XEN) Notifying guest 0:93 (virq 1, port 0)
Apr 23 15:08:27.861029 (XEN) Notifying guest 0:94 (virq 1, port 0)
Apr 23 15:08:27.872907 (XEN) Notifying guest 0:95 (virq 1, port 0)
Apr 23 15:08:27.872966 Apr 23 15:08:34.242274 <client 0x195a580 connected - now 1 clients>
(XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input)
Apr 23 15:08:34.256937 Apr 23 15:08:34.258271 <client 0x195a580 disconnected - now 0 clients>