Apr 24 12:01:16.859107 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:16.859404 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:16.868722 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:16.868722 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:16.868722 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:16.868722 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:16.868722 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:16.880670 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:16.880670 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:16.880670 (XEN) No periodic timer
Apr 24 12:01:16.880670 (XEN)   UNIT12 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:16.880670 (XEN)     VCPU12: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:16.892711 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:16.892711 (XEN) GICH_LRs (vcpu 12) mask=0
Apr 24 12:01:16.892711 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:16.904670 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:16.904670 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:16.904670 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:16.904670 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:16.904670 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:16.904670 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:16.916666 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:16.916666 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:16.916666 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:16.916666 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:16.916666 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:16.928675 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:16.928675 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:16.928675 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:16.928675 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:16.928675 (XEN) No periodic timer
Apr 24 12:01:16.928675 (XEN)   UNIT13 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:16.940669 (XEN)     VCPU13: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:16.940669 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:16.952667 (XEN) GICH_LRs (vcpu 13) mask=0
Apr 24 12:01:16.952667 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:16.952667 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:16.952667 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:16.952667 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:16.964667 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:16.964667 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:16.964667 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:16.964667 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:16.964667 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:16.964667 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:16.976667 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:16.976667 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:16.976667 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:16.976667 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:16.976667 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:16.976667 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:16.988667 (XEN) No periodic timer
Apr 24 12:01:16.988667 (XEN)   UNIT14 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:16.988667 (XEN)     VCPU14: CPU7 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.000668 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.000668 (XEN) GICH_LRs (vcpu 14) mask=0
Apr 24 12:01:17.000668 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.000668 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.012670 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.012670 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.012670 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.012670 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.012670 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.012670 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.012670 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.024668 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.024668 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.024668 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.024668 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.024668 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.036671 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.036671 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.036671 (XEN) No periodic timer
Apr 24 12:01:17.036671 (XEN)   UNIT15 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.036671 (XEN)     VCPU15: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.048657 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.048657 (XEN) GICH_LRs (vcpu 15) mask=0
Apr 24 12:01:17.060669 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.060669 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.060669 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.060669 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.060669 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.060669 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.072668 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.072668 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.072668 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.072668 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.072668 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.072668 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.084669 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.084669 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.084669 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.084669 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.084669 (XEN) No periodic timer
Apr 24 12:01:17.084669 (XEN)   UNIT16 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.096707 (XEN)     VCPU16: CPU67 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.096707 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.108945 (XEN) GICH_LRs (vcpu 16) mask=0
Apr 24 12:01:17.109009 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.109051 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.109092 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.109132 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.120906 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.120962 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.121004 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.121045 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.121084 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.121147 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.132916 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.132973 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.133015 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.133056 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.133120 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.133162 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.144917 (XEN) No periodic timer
Apr 24 12:01:17.144973 (XEN)   UNIT17 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.145021 (XEN)     VCPU17: CPU34 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.156929 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.156988 (XEN) GICH_LRs (vcpu 17) mask=0
Apr 24 12:01:17.157032 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.157073 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.168923 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.168979 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.169046 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.169089 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.169130 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.169171 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.180916 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.180994 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.181038 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.181079 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.181119 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.192921 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.193000 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.193045 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.193086 (XEN) No periodic timer
Apr 24 12:01:17.193129 (XEN)   UNIT18 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.204928 (XEN)     VCPU18: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.205014 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.205062 (XEN) GICH_LRs (vcpu 18) mask=0
Apr 24 12:01:17.216904 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.216961 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.217004 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.217067 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.217108 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.217148 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.228946 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.229002 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.229067 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.229108 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.229148 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.229189 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.240931 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.241010 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.241055 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.241095 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.241136 (XEN) No periodic timer
Apr 24 12:01:17.252932 (XEN)   UNIT19 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.253016 (XEN)     VCPU19: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.253069 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.264954 (XEN) GICH_LRs (vcpu 19) mask=0
Apr 24 12:01:17.265012 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.265055 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.265118 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.265160 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.276925 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.276981 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.277022 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.277086 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.277127 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.277167 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.288936 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.288992 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.289058 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.289100 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.289140 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.289180 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.300917 (XEN) No periodic timer
Apr 24 12:01:17.300995 (XEN)   UNIT20 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.301045 (XEN)     VCPU20: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.312940 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.312998 (XEN) GICH_LRs (vcpu 20) mask=0
Apr 24 12:01:17.313042 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.324923 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.324980 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.325024 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.325066 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.325107 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.325170 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.336923 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.336979 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.337021 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.337061 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.337124 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.337166 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.348932 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.348988 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.349032 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.349073 (XEN) No periodic timer
Apr 24 12:01:17.349114 (XEN)   UNIT21 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.360922 (XEN)     VCPU21: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.360986 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.361030 (XEN) GICH_LRs (vcpu 21) mask=0
Apr 24 12:01:17.372928 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.372985 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.373027 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.373066 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.373106 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.384922 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.384981 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.385024 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.385064 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.385104 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.385144 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.396923 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.396981 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.397024 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.397064 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.397104 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.397144 (XEN) No periodic timer
Apr 24 12:01:17.408936 (XEN)   UNIT22 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.408997 (XEN)     VCPU22: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.409048 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.420924 (XEN) GICH_LRs (vcpu 22) mask=0
Apr 24 12:01:17.420983 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.421025 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.421066 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.421107 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.432921 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.432977 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.433019 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.433060 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.433101 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.444923 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.444979 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.445021 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.445062 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.445102 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.445142 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.456928 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.456984 (XEN) No periodic timer
Apr 24 12:01:17.457045 (XEN)   UNIT23 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.457095 (XEN)     VCPU23: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.468937 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.468996 (XEN) GICH_LRs (vcpu 23) mask=0
Apr 24 12:01:17.469040 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.480927 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.480984 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.481027 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.481067 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.481107 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.481147 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.492919 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.492976 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.493018 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.493059 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.493099 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.493139 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.504927 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.504984 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.505026 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.505067 (XEN) No periodic timer
Apr 24 12:01:17.505108 (XEN)   UNIT24 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.516925 (XEN)     VCPU24: CPU6 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.516990 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.517036 (XEN) GICH_LRs (vcpu 24) mask=0
Apr 24 12:01:17.528935 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.528991 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.529034 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.529074 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.529114 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.540923 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.540979 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.541022 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.541063 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.541102 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.541142 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.552911 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.552968 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.553011 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.553052 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.553092 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.564925 (XEN) No periodic timer
Apr 24 12:01:17.564982 (XEN)   UNIT25 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.565030 (XEN)     VCPU25: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.576920 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.576979 (XEN) GICH_LRs (vcpu 25) mask=0
Apr 24 12:01:17.577024 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.577065 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.577105 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.588937 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.588992 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.589034 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.589075 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.589115 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.589154 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.600924 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.600980 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.601022 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.601062 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.601102 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.612926 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.612984 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.613027 (XEN) No periodic timer
Apr 24 12:01:17.613068 (XEN)   UNIT26 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.613114 (XEN)     VCPU26: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.624942 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.625000 (XEN) GICH_LRs (vcpu 26) mask=0
Apr 24 12:01:17.625045 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.636931 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.636986 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.637028 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.637069 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.637108 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.637147 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.648931 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.648987 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.649029 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.649069 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.649108 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.649147 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.660935 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.660992 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.661035 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.661074 (XEN) No periodic timer
Apr 24 12:01:17.661115 (XEN)   UNIT27 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.672927 (XEN)     VCPU27: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.672991 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.673036 (XEN) GICH_LRs (vcpu 27) mask=0
Apr 24 12:01:17.684921 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.684977 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.685019 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.685059 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.696918 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.696973 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.697015 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.697056 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.697096 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.697135 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.708918 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.708974 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.709016 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.709057 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.709098 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.709137 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.720933 (XEN) No periodic timer
Apr 24 12:01:17.720989 (XEN)   UNIT28 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.721037 (XEN)     VCPU28: CPU70 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.732927 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.732985 (XEN) GICH_LRs (vcpu 28) mask=0
Apr 24 12:01:17.733030 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.733071 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.744883 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.744940 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.744982 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.745022 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.745061 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.745100 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.756928 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.756985 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.757026 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.757067 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.757107 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.757146 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.768939 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.768995 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.769037 (XEN) No periodic timer
Apr 24 12:01:17.769079 (XEN)   UNIT29 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.769124 (XEN)     VCPU29: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.780930 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.780988 (XEN) GICH_LRs (vcpu 29) mask=0
Apr 24 12:01:17.781031 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.792929 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.792985 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.793026 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.793066 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.793105 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.793145 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.804931 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.804987 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.805029 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.805069 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.805109 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.805149 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.816925 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.816980 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.817022 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.817063 (XEN) No periodic timer
Apr 24 12:01:17.828923 (XEN)   UNIT30 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.828986 (XEN)     VCPU30: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.829038 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.840927 (XEN) GICH_LRs (vcpu 30) mask=0
Apr 24 12:01:17.840985 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.841027 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.841067 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.841107 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.852917 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.852974 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.853016 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.853055 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.853112 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.853155 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.864927 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.864983 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.865025 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.865066 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.865106 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.865146 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.876927 (XEN) No periodic timer
Apr 24 12:01:17.876983 (XEN)   UNIT31 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.877031 (XEN)     VCPU31: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.888869 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.888869 (XEN) GICH_LRs (vcpu 31) mask=0
Apr 24 12:01:17.888869 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.888869 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.900947 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.901006 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.901049 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.901089 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.901129 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.901169 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.912936 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.912992 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.913035 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.913076 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.913116 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.913155 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.924920 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.924976 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.925018 (XEN) No periodic timer
Apr 24 12:01:17.925060 (XEN)   UNIT32 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.925105 (XEN)     VCPU32: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.936926 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.936983 (XEN) GICH_LRs (vcpu 32) mask=0
Apr 24 12:01:17.948927 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.948983 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.949025 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.949065 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:17.949105 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:17.949144 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:17.960930 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:17.960985 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:17.961027 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:17.961066 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:17.961106 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:17.961145 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:17.972927 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:17.972982 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:17.973025 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:17.973065 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:17.973105 (XEN) No periodic timer
Apr 24 12:01:17.984940 (XEN)   UNIT33 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:17.985001 (XEN)     VCPU33: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:17.985052 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:17.996942 (XEN) GICH_LRs (vcpu 33) mask=0
Apr 24 12:01:17.997000 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:17.997042 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:17.997082 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:17.997122 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.008942 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.008998 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.009040 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.009080 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.009120 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.009159 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.020926 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.020982 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.021025 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.021065 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.021104 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.021144 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.032927 (XEN) No periodic timer
Apr 24 12:01:18.032983 (XEN)   UNIT34 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.033031 (XEN)     VCPU34: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.044935 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.044993 (XEN) GICH_LRs (vcpu 34) mask=0
Apr 24 12:01:18.045038 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.045079 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.056925 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.056999 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.057045 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.057085 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.057125 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.057164 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.068921 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.068977 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.069019 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.069060 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.069099 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.080790 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.080821 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.080844 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.080866 (XEN) No periodic timer
Apr 24 12:01:18.080889 (XEN)   UNIT35 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.092759 (XEN)     VCPU35: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.092789 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.092813 (XEN) GICH_LRs (vcpu 35) mask=0
Apr 24 12:01:18.104906 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.104962 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.105003 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.105043 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.105082 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.116926 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.116982 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.117024 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.117065 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.117105 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.117145 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.128929 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.128985 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.129027 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.129067 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.129106 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.129146 (XEN) No periodic timer
Apr 24 12:01:18.140927 (XEN)   UNIT36 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.140988 (XEN)     VCPU36: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.141039 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.152933 (XEN) GICH_LRs (vcpu 36) mask=0
Apr 24 12:01:18.152991 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.153033 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.153074 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.153114 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.164931 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.164987 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.165030 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.165070 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.165109 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.165148 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.176921 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.176977 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.177019 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.177060 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.177100 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.188908 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.188965 (XEN) No periodic timer
Apr 24 12:01:18.189008 (XEN)   UNIT37 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.189054 (XEN)     VCPU37: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.200937 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.200994 (XEN) GICH_LRs (vcpu 37) mask=0
Apr 24 12:01:18.201039 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.212929 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.212985 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.213026 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.213067 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.213106 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.213145 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.224925 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.224980 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.225023 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.225063 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.225103 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.225142 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.236927 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.236983 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.237025 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.237066 (XEN) No periodic timer
Apr 24 12:01:18.237106 (XEN)   UNIT38 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.248938 (XEN)     VCPU38: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.249003 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.249065 (XEN) GICH_LRs (vcpu 38) mask=0
Apr 24 12:01:18.260909 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.260965 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.261007 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.261047 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.261087 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.272931 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.272987 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.273029 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.273069 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.273108 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.273147 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.284915 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.284971 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.285014 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.285054 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.285094 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.285134 (XEN) No periodic timer
Apr 24 12:01:18.296932 (XEN)   UNIT39 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.296994 (XEN)     VCPU39: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.297044 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.308936 (XEN) GICH_LRs (vcpu 39) mask=0
Apr 24 12:01:18.308993 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.309035 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.309075 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.320921 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.320977 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.321020 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.321060 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.321100 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.321139 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.332927 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.332982 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.333025 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.333065 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.333104 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.344934 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.344991 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.345033 (XEN) No periodic timer
Apr 24 12:01:18.345074 (XEN)   UNIT40 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.345119 (XEN)     VCPU40: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.356931 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.356989 (XEN) GICH_LRs (vcpu 40) mask=0
Apr 24 12:01:18.357033 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.368939 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.368995 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.369036 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.369076 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.369115 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.369155 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.380926 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.380981 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.381023 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.381064 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.381104 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.381145 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.392931 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.392987 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.393029 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.393070 (XEN) No periodic timer
Apr 24 12:01:18.393110 (XEN)   UNIT41 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.404942 (XEN)     VCPU41: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.405006 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.416923 (XEN) GICH_LRs (vcpu 41) mask=0
Apr 24 12:01:18.416982 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.417025 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.417065 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.417105 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.417144 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.428928 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.428983 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.429026 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.429066 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.429106 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.429145 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.440931 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.440987 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.441029 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.441069 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.441109 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.441149 (XEN) No periodic timer
Apr 24 12:01:18.452937 (XEN)   UNIT42 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.452999 (XEN)     VCPU42: CPU9 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.464933 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.464991 (XEN) GICH_LRs (vcpu 42) mask=0
Apr 24 12:01:18.465035 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.465075 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.476919 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.476975 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.477017 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.477058 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.477097 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.477136 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.488937 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.488994 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.489036 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.489076 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.489116 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.489155 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.500928 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.500984 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.501026 (XEN) No periodic timer
Apr 24 12:01:18.501068 (XEN)   UNIT43 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.501114 (XEN)     VCPU43: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.512929 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.512987 (XEN) GICH_LRs (vcpu 43) mask=0
Apr 24 12:01:18.513031 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.524918 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.524974 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.525016 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.525056 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.525095 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.525135 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.536925 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.536981 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.537023 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.537063 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.537103 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.537142 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.548938 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.548993 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.549035 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.549075 (XEN) No periodic timer
Apr 24 12:01:18.549116 (XEN)   UNIT44 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.560940 (XEN)     VCPU44: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.561004 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.572925 (XEN) GICH_LRs (vcpu 44) mask=0
Apr 24 12:01:18.572983 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.573026 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.573066 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.573106 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.584933 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.584989 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.585031 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.585071 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.585110 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.585150 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.596925 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.596980 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.597023 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.597063 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.597103 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.597142 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.608928 (XEN) No periodic timer
Apr 24 12:01:18.608984 (XEN)   UNIT45 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.609031 (XEN)     VCPU45: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.620926 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.620984 (XEN) GICH_LRs (vcpu 45) mask=0
Apr 24 12:01:18.621028 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.621069 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.632924 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.632980 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.633023 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.633063 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.633102 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.633141 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.644928 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.644984 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.645026 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.645067 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.645107 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.645164 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.656924 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.656980 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.657022 (XEN) No periodic timer
Apr 24 12:01:18.657064 (XEN)   UNIT46 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.657110 (XEN)     VCPU46: CPU72 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.668945 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.669003 (XEN) GICH_LRs (vcpu 46) mask=0
Apr 24 12:01:18.680917 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.680973 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.681015 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.681055 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.681095 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.681135 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.692923 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.692980 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.693022 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.693062 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.693102 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.693142 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.704919 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.704975 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.705017 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.705058 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.705097 (XEN) No periodic timer
Apr 24 12:01:18.716930 (XEN)   UNIT47 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.716992 (XEN)     VCPU47: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.717042 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.728946 (XEN) GICH_LRs (vcpu 47) mask=0
Apr 24 12:01:18.729003 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.729045 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.729085 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.729124 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.740929 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.740985 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.741027 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.741067 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.741107 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.741146 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.752932 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.752989 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.753031 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.753071 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.753110 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.753150 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.764941 (XEN) No periodic timer
Apr 24 12:01:18.764996 (XEN)   UNIT48 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.765044 (XEN)     VCPU48: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.776932 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.776990 (XEN) GICH_LRs (vcpu 48) mask=0
Apr 24 12:01:18.777035 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.777076 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.788925 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.788981 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.789023 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.789063 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.789102 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.789142 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.800925 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.800981 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.801023 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.801063 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.801102 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.801142 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.812933 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.812988 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.813030 (XEN) No periodic timer
Apr 24 12:01:18.813072 (XEN)   UNIT49 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.824928 (XEN)     VCPU49: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.824992 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.825037 (XEN) GICH_LRs (vcpu 49) mask=0
Apr 24 12:01:18.836928 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.836984 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.837026 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.837066 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.837106 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.848931 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.848988 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.849030 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.849088 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.849131 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.849172 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.860925 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.860982 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.861023 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.861064 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.861103 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.861143 (XEN) No periodic timer
Apr 24 12:01:18.872927 (XEN)   UNIT50 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.872988 (XEN)     VCPU50: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.873039 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.884933 (XEN) GICH_LRs (vcpu 50) mask=0
Apr 24 12:01:18.884990 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.885033 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.885073 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.885112 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.896933 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.896988 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.897029 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.897069 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.897109 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.897148 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.908946 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.909001 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.909044 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.909085 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.909125 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.920928 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.920984 (XEN) No periodic timer
Apr 24 12:01:18.921028 (XEN)   UNIT51 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.921073 (XEN)     VCPU51: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.932925 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.932983 (XEN) GICH_LRs (vcpu 51) mask=0
Apr 24 12:01:18.933027 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.933068 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.944934 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.944990 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.945032 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:18.945072 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:18.945111 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:18.945151 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:18.956918 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:18.956973 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:18.957015 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:18.957055 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:18.957095 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:18.968947 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:18.969002 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:18.969045 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:18.969085 (XEN) No periodic timer
Apr 24 12:01:18.969126 (XEN)   UNIT52 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:18.980926 (XEN)     VCPU52: CPU73 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:18.980990 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:18.981035 (XEN) GICH_LRs (vcpu 52) mask=0
Apr 24 12:01:18.992941 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:18.992997 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:18.993039 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:18.993079 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:18.993118 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.004933 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.004989 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.005031 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.005071 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.005111 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.005151 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.016931 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.016987 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.017029 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.017069 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.017109 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.017148 (XEN) No periodic timer
Apr 24 12:01:19.028933 (XEN)   UNIT53 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.028995 (XEN)     VCPU53: CPU89 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.040917 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.040978 (XEN) GICH_LRs (vcpu 53) mask=0
Apr 24 12:01:19.041024 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.041065 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.041104 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.052923 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.052997 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.053042 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.053083 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.053122 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.053162 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.064920 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.064976 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.065019 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.065059 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.065099 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.065138 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.076917 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.076973 (XEN) No periodic timer
Apr 24 12:01:19.077016 (XEN)   UNIT54 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.077063 (XEN)     VCPU54: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.088925 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.088983 (XEN) GICH_LRs (vcpu 54) mask=0
Apr 24 12:01:19.089027 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.100926 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.100981 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.101024 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.101064 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.101104 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.101143 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.112924 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.112980 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.113021 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.113061 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.113101 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.113140 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.124929 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.124984 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.125026 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.125067 (XEN) No periodic timer
Apr 24 12:01:19.125107 (XEN)   UNIT55 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.136925 (XEN)     VCPU55: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.136989 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.148923 (XEN) GICH_LRs (vcpu 55) mask=0
Apr 24 12:01:19.148981 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.149024 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.149065 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.149105 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.149145 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.160929 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.160984 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.161026 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.161067 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.161106 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.161145 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.172933 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.172989 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.173032 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.173072 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.173112 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.173152 (XEN) No periodic timer
Apr 24 12:01:19.184922 (XEN)   UNIT56 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.184983 (XEN)     VCPU56: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.196928 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.196987 (XEN) GICH_LRs (vcpu 56) mask=0
Apr 24 12:01:19.197032 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.197073 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.197113 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.208917 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.208973 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.209015 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.209055 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.209095 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.220933 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.220988 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.221031 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.221071 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.221111 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.221151 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.232922 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.232979 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.233021 (XEN) No periodic timer
Apr 24 12:01:19.233062 (XEN)   UNIT57 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.233107 (XEN)     VCPU57: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.244931 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.245008 (XEN) GICH_LRs (vcpu 57) mask=0
Apr 24 12:01:19.256916 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.256974 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.257016 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.257056 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.257096 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.257135 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.268936 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.268993 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.269036 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.269076 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.269116 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.269156 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.280922 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.280979 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.281021 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.281061 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.281101 (XEN) No periodic timer
Apr 24 12:01:19.281141 (XEN)   UNIT58 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.292927 (XEN)     VCPU58: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.292991 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.304933 (XEN) GICH_LRs (vcpu 58) mask=0
Apr 24 12:01:19.304992 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.305034 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.305073 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.305112 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.305151 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.316937 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.316992 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.317034 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.317074 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.317113 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.317152 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.328929 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.328985 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.329027 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.329068 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.329107 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.340909 (XEN) No periodic timer
Apr 24 12:01:19.340968 (XEN)   UNIT59 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.341015 (XEN)     VCPU59: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.352927 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.352985 (XEN) GICH_LRs (vcpu 59) mask=0
Apr 24 12:01:19.353029 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.353070 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.364922 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.364978 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.365020 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.365059 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.365099 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.365139 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.376924 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.376980 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.377022 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.377062 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.377102 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.377142 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.388925 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.388981 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.389023 (XEN) No periodic timer
Apr 24 12:01:19.389064 (XEN)   UNIT60 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.400923 (XEN)     VCPU60: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.400989 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.401034 (XEN) GICH_LRs (vcpu 60) mask=0
Apr 24 12:01:19.412931 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.412987 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.413029 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.413070 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.413109 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.413148 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.424921 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.424978 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.425020 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.425060 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.425099 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.425139 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.436918 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.436974 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.437017 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.437057 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.437098 (XEN) No periodic timer
Apr 24 12:01:19.437138 (XEN)   UNIT61 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.448943 (XEN)     VCPU61: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.449008 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.460923 (XEN) GICH_LRs (vcpu 61) mask=0
Apr 24 12:01:19.460980 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.461023 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.461063 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.461103 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.472933 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.472989 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.473031 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.473071 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.473110 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.473149 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.484924 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.484980 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.485022 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.485063 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.485102 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.496925 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.496982 (XEN) No periodic timer
Apr 24 12:01:19.497024 (XEN)   UNIT62 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.497071 (XEN)     VCPU62: CPU36 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.508876 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.508934 (XEN) GICH_LRs (vcpu 62) mask=0
Apr 24 12:01:19.508978 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.509020 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.520927 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.520982 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.521024 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.521064 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.521103 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.521142 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.532926 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.532982 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.533024 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.533063 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.533103 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.533142 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.544922 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.544978 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.545019 (XEN) No periodic timer
Apr 24 12:01:19.545060 (XEN)   UNIT63 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.556911 (XEN)     VCPU63: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.556976 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.557021 (XEN) GICH_LRs (vcpu 63) mask=0
Apr 24 12:01:19.568935 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.568991 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.569033 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.569073 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.569113 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.569152 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.580927 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.580983 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.581025 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.581065 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.581104 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.581144 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.592910 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.592966 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.593009 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.593050 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.593089 (XEN) No periodic timer
Apr 24 12:01:19.604929 (XEN)   UNIT64 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.604991 (XEN)     VCPU64: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.605042 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.616928 (XEN) GICH_LRs (vcpu 64) mask=0
Apr 24 12:01:19.616986 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.617028 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.617068 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.628918 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.628975 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.629017 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.629058 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.629097 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.629136 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.640925 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.640981 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.641024 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.641065 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.641123 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.641166 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.652925 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.652982 (XEN) No periodic timer
Apr 24 12:01:19.653025 (XEN)   UNIT65 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.653071 (XEN)     VCPU65: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.664946 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.665003 (XEN) GICH_LRs (vcpu 65) mask=0
Apr 24 12:01:19.665047 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.665088 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.676928 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.676983 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.677025 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.677065 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.677104 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.677143 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.688924 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.688980 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.689022 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.689061 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.689101 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.689140 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.700929 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.700984 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.701026 (XEN) No periodic timer
Apr 24 12:01:19.701068 (XEN)   UNIT66 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.712928 (XEN)     VCPU66: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.712992 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.713038 (XEN) GICH_LRs (vcpu 66) mask=0
Apr 24 12:01:19.724933 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.724988 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.725030 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.725071 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.725111 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.736920 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.736977 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.737019 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.737059 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.737099 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.737139 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.748930 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.748986 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.749027 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.749067 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.749107 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.749146 (XEN) No periodic timer
Apr 24 12:01:19.760919 (XEN)   UNIT67 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.760980 (XEN)     VCPU67: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.772950 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.773008 (XEN) GICH_LRs (vcpu 67) mask=0
Apr 24 12:01:19.773053 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.773094 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.773134 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.784928 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.784984 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.785026 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.785067 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.785107 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.785146 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.796922 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.796979 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.797021 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.797062 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.797102 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.797141 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.808928 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.808984 (XEN) No periodic timer
Apr 24 12:01:19.809027 (XEN)   UNIT68 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.809073 (XEN)     VCPU68: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.820942 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.821000 (XEN) GICH_LRs (vcpu 68) mask=0
Apr 24 12:01:19.821044 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.832920 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.832976 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.833019 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.833059 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.833099 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.833138 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.844913 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.844970 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.845030 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.845075 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.845116 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.856923 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.856981 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.857024 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.857064 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.857104 (XEN) No periodic timer
Apr 24 12:01:19.857146 (XEN)   UNIT69 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.868925 (XEN)     VCPU69: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.868989 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.880932 (XEN) GICH_LRs (vcpu 69) mask=0
Apr 24 12:01:19.880991 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.881033 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.881073 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.881113 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.881152 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.892925 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.892980 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.893022 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.893062 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.893102 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.893141 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.904927 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.904983 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.905025 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.905064 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.905104 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.905144 (XEN) No periodic timer
Apr 24 12:01:19.916928 (XEN)   UNIT70 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.916989 (XEN)     VCPU70: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.928925 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.928984 (XEN) GICH_LRs (vcpu 70) mask=0
Apr 24 12:01:19.929027 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.929068 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.929107 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.940918 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.940974 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.941016 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:19.941056 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:19.941096 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:19.941135 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:19.952841 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:19.952841 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:19.952841 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:19.952841 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:19.952841 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:19.952841 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:19.964941 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:19.965001 (XEN) No periodic timer
Apr 24 12:01:19.965043 (XEN)   UNIT71 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:19.965089 (XEN)     VCPU71: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:19.976918 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:19.976976 (XEN) GICH_LRs (vcpu 71) mask=0
Apr 24 12:01:19.988887 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:19.988943 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:19.988986 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:19.989026 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:19.989066 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:19.989106 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.000924 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.000981 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.001023 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.001063 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.001102 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.001142 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.012905 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.012961 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.013003 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.013043 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.013083 (XEN) No periodic timer
Apr 24 12:01:20.013123 (XEN)   UNIT72 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.024931 (XEN)     VCPU72: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.024996 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.036923 (XEN) GICH_LRs (vcpu 72) mask=0
Apr 24 12:01:20.036981 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.037023 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.037064 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.037103 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.037166 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.048918 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.048973 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.049015 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.049056 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.049095 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.049134 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.060921 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.060977 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.061019 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.061059 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.061098 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.072927 (XEN) No periodic timer
Apr 24 12:01:20.072983 (XEN)   UNIT73 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.073031 (XEN)     VCPU73: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.084938 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.084997 (XEN) GICH_LRs (vcpu 73) mask=0
Apr 24 12:01:20.085041 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.085081 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.085120 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.096916 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.096972 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.097014 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.097054 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.097093 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.108928 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.108984 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.109025 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.109066 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.109105 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.109144 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.120924 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.120981 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.121023 (XEN) No periodic timer
Apr 24 12:01:20.121065 (XEN)   UNIT74 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.132794 (XEN)     VCPU74: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.132794 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.132794 (XEN) GICH_LRs (vcpu 74) mask=0
Apr 24 12:01:20.144781 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.144781 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.144781 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.144781 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.144781 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.144781 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.156785 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.156785 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.156785 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.156785 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.156785 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.156785 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.168789 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.168789 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.168789 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.168789 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.168789 (XEN) No periodic timer
Apr 24 12:01:20.168789 (XEN)   UNIT75 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.180790 (XEN)     VCPU75: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.180790 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.192784 (XEN) GICH_LRs (vcpu 75) mask=0
Apr 24 12:01:20.192784 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.192784 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.192784 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.192784 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.204777 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.204777 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.204777 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.204777 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.204777 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.204777 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.216774 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.216774 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.216774 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.216774 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.216774 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.216774 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.228779 (XEN) No periodic timer
Apr 24 12:01:20.228779 (XEN)   UNIT76 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.228779 (XEN)     VCPU76: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.240785 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.240785 (XEN) GICH_LRs (vcpu 76) mask=0
Apr 24 12:01:20.240785 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.240785 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.252781 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.252781 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.252781 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.252781 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.252781 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.252781 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.264774 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.264774 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.264774 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.264774 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.264774 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.264774 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.276782 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.276782 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.276782 (XEN) No periodic timer
Apr 24 12:01:20.276782 (XEN)   UNIT77 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.288716 (XEN)     VCPU77: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.288716 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.288716 (XEN) GICH_LRs (vcpu 77) mask=0
Apr 24 12:01:20.300748 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.300748 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.300748 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.300748 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.300748 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.300748 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.312768 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.312768 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.312768 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.312768 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.312768 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.312768 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.324700 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.324700 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.324700 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.324700 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.324700 (XEN) No periodic timer
Apr 24 12:01:20.324700 (XEN)   UNIT78 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.336767 (XEN)     VCPU78: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.336767 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.348961 (XEN) GICH_LRs (vcpu 78) mask=0
Apr 24 12:01:20.349043 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.349100 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.349143 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.360922 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.360979 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.361020 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.361061 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.361100 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.361140 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.372884 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.372940 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.372983 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.373024 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.373064 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.373103 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.384839 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.384887 (XEN) No periodic timer
Apr 24 12:01:20.384930 (XEN)   UNIT79 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.384977 (XEN)     VCPU79: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.396816 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.396867 (XEN) GICH_LRs (vcpu 79) mask=0
Apr 24 12:01:20.396911 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.396951 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.408859 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.408907 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.408949 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.408991 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.409031 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.409070 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.420853 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.420901 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.420942 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.420982 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.421023 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.432854 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.432902 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.432942 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.432983 (XEN) No periodic timer
Apr 24 12:01:20.433023 (XEN)   UNIT80 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.444847 (XEN)     VCPU80: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.444904 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.444948 (XEN) GICH_LRs (vcpu 80) mask=0
Apr 24 12:01:20.456869 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.456925 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.456968 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.457010 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.457051 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.457092 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.468856 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.468912 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.468954 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.468995 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.469035 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.469076 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.484859 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.484915 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.484957 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.484998 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.485039 (XEN) No periodic timer
Apr 24 12:01:20.485124 (XEN)   UNIT81 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.492767 (XEN)     VCPU81: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.504864 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.504928 (XEN) GICH_LRs (vcpu 81) mask=0
Apr 24 12:01:20.504973 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.505013 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.505054 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.516928 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.516983 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.517025 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.517066 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.517105 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.517145 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.528924 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.528980 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.529022 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.529063 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.529103 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.529142 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.540918 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.540974 (XEN) No periodic timer
Apr 24 12:01:20.541017 (XEN)   UNIT82 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.541064 (XEN)     VCPU82: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.552917 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.552975 (XEN) GICH_LRs (vcpu 82) mask=0
Apr 24 12:01:20.553020 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.564918 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.564974 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.565016 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.565057 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.565097 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.565137 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.576911 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.576967 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.577009 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.577050 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.577090 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.577130 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.588917 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.588974 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.589016 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.589058 (XEN) No periodic timer
Apr 24 12:01:20.589098 (XEN)   UNIT83 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.600921 (XEN)     VCPU83: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.600985 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.601031 (XEN) GICH_LRs (vcpu 83) mask=0
Apr 24 12:01:20.612912 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.612969 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.613011 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.613053 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.613093 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.624918 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.624974 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.625016 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.625057 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.625097 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.625137 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.636923 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.636979 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.637022 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.637082 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.637127 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.648911 (XEN) No periodic timer
Apr 24 12:01:20.648969 (XEN)   UNIT84 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.649016 (XEN)     VCPU84: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.660919 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.660978 (XEN) GICH_LRs (vcpu 84) mask=0
Apr 24 12:01:20.661023 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.661064 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.661104 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.672928 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.672984 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.673027 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.673067 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.673107 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.673147 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.684772 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.684803 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.684826 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.684848 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.684870 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.684892 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.696738 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.696763 (XEN) No periodic timer
Apr 24 12:01:20.696786 (XEN)   UNIT85 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.696812 (XEN)     VCPU85: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.708839 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.708889 (XEN) GICH_LRs (vcpu 85) mask=0
Apr 24 12:01:20.708933 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.720870 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.720917 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.720959 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.721000 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.721040 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.721079 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.732859 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.732906 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.732947 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.732988 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.733028 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.744863 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.744910 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.744951 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.744992 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.745032 (XEN) No periodic timer
Apr 24 12:01:20.745071 (XEN)   UNIT86 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.756870 (XEN)     VCPU86: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.756924 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.768928 (XEN) GICH_LRs (vcpu 86) mask=0
Apr 24 12:01:20.768987 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.769030 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.769071 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.769111 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.780921 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.780979 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.781022 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.781062 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.781102 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.781142 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.781181 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.792924 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.792980 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.793022 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.793063 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.793103 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.804915 (XEN) No periodic timer
Apr 24 12:01:20.804972 (XEN)   UNIT87 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.805021 (XEN)     VCPU87: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.816906 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.816967 (XEN) GICH_LRs (vcpu 87) mask=0
Apr 24 12:01:20.817012 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.817054 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.817094 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.828928 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.828985 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.829028 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.829069 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.829110 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.829150 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.840941 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.840999 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.841041 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.841081 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.841121 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.841160 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.852935 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.852991 (XEN) No periodic timer
Apr 24 12:01:20.853034 (XEN)   UNIT88 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.853080 (XEN)     VCPU88: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.864938 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.864996 (XEN) GICH_LRs (vcpu 88) mask=0
Apr 24 12:01:20.876919 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.876975 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.877018 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.877058 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.877097 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.877136 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.888934 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.888990 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.889032 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.889073 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.889112 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.889153 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.900920 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.900976 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.901019 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.901059 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.901099 (XEN) No periodic timer
Apr 24 12:01:20.901140 (XEN)   UNIT89 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.912956 (XEN)     VCPU89: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.913019 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.924931 (XEN) GICH_LRs (vcpu 89) mask=0
Apr 24 12:01:20.924989 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.925031 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.925071 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.925111 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.936923 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.936979 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.937021 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.937061 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.937101 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.937140 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.948912 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.948968 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.949010 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.949051 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:20.949091 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:20.949131 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:20.960931 (XEN) No periodic timer
Apr 24 12:01:20.960988 (XEN)   UNIT90 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:20.961036 (XEN)     VCPU90: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:20.972925 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:20.972983 (XEN) GICH_LRs (vcpu 90) mask=0
Apr 24 12:01:20.973028 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:20.973069 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:20.973109 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:20.984909 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:20.984964 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:20.985006 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:20.985046 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:20.985086 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:20.996924 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:20.996982 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:20.997024 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:20.997065 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:20.997105 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:20.997144 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:21.008942 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:21.008997 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:21.009041 (XEN) No periodic timer
Apr 24 12:01:21.009082 (XEN)   UNIT91 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:21.020931 (XEN)     VCPU91: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:21.020996 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:21.021041 (XEN) GICH_LRs (vcpu 91) mask=0
Apr 24 12:01:21.032927 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:21.032983 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:21.033026 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:21.033067 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:21.033106 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:21.033164 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:21.044929 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:21.044985 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:21.045027 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:21.045067 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:21.045107 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:21.045147 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:21.056923 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:21.056979 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:21.057020 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:21.057060 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:21.057100 (XEN) No periodic timer
Apr 24 12:01:21.057140 (XEN)   UNIT92 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:21.068942 (XEN)     VCPU92: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:21.069006 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:21.080930 (XEN) GICH_LRs (vcpu 92) mask=0
Apr 24 12:01:21.080988 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:21.081030 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:21.081070 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:21.081109 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:21.092928 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:21.092985 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:21.093027 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:21.093068 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:21.093108 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:21.093148 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:21.104933 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:21.104990 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:21.105032 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:21.105072 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:21.105112 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:21.105152 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:21.116915 (XEN) No periodic timer
Apr 24 12:01:21.116971 (XEN)   UNIT93 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:21.117019 (XEN)     VCPU93: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:21.128931 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:21.128989 (XEN) GICH_LRs (vcpu 93) mask=0
Apr 24 12:01:21.129034 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:21.140932 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:21.140990 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:21.141032 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:21.141073 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:21.141113 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:21.141152 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:21.152931 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:21.152988 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:21.153030 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:21.153070 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:21.153110 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:21.153149 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:21.164936 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:21.164992 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:21.165035 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:21.165075 (XEN) No periodic timer
Apr 24 12:01:21.165116 (XEN)   UNIT94 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:21.176940 (XEN)     VCPU94: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:21.177004 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:21.177049 (XEN) GICH_LRs (vcpu 94) mask=0
Apr 24 12:01:21.188936 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:21.188992 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:21.189034 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:21.189074 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:21.189114 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:21.189154 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:21.200919 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:21.200975 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:21.201016 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:21.201056 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:21.201095 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:21.201135 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:21.212942 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:21.212998 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:21.213040 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:21.213081 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:21.213121 (XEN) No periodic timer
Apr 24 12:01:21.224930 (XEN)   UNIT95 affinities: hard={0-95} soft={0-95}
Apr 24 12:01:21.224991 (XEN)     VCPU95: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 24 12:01:21.225042 (XEN)     pause_count=0 pause_flags=1
Apr 24 12:01:21.236939 (XEN) GICH_LRs (vcpu 95) mask=0
Apr 24 12:01:21.237016 (XEN)    VCPU_LR[0]=0
Apr 24 12:01:21.237062 (XEN)    VCPU_LR[1]=0
Apr 24 12:01:21.237103 (XEN)    VCPU_LR[2]=0
Apr 24 12:01:21.237143 (XEN)    VCPU_LR[3]=0
Apr 24 12:01:21.248918 (XEN)    VCPU_LR[4]=0
Apr 24 12:01:21.248973 (XEN)    VCPU_LR[5]=0
Apr 24 12:01:21.249015 (XEN)    VCPU_LR[6]=0
Apr 24 12:01:21.249055 (XEN)    VCPU_LR[7]=0
Apr 24 12:01:21.249095 (XEN)    VCPU_LR[8]=0
Apr 24 12:01:21.260928 (XEN)    VCPU_LR[9]=0
Apr 24 12:01:21.260984 (XEN)    VCPU_LR[10]=0
Apr 24 12:01:21.261026 (XEN)    VCPU_LR[11]=0
Apr 24 12:01:21.261067 (XEN)    VCPU_LR[12]=0
Apr 24 12:01:21.261108 (XEN)    VCPU_LR[13]=0
Apr 24 12:01:21.261148 (XEN)    VCPU_LR[14]=0
Apr 24 12:01:21.272948 (XEN)    VCPU_LR[15]=0
Apr 24 12:01:21.273003 (XEN) No periodic timer
Apr 24 12:01:21.273046 (XEN) Notifying guest 0:0 (virq 1, port 0)
Apr 24 12:01:21.273091 (XEN) Notifying guest 0:1 (virq 1, port 0)
Apr 24 12:01:21.284928 (XEN) Notifying guest 0:2 (virq 1, port 0)
Apr 24 12:01:21.284988 (XEN) Notifying guest 0:3 (virq 1, port 0)
Apr 24 12:01:21.285033 (XEN) Notifying guest 0:4 (virq 1, port 0)
Apr 24 12:01:21.296924 (XEN) Notifying guest 0:5 (virq 1, port 0)
Apr 24 12:01:21.296985 (XEN) Notifying guest 0:6 (virq 1, port 0)
Apr 24 12:01:21.297030 (XEN) Notifying guest 0:7 (virq 1, port 0)
Apr 24 12:01:21.308918 (XEN) Notifying guest 0:8 (virq 1, port 0)
Apr 24 12:01:21.308979 (XEN) Notifying guest 0:9 (virq 1, port 0)
Apr 24 12:01:21.309024 (XEN) Notifying guest 0:10 (virq 1, port 0)
Apr 24 12:01:21.309067 (XEN) Notifying guest 0:11 (virq 1, port 0)
Apr 24 12:01:21.320943 (XEN) Notifying guest 0:12 (virq 1, port 0)
Apr 24 12:01:21.321001 (XEN) Notifying guest 0:13 (virq 1, port 0)
Apr 24 12:01:21.321046 (XEN) Notifying guest 0:14 (virq 1, port 0)
Apr 24 12:01:21.332930 (XEN) Notifying guest 0:15 (virq 1, port 0)
Apr 24 12:01:21.332989 (XEN) Notifying guest 0:16 (virq 1, port 0)
Apr 24 12:01:21.333035 (XEN) Notifying guest 0:17 (virq 1, port 0)
Apr 24 12:01:21.344931 (XEN) Notifying guest 0:18 (virq 1, port 0)
Apr 24 12:01:21.344990 (XEN) Notifying guest 0:19 (virq 1, port 0)
Apr 24 12:01:21.345035 (XEN) Notifying guest 0:20 (virq 1, port 0)
Apr 24 12:01:21.356929 (XEN) Notifying guest 0:21 (virq 1, port 0)
Apr 24 12:01:21.356987 (XEN) Notifying guest 0:22 (virq 1, port 0)
Apr 24 12:01:21.357033 (XEN) Notifying guest 0:23 (virq 1, port 0)
Apr 24 12:01:21.368928 (XEN) Notifying guest 0:24 (virq 1, port 0)
Apr 24 12:01:21.368987 (XEN) Notifying guest 0:25 (virq 1, port 0)
Apr 24 12:01:21.369032 (XEN) Notifying guest 0:26 (virq 1, port 0)
Apr 24 12:01:21.380926 (XEN) Notifying guest 0:27 (virq 1, port 0)
Apr 24 12:01:21.380985 (XEN) Notifying guest 0:28 (virq 1, port 0)
Apr 24 12:01:21.381030 (XEN) Notifying guest 0:29 (virq 1, port 0)
Apr 24 12:01:21.392934 (XEN) Notifying guest 0:30 (virq 1, port 0)
Apr 24 12:01:21.392993 (XEN) Notifying guest 0:31 (virq 1, port 0)
Apr 24 12:01:21.393037 (XEN) Notifying guest 0:32 (virq 1, port 0)
Apr 24 12:01:21.404931 (XEN) Notifying guest 0:33 (virq 1, port 0)
Apr 24 12:01:21.404990 (XEN) Notifying guest 0:34 (virq 1, port 0)
Apr 24 12:01:21.405035 (XEN) Notifying guest 0:35 (virq 1, port 0)
Apr 24 12:01:21.416932 (XEN) Notifying guest 0:36 (virq 1, port 0)
Apr 24 12:01:21.416991 (XEN) Notifying guest 0:37 (virq 1, port 0)
Apr 24 12:01:21.417036 (XEN) Notifying guest 0:38 (virq 1, port 0)
Apr 24 12:01:21.428926 (XEN) Notifying guest 0:39 (virq 1, port 0)
Apr 24 12:01:21.428985 (XEN) Notifying guest 0:40 (virq 1, port 0)
Apr 24 12:01:21.429030 (XEN) Notifying guest 0:41 (virq 1, port 0)
Apr 24 12:01:21.440932 (XEN) Notifying guest 0:42 (virq 1, port 0)
Apr 24 12:01:21.440991 (XEN) Notifying guest 0:43 (virq 1, port 0)
Apr 24 12:01:21.441036 (XEN) Notifying guest 0:44 (virq 1, port 0)
Apr 24 12:01:21.452920 (XEN) Notifying guest 0:45 (virq 1, port 0)
Apr 24 12:01:21.452979 (XEN) Notifying guest 0:46 (virq 1, port 0)
Apr 24 12:01:21.453025 (XEN) Notifying guest 0:47 (virq 1, port 0)
Apr 24 12:01:21.464931 (XEN) Notifying guest 0:48 (virq 1, port 0)
Apr 24 12:01:21.465008 (XEN) Notifying guest 0:49 (virq 1, port 0)
Apr 24 12:01:21.465057 (XEN) Notifying guest 0:50 (virq 1, port 0)
Apr 24 12:01:21.476919 (XEN) Notifying guest 0:51 (virq 1, port 0)
Apr 24 12:01:21.476979 (XEN) Notifying guest 0:52 (virq 1, port 0)
Apr 24 12:01:21.477025 (XEN) Notifying guest 0:53 (virq 1, port 0)
Apr 24 12:01:21.488933 (XEN) Notifying guest 0:54 (virq 1, port 0)
Apr 24 12:01:21.488993 (XEN) Notifying guest 0:55 (virq 1, port 0)
Apr 24 12:01:21.489039 (XEN) Notifying guest 0:56 (virq 1, port 0)
Apr 24 12:01:21.500909 (XEN) Notifying guest 0:57 (virq 1, port 0)
Apr 24 12:01:21.500969 (XEN) Notifying guest 0:58 (virq 1, port 0)
Apr 24 12:01:21.501014 (XEN) Notifying guest 0:59 (virq 1, port 0)
Apr 24 12:01:21.512932 (XEN) Notifying guest 0:60 (virq 1, port 0)
Apr 24 12:01:21.512992 (XEN) Notifying guest 0:61 (virq 1, port 0)
Apr 24 12:01:21.513037 (XEN) Notifying guest 0:62 (virq 1, port 0)
Apr 24 12:01:21.524894 (XEN) Notifying guest 0:63 (virq 1, port 0)
Apr 24 12:01:21.524953 (XEN) Notifying guest 0:64 (virq 1, port 0)
Apr 24 12:01:21.524998 (XEN) Notifying guest 0:65 (virq 1, port 0)
Apr 24 12:01:21.536928 (XEN) Notifying guest 0:66 (virq 1, port 0)
Apr 24 12:01:21.536988 (XEN) Notifying guest 0:67 (virq 1, port 0)
Apr 24 12:01:21.537033 (XEN) Notifying guest 0:68 (virq 1, port 0)
Apr 24 12:01:21.548901 (XEN) Notifying guest 0:69 (virq 1, port 0)
Apr 24 12:01:21.548961 (XEN) Notifying guest 0:70 (virq 1, port 0)
Apr 24 12:01:21.549006 (XEN) Notifying guest 0:71 (virq 1, port 0)
Apr 24 12:01:21.560926 (XEN) Notifying guest 0:72 (virq 1, port 0)
Apr 24 12:01:21.560986 (XEN) Notifying guest 0:73 (virq 1, port 0)
Apr 24 12:01:21.561032 (XEN) Notifying guest 0:74 (virq 1, port 0)
Apr 24 12:01:21.572929 (XEN) Notifying guest 0:75 (virq 1, port 0)
Apr 24 12:01:21.572989 (XEN) Notifying guest 0:76 (virq 1, port 0)
Apr 24 12:01:21.573034 (XEN) Notifying guest 0:77 (virq 1, port 0)
Apr 24 12:01:21.584938 (XEN) Notifying guest 0:78 (virq 1, port 0)
Apr 24 12:01:21.584998 (XEN) Notifying guest 0:79 (virq 1, port 0)
Apr 24 12:01:21.585043 (XEN) Notifying guest 0:80 (virq 1, port 0)
Apr 24 12:01:21.596921 (XEN) Notifying guest 0:81 (virq 1, port 0)
Apr 24 12:01:21.596982 (XEN) Notifying guest 0:82 (virq 1, port 0)
Apr 24 12:01:21.597028 (XEN) Notifying guest 0:83 (virq 1, port 0)
Apr 24 12:01:21.608929 (XEN) Notifying guest 0:84 (virq 1, port 0)
Apr 24 12:01:21.608990 (XEN) Notifying guest 0:85 (virq 1, port 0)
Apr 24 12:01:21.609035 (XEN) Notifying guest 0:86 (virq 1, port 0)
Apr 24 12:01:21.620913 (XEN) Notifying guest 0:87 (virq 1, port 0)
Apr 24 12:01:21.620975 (XEN) Notifying guest 0:88 (virq 1, port 0)
Apr 24 12:01:21.621021 (XEN) Notifying guest 0:89 (virq 1, port 0)
Apr 24 12:01:21.632933 (XEN) Notifying guest 0:90 (virq 1, port 0)
Apr 24 12:01:21.632993 (XEN) Notifying guest 0:91 (virq 1, port 0)
Apr 24 12:01:21.633038 (XEN) Notifying guest 0:92 (virq 1, port 0)
Apr 24 12:01:21.644940 (XEN) Notifying guest 0:93 (virq 1, port 0)
Apr 24 12:01:21.644999 (XEN) Notifying guest 0:94 (virq 1, port 0)
Apr 24 12:01:21.645044 (XEN) Notifying guest 0:95 (virq 1, port 0)
Apr 24 12:01:21.656866 Apr 24 12:01:28.156439 <client 0x1a615f0 connected - now 1 clients>
(XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input)
Apr 24 12:01:28.180888 Apr 24 12:01:28.182295 <client 0x1a615f0 disconnected - now 0 clients>