Apr 25 22:26:03.643287 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:03.643599 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:03.643644 (XEN) No periodic timer
Apr 25 22:26:03.652822 (XEN)   UNIT64 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:03.652882 (XEN)     VCPU64: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:03.664867 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:03.664925 (XEN) GICH_LRs (vcpu 64) mask=0
Apr 25 22:26:03.664970 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:03.665032 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:03.676852 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:03.676910 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:03.676954 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:03.676995 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:03.677058 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:03.677100 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:03.677140 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:03.688849 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:03.688904 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:03.688969 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:03.689012 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:03.689053 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:03.700845 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:03.700901 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:03.700967 (XEN) No periodic timer
Apr 25 22:26:03.701010 (XEN)   UNIT65 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:03.701055 (XEN)     VCPU65: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:03.712854 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:03.712912 (XEN) GICH_LRs (vcpu 65) mask=0
Apr 25 22:26:03.712979 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:03.724861 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:03.724916 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:03.724959 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:03.725000 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:03.725062 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:03.725104 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:03.740850 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:03.740881 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:03.740904 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:03.740938 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:03.740961 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:03.740983 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:03.741005 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:03.741027 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:03.756875 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:03.756931 (XEN) No periodic timer
Apr 25 22:26:03.756975 (XEN)   UNIT66 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:03.757022 (XEN)     VCPU66: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:03.768927 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:03.769006 (XEN) GICH_LRs (vcpu 66) mask=0
Apr 25 22:26:03.769053 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:03.769094 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:03.769134 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:03.780848 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:03.780925 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:03.780969 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:03.781011 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:03.781052 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:03.792848 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:03.792925 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:03.792969 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:03.793010 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:03.793050 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:03.793090 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:03.804849 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:03.804905 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:03.804949 (XEN) No periodic timer
Apr 25 22:26:03.804991 (XEN)   UNIT67 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:03.805038 (XEN)     VCPU67: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:03.816859 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:03.816918 (XEN) GICH_LRs (vcpu 67) mask=0
Apr 25 22:26:03.828886 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:03.828942 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:03.828986 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:03.829028 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:03.829091 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:03.829133 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:03.840834 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:03.840890 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:03.840934 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:03.840998 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:03.841061 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:03.841113 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:03.852847 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:03.852904 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:03.852970 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:03.853012 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:03.853054 (XEN) No periodic timer
Apr 25 22:26:03.853095 (XEN)   UNIT68 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:03.864854 (XEN)     VCPU68: CPU36 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:03.864940 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:03.876850 (XEN) GICH_LRs (vcpu 68) mask=0
Apr 25 22:26:03.876910 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:03.876954 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:03.876995 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:03.877059 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:03.877101 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:03.892908 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:03.892965 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:03.893008 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:03.893071 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:03.893114 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:03.893156 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:03.893196 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:03.908832 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:03.908911 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:03.908957 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:03.908999 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:03.909040 (XEN) No periodic timer
Apr 25 22:26:03.909081 (XEN)   UNIT69 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:03.920775 (XEN)     VCPU69: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:03.920824 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:03.920869 (XEN) GICH_LRs (vcpu 69) mask=0
Apr 25 22:26:03.932761 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:03.932793 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:03.932828 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:03.932851 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:03.932873 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:03.932896 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:03.944757 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:03.944800 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:03.944824 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:03.944846 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:03.944869 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:03.944891 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:03.956755 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:03.956785 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:03.956808 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:03.956831 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:03.956854 (XEN) No periodic timer
Apr 25 22:26:03.956889 (XEN)   UNIT70 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:03.968759 (XEN)     VCPU70: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:03.968795 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:03.980757 (XEN) GICH_LRs (vcpu 70) mask=0
Apr 25 22:26:03.980788 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:03.980824 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:03.980847 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:03.980869 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:03.992757 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:03.992788 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:03.992824 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:03.992847 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:03.992869 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:03.992892 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.004758 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.004801 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.004825 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.004848 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.004871 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.004893 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.016755 (XEN) No periodic timer
Apr 25 22:26:04.016798 (XEN)   UNIT71 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.016825 (XEN)     VCPU71: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.028761 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.028793 (XEN) GICH_LRs (vcpu 71) mask=0
Apr 25 22:26:04.028817 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.028853 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.040746 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.040777 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.040801 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.040835 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.040872 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.052752 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.052783 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.052808 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.052831 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.052865 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.052889 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.064753 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.064785 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.064809 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.064844 (XEN) No periodic timer
Apr 25 22:26:04.064867 (XEN)   UNIT72 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.076755 (XEN)     VCPU72: CPU9 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.076790 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.076816 (XEN) GICH_LRs (vcpu 72) mask=0
Apr 25 22:26:04.088783 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.088814 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.088837 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.088861 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.088883 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.088918 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.100790 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.100821 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.100845 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.100867 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.100902 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.100925 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.112906 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.112962 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.113006 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.113070 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.113113 (XEN) No periodic timer
Apr 25 22:26:04.124896 (XEN)   UNIT73 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.124959 (XEN)     VCPU73: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.125012 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.136913 (XEN) GICH_LRs (vcpu 73) mask=0
Apr 25 22:26:04.136972 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.137016 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.137058 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.137100 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.148913 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.148969 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.149013 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.149055 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.149096 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.149136 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.160889 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.160943 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.160967 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.161015 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.161056 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.172915 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.172970 (XEN) No periodic timer
Apr 25 22:26:04.173014 (XEN)   UNIT74 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.173061 (XEN)     VCPU74: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.184909 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.184968 (XEN) GICH_LRs (vcpu 74) mask=0
Apr 25 22:26:04.185013 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.196904 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.196960 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.197004 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.197046 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.197087 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.197128 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.208899 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.208956 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.208999 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.209041 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.209081 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.209121 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.220905 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.220960 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.220984 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.221030 (XEN) No periodic timer
Apr 25 22:26:04.221072 (XEN)   UNIT75 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.232917 (XEN)     VCPU75: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.232981 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.233027 (XEN) GICH_LRs (vcpu 75) mask=0
Apr 25 22:26:04.244906 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.244981 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.245027 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.245068 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.245110 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.245151 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.256916 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.256972 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.257014 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.257054 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.257094 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.268894 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.268951 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.268995 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.269036 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.269076 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.269116 (XEN) No periodic timer
Apr 25 22:26:04.280911 (XEN)   UNIT76 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.280981 (XEN)     VCPU76: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.281009 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.292898 (XEN) GICH_LRs (vcpu 76) mask=0
Apr 25 22:26:04.292955 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.292998 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.293039 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.304902 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.304958 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.305000 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.305041 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.305081 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.305121 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.316903 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.316958 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.317001 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.317042 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.317083 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.317122 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.328906 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.328961 (XEN) No periodic timer
Apr 25 22:26:04.329005 (XEN)   UNIT77 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.329051 (XEN)     VCPU77: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.340912 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.340971 (XEN) GICH_LRs (vcpu 77) mask=0
Apr 25 22:26:04.341012 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.352902 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.352958 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.353001 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.353042 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.353082 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.353122 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.364901 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.364957 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.365000 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.365041 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.365081 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.365121 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.376902 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.376959 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.377001 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.377042 (XEN) No periodic timer
Apr 25 22:26:04.377084 (XEN)   UNIT78 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.388903 (XEN)     VCPU78: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.388967 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.389012 (XEN) GICH_LRs (vcpu 78) mask=0
Apr 25 22:26:04.400912 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.400967 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.401019 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.401041 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.401063 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.412903 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.412959 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.413002 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.413043 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.413084 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.413123 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.424907 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.424963 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.425005 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.425046 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.425087 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.436906 (XEN) No periodic timer
Apr 25 22:26:04.436963 (XEN)   UNIT79 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.437011 (XEN)     VCPU79: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.448924 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.448983 (XEN) GICH_LRs (vcpu 79) mask=0
Apr 25 22:26:04.449028 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.449069 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.449109 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.460904 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.460959 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.461002 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.461047 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.461068 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.461090 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.472907 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.472963 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.473006 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.473046 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.473086 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.484910 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.484967 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.485010 (XEN) No periodic timer
Apr 25 22:26:04.485052 (XEN)   UNIT80 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.485098 (XEN)     VCPU80: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.496906 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.496964 (XEN) GICH_LRs (vcpu 80) mask=0
Apr 25 22:26:04.497008 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.508906 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.508961 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.509003 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.509044 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.509083 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.509123 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.520905 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.520960 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.521002 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.521056 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.521078 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.521100 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.532915 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.532970 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.533013 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.533054 (XEN) No periodic timer
Apr 25 22:26:04.533096 (XEN)   UNIT81 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.544897 (XEN)     VCPU81: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.544960 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.556904 (XEN) GICH_LRs (vcpu 81) mask=0
Apr 25 22:26:04.556961 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.557004 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.557044 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.557084 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.568900 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.568957 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.568999 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.569040 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.569080 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.569120 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.580898 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.580953 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.580996 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.581037 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.581085 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.581108 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.592912 (XEN) No periodic timer
Apr 25 22:26:04.592968 (XEN)   UNIT82 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.593016 (XEN)     VCPU82: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.604907 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.604965 (XEN) GICH_LRs (vcpu 82) mask=0
Apr 25 22:26:04.605010 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.605051 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.616897 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.616954 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.616996 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.617036 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.617076 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.617116 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.628910 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.628966 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.629008 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.629048 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.629088 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.629128 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.640898 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.640973 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.641019 (XEN) No periodic timer
Apr 25 22:26:04.641062 (XEN)   UNIT83 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.641113 (XEN)     VCPU83: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.652921 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.652979 (XEN) GICH_LRs (vcpu 83) mask=0
Apr 25 22:26:04.653024 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.664901 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.664956 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.664999 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.665040 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.665081 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.665121 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.676906 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.676962 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.677004 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.677044 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.677085 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.688905 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.688960 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.689003 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.689043 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.689084 (XEN) No periodic timer
Apr 25 22:26:04.700899 (XEN)   UNIT84 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.700962 (XEN)     VCPU84: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.701014 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.712902 (XEN) GICH_LRs (vcpu 84) mask=0
Apr 25 22:26:04.712959 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.713002 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.713043 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.713082 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.724913 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.724968 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.725010 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.725052 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.725092 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.725132 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.736916 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.736972 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.737014 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.737055 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.737095 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.737135 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.748896 (XEN) No periodic timer
Apr 25 22:26:04.748951 (XEN)   UNIT85 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.749000 (XEN)     VCPU85: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.760917 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.760975 (XEN) GICH_LRs (vcpu 85) mask=0
Apr 25 22:26:04.761020 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.761061 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.772915 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.772971 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.773013 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.773054 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.773094 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.773134 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.784902 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.784958 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.785002 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.785043 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.785083 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.785123 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.796897 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.796953 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.796995 (XEN) No periodic timer
Apr 25 22:26:04.797036 (XEN)   UNIT86 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.808903 (XEN)     VCPU86: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.808968 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.809013 (XEN) GICH_LRs (vcpu 86) mask=0
Apr 25 22:26:04.820905 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.820960 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.821003 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.821044 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.821084 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.821124 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.832908 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.832963 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.833005 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.833045 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.833104 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.833148 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.844904 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.844958 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.845001 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.845043 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.845084 (XEN) No periodic timer
Apr 25 22:26:04.856902 (XEN)   UNIT87 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.856964 (XEN)     VCPU87: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.857015 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.868909 (XEN) GICH_LRs (vcpu 87) mask=0
Apr 25 22:26:04.868967 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.869010 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.869051 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.869091 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.880903 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.880958 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.881001 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.881041 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.881081 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.881121 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.892915 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.892970 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.893012 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.893053 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.893093 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.893133 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.904908 (XEN) No periodic timer
Apr 25 22:26:04.904963 (XEN)   UNIT88 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.905012 (XEN)     VCPU88: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.916906 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.916964 (XEN) GICH_LRs (vcpu 88) mask=0
Apr 25 22:26:04.917009 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.917050 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.928892 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.928948 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.928990 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.929030 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.929070 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.940906 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.940962 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.941004 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.941044 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:04.941083 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:04.941124 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:04.952903 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:04.952959 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:04.953002 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:04.953043 (XEN) No periodic timer
Apr 25 22:26:04.953085 (XEN)   UNIT89 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:04.964904 (XEN)     VCPU89: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:04.964968 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:04.965013 (XEN) GICH_LRs (vcpu 89) mask=0
Apr 25 22:26:04.976908 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:04.976964 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:04.977006 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:04.977047 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:04.977086 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:04.988876 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:04.988932 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:04.988974 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:04.989015 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:04.989054 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:04.989094 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:05.000921 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:05.000979 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:05.001031 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:05.001075 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:05.001117 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:05.001164 (XEN) No periodic timer
Apr 25 22:26:05.012848 (XEN)   UNIT90 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:05.012910 (XEN)     VCPU90: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:05.012961 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:05.024921 (XEN) GICH_LRs (vcpu 90) mask=0
Apr 25 22:26:05.024979 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:05.025021 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:05.025062 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:05.025101 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:05.036877 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:05.036933 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:05.036994 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:05.037039 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:05.037079 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:05.037119 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:05.048895 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:05.048951 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:05.048993 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:05.049033 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:05.049074 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:05.060907 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:05.060962 (XEN) No periodic timer
Apr 25 22:26:05.061005 (XEN)   UNIT91 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:05.061052 (XEN)     VCPU91: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:05.072915 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:05.072974 (XEN) GICH_LRs (vcpu 91) mask=0
Apr 25 22:26:05.073018 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:05.084907 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:05.084963 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:05.085006 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:05.085046 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:05.085087 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:05.085126 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:05.096915 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:05.096971 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:05.097013 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:05.097054 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:05.097094 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:05.097135 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:05.108903 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:05.108958 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:05.109001 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:05.109042 (XEN) No periodic timer
Apr 25 22:26:05.109084 (XEN)   UNIT92 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:05.120902 (XEN)     VCPU92: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:05.120966 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:05.121012 (XEN) GICH_LRs (vcpu 92) mask=0
Apr 25 22:26:05.132917 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:05.132973 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:05.133016 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:05.133056 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:05.133097 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:05.144925 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:05.144981 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:05.145023 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:05.145063 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:05.145103 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:05.145143 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:05.156905 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:05.156960 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:05.157003 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:05.157043 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:05.157084 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:05.157124 (XEN) No periodic timer
Apr 25 22:26:05.168899 (XEN)   UNIT93 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:05.168960 (XEN)     VCPU93: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:05.180900 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:05.180961 (XEN) GICH_LRs (vcpu 93) mask=0
Apr 25 22:26:05.181006 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:05.181048 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:05.192901 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:05.192959 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:05.193002 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:05.193043 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:05.193084 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:05.193123 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:05.193163 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:05.204906 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:05.204961 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:05.205004 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:05.205045 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:05.205085 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:05.216911 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:05.216967 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:05.217011 (XEN) No periodic timer
Apr 25 22:26:05.217053 (XEN)   UNIT94 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:05.217099 (XEN)     VCPU94: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:05.228910 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:05.228969 (XEN) GICH_LRs (vcpu 94) mask=0
Apr 25 22:26:05.229014 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:05.240930 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:05.240986 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:05.241029 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:05.241069 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:05.241108 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:05.241148 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:05.252885 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:05.252941 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:05.252984 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:05.253024 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:05.253065 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:05.253105 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:05.264906 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:05.264962 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:05.265004 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:05.265045 (XEN) No periodic timer
Apr 25 22:26:05.265086 (XEN)   UNIT95 affinities: hard={0-95} soft={0-95}
Apr 25 22:26:05.276921 (XEN)     VCPU95: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 25 22:26:05.276985 (XEN)     pause_count=0 pause_flags=1
Apr 25 22:26:05.288903 (XEN) GICH_LRs (vcpu 95) mask=0
Apr 25 22:26:05.288962 (XEN)    VCPU_LR[0]=0
Apr 25 22:26:05.289005 (XEN)    VCPU_LR[1]=0
Apr 25 22:26:05.289046 (XEN)    VCPU_LR[2]=0
Apr 25 22:26:05.289085 (XEN)    VCPU_LR[3]=0
Apr 25 22:26:05.289125 (XEN)    VCPU_LR[4]=0
Apr 25 22:26:05.300905 (XEN)    VCPU_LR[5]=0
Apr 25 22:26:05.300960 (XEN)    VCPU_LR[6]=0
Apr 25 22:26:05.301003 (XEN)    VCPU_LR[7]=0
Apr 25 22:26:05.301043 (XEN)    VCPU_LR[8]=0
Apr 25 22:26:05.301083 (XEN)    VCPU_LR[9]=0
Apr 25 22:26:05.301122 (XEN)    VCPU_LR[10]=0
Apr 25 22:26:05.312856 (XEN)    VCPU_LR[11]=0
Apr 25 22:26:05.312911 (XEN)    VCPU_LR[12]=0
Apr 25 22:26:05.312954 (XEN)    VCPU_LR[13]=0
Apr 25 22:26:05.312994 (XEN)    VCPU_LR[14]=0
Apr 25 22:26:05.313034 (XEN)    VCPU_LR[15]=0
Apr 25 22:26:05.324906 (XEN) No periodic timer
Apr 25 22:26:05.324963 (XEN) Notifying guest 0:0 (virq 1, port 0)
Apr 25 22:26:05.325009 (XEN) Notifying guest 0:1 (virq 1, port 0)
Apr 25 22:26:05.325053 (XEN) Notifying guest 0:2 (virq 1, port 0)
Apr 25 22:26:05.336912 (XEN) Notifying guest 0:3 (virq 1, port 0)
Apr 25 22:26:05.336971 (XEN) Notifying guest 0:4 (virq 1, port 0)
Apr 25 22:26:05.337016 (XEN) Notifying guest 0:5 (virq 1, port 0)
Apr 25 22:26:05.348883 (XEN) Notifying guest 0:6 (virq 1, port 0)
Apr 25 22:26:05.348942 (XEN) Notifying guest 0:7 (virq 1, port 0)
Apr 25 22:26:05.348988 (XEN) Notifying guest 0:8 (virq 1, port 0)
Apr 25 22:26:05.360903 (XEN) Notifying guest 0:9 (virq 1, port 0)
Apr 25 22:26:05.360962 (XEN) Notifying guest 0:10 (virq 1, port 0)
Apr 25 22:26:05.361008 (XEN) Notifying guest 0:11 (virq 1, port 0)
Apr 25 22:26:05.372907 (XEN) Notifying guest 0:12 (virq 1, port 0)
Apr 25 22:26:05.372966 (XEN) Notifying guest 0:13 (virq 1, port 0)
Apr 25 22:26:05.373011 (XEN) Notifying guest 0:14 (virq 1, port 0)
Apr 25 22:26:05.384906 (XEN) Notifying guest 0:15 (virq 1, port 0)
Apr 25 22:26:05.385042 (XEN) Notifying guest 0:16 (virq 1, port 0)
Apr 25 22:26:05.385070 (XEN) Notifying guest 0:17 (virq 1, port 0)
Apr 25 22:26:05.396899 (XEN) Notifying guest 0:18 (virq 1, port 0)
Apr 25 22:26:05.396959 (XEN) Notifying guest 0:19 (virq 1, port 0)
Apr 25 22:26:05.397005 (XEN) Notifying guest 0:20 (virq 1, port 0)
Apr 25 22:26:05.408911 (XEN) Notifying guest 0:21 (virq 1, port 0)
Apr 25 22:26:05.408970 (XEN) Notifying guest 0:22 (virq 1, port 0)
Apr 25 22:26:05.409016 (XEN) Notifying guest 0:23 (virq 1, port 0)
Apr 25 22:26:05.420904 (XEN) Notifying guest 0:24 (virq 1, port 0)
Apr 25 22:26:05.420964 (XEN) Notifying guest 0:25 (virq 1, port 0)
Apr 25 22:26:05.421010 (XEN) Notifying guest 0:26 (virq 1, port 0)
Apr 25 22:26:05.432897 (XEN) Notifying guest 0:27 (virq 1, port 0)
Apr 25 22:26:05.432958 (XEN) Notifying guest 0:28 (virq 1, port 0)
Apr 25 22:26:05.433004 (XEN) Notifying guest 0:29 (virq 1, port 0)
Apr 25 22:26:05.444910 (XEN) Notifying guest 0:30 (virq 1, port 0)
Apr 25 22:26:05.444969 (XEN) Notifying guest 0:31 (virq 1, port 0)
Apr 25 22:26:05.445015 (XEN) Notifying guest 0:32 (virq 1, port 0)
Apr 25 22:26:05.456906 (XEN) Notifying guest 0:33 (virq 1, port 0)
Apr 25 22:26:05.456992 (XEN) Notifying guest 0:34 (virq 1, port 0)
Apr 25 22:26:05.457042 (XEN) Notifying guest 0:35 (virq 1, port 0)
Apr 25 22:26:05.468868 (XEN) Notifying guest 0:36 (virq 1, port 0)
Apr 25 22:26:05.468928 (XEN) Notifying guest 0:37 (virq 1, port 0)
Apr 25 22:26:05.468974 (XEN) Notifying guest 0:38 (virq 1, port 0)
Apr 25 22:26:05.480902 (XEN) Notifying guest 0:39 (virq 1, port 0)
Apr 25 22:26:05.480962 (XEN) Notifying guest 0:40 (virq 1, port 0)
Apr 25 22:26:05.481008 (XEN) Notifying guest 0:41 (virq 1, port 0)
Apr 25 22:26:05.492910 (XEN) Notifying guest 0:42 (virq 1, port 0)
Apr 25 22:26:05.492970 (XEN) Notifying guest 0:43 (virq 1, port 0)
Apr 25 22:26:05.493017 (XEN) Notifying guest 0:44 (virq 1, port 0)
Apr 25 22:26:05.504917 (XEN) Notifying guest 0:45 (virq 1, port 0)
Apr 25 22:26:05.504977 (XEN) Notifying guest 0:46 (virq 1, port 0)
Apr 25 22:26:05.505023 (XEN) Notifying guest 0:47 (virq 1, port 0)
Apr 25 22:26:05.505066 (XEN) Notifying guest 0:48 (virq 1, port 0)
Apr 25 22:26:05.516908 (XEN) Notifying guest 0:49 (virq 1, port 0)
Apr 25 22:26:05.516966 (XEN) Notifying guest 0:50 (virq 1, port 0)
Apr 25 22:26:05.517012 (XEN) Notifying guest 0:51 (virq 1, port 0)
Apr 25 22:26:05.528919 (XEN) Notifying guest 0:52 (virq 1, port 0)
Apr 25 22:26:05.528977 (XEN) Notifying guest 0:53 (virq 1, port 0)
Apr 25 22:26:05.529023 (XEN) Notifying guest 0:54 (virq 1, port 0)
Apr 25 22:26:05.540911 (XEN) Notifying guest 0:55 (virq 1, port 0)
Apr 25 22:26:05.540970 (XEN) Notifying guest 0:56 (virq 1, port 0)
Apr 25 22:26:05.541016 (XEN) Notifying guest 0:57 (virq 1, port 0)
Apr 25 22:26:05.552912 (XEN) Notifying guest 0:58 (virq 1, port 0)
Apr 25 22:26:05.552971 (XEN) Notifying guest 0:59 (virq 1, port 0)
Apr 25 22:26:05.553016 (XEN) Notifying guest 0:60 (virq 1, port 0)
Apr 25 22:26:05.564901 (XEN) Notifying guest 0:61 (virq 1, port 0)
Apr 25 22:26:05.564960 (XEN) Notifying guest 0:62 (virq 1, port 0)
Apr 25 22:26:05.576905 (XEN) Notifying guest 0:63 (virq 1, port 0)
Apr 25 22:26:05.576965 (XEN) Notifying guest 0:64 (virq 1, port 0)
Apr 25 22:26:05.577011 (XEN) Notifying guest 0:65 (virq 1, port 0)
Apr 25 22:26:05.577055 (XEN) Notifying guest 0:66 (virq 1, port 0)
Apr 25 22:26:05.588910 (XEN) Notifying guest 0:67 (virq 1, port 0)
Apr 25 22:26:05.588968 (XEN) Notifying guest 0:68 (virq 1, port 0)
Apr 25 22:26:05.589014 (XEN) Notifying guest 0:69 (virq 1, port 0)
Apr 25 22:26:05.600922 (XEN) Notifying guest 0:70 (virq 1, port 0)
Apr 25 22:26:05.600981 (XEN) Notifying guest 0:71 (virq 1, port 0)
Apr 25 22:26:05.601025 (XEN) Notifying guest 0:72 (virq 1, port 0)
Apr 25 22:26:05.612911 (XEN) Notifying guest 0:73 (virq 1, port 0)
Apr 25 22:26:05.612970 (XEN) Notifying guest 0:74 (virq 1, port 0)
Apr 25 22:26:05.613015 (XEN) Notifying guest 0:75 (virq 1, port 0)
Apr 25 22:26:05.624859 (XEN) Notifying guest 0:76 (virq 1, port 0)
Apr 25 22:26:05.624918 (XEN) Notifying guest 0:77 (virq 1, port 0)
Apr 25 22:26:05.624964 (XEN) Notifying guest 0:78 (virq 1, port 0)
Apr 25 22:26:05.636919 (XEN) Notifying guest 0:79 (virq 1, port 0)
Apr 25 22:26:05.636978 (XEN) Notifying guest 0:80 (virq 1, port 0)
Apr 25 22:26:05.637024 (XEN) Notifying guest 0:81 (virq 1, port 0)
Apr 25 22:26:05.648908 (XEN) Notifying guest 0:82 (virq 1, port 0)
Apr 25 22:26:05.648967 (XEN) Notifying guest 0:83 (virq 1, port 0)
Apr 25 22:26:05.649013 (XEN) Notifying guest 0:84 (virq 1, port 0)
Apr 25 22:26:05.660903 (XEN) Notifying guest 0:85 (virq 1, port 0)
Apr 25 22:26:05.660962 (XEN) Notifying guest 0:86 (virq 1, port 0)
Apr 25 22:26:05.661008 (XEN) Notifying guest 0:87 (virq 1, port 0)
Apr 25 22:26:05.672888 (XEN) Notifying guest 0:88 (virq 1, port 0)
Apr 25 22:26:05.672947 (XEN) Notifying guest 0:89 (virq 1, port 0)
Apr 25 22:26:05.672993 (XEN) Notifying guest 0:90 (virq 1, port 0)
Apr 25 22:26:05.684895 (XEN) Notifying guest 0:91 (virq 1, port 0)
Apr 25 22:26:05.684954 (XEN) Notifying guest 0:92 (virq 1, port 0)
Apr 25 22:26:05.685000 (XEN) Notifying guest 0:93 (virq 1, port 0)
Apr 25 22:26:05.696933 (XEN) Notifying guest 0:94 (virq 1, port 0)
Apr 25 22:26:05.696994 (XEN) Notifying guest 0:95 (virq 1, port 0)
Apr 25 22:26:05.697039 Apr 25 22:26:12.207877 <client 0x1a615f0 connected - now 1 clients>
(XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input)
Apr 25 22:26:12.228859 Apr 25 22:26:12.230230 <client 0x1a615f0 disconnected - now 0 clients>