Apr 26 15:13:05.271080 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.271387 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.280665 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.280665 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.280665 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.280665 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.280665 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.280665 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.292722 (XEN) No periodic timer
Apr 26 15:13:05.292722 (XEN)   UNIT13 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.292722 (XEN)     VCPU13: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.304664 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.304664 (XEN) GICH_LRs (vcpu 13) mask=0
Apr 26 15:13:05.304664 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.304664 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.316662 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.316662 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.316662 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.316662 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.316662 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.316662 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.328677 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.328677 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.328677 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.328677 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.328677 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.328677 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.340661 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.340661 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.340661 (XEN) No periodic timer
Apr 26 15:13:05.340661 (XEN)   UNIT14 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.340661 (XEN)     VCPU14: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.352662 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.352662 (XEN) GICH_LRs (vcpu 14) mask=0
Apr 26 15:13:05.364661 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.364661 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.364661 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.364661 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.364661 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.364661 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.376657 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.376657 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.376657 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.376657 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.376657 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.376657 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.388661 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.388661 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.388661 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.388661 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.388661 (XEN) No periodic timer
Apr 26 15:13:05.400661 (XEN)   UNIT15 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.400661 (XEN)     VCPU15: CPU7 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.400661 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.412661 (XEN) GICH_LRs (vcpu 15) mask=0
Apr 26 15:13:05.412661 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.412661 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.412661 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.412661 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.424663 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.424663 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.424663 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.424663 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.424663 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.424663 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.436660 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.436660 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.436660 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.436660 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.436660 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.436660 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.448671 (XEN) No periodic timer
Apr 26 15:13:05.448671 (XEN)   UNIT16 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.448671 (XEN)     VCPU16: CPU73 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.460662 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.460662 (XEN) GICH_LRs (vcpu 16) mask=0
Apr 26 15:13:05.460662 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.460662 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.472662 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.472662 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.472662 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.472662 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.472662 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.472662 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.484661 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.484661 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.484661 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.484661 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.484661 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.484661 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.496662 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.496662 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.496662 (XEN) No periodic timer
Apr 26 15:13:05.496662 (XEN)   UNIT17 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.496662 (XEN)     VCPU17: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.508652 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.508652 (XEN) GICH_LRs (vcpu 17) mask=0
Apr 26 15:13:05.520773 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.520773 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.520773 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.520773 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.520773 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.532921 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.532985 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.533027 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.533067 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.533108 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.533171 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.544906 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.544963 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.545028 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.545069 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.545109 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.545149 (XEN) No periodic timer
Apr 26 15:13:05.556909 (XEN)   UNIT18 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.556992 (XEN)     VCPU18: CPU6 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.557044 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.568918 (XEN) GICH_LRs (vcpu 18) mask=0
Apr 26 15:13:05.568976 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.569019 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.569082 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.569123 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.580915 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.580971 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.581012 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.581074 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.581115 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.581155 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.592855 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.592911 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.592975 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.593017 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.593058 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.593098 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.604916 (XEN) No periodic timer
Apr 26 15:13:05.604993 (XEN)   UNIT19 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.605043 (XEN)     VCPU19: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.616910 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.616968 (XEN) GICH_LRs (vcpu 19) mask=0
Apr 26 15:13:05.617012 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.617077 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.628893 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.628949 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.628990 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.629031 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.629094 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.629135 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.640909 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.640964 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.641006 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.641068 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.641110 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.652924 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.652980 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.653022 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.653084 (XEN) No periodic timer
Apr 26 15:13:05.653126 (XEN)   UNIT20 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.664907 (XEN)     VCPU20: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.664971 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.665016 (XEN) GICH_LRs (vcpu 20) mask=0
Apr 26 15:13:05.676925 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.676982 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.677023 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.677064 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.677103 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.688916 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.688973 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.689015 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.689055 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.689095 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.689157 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.700918 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.700974 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.701016 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.701056 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.701119 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.701161 (XEN) No periodic timer
Apr 26 15:13:05.712910 (XEN)   UNIT21 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.712971 (XEN)     VCPU21: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.713022 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.724914 (XEN) GICH_LRs (vcpu 21) mask=0
Apr 26 15:13:05.724971 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.725013 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.725053 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.736908 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.736965 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.737029 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.737071 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.737111 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.737151 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.737191 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.748912 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.748968 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.749010 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.749050 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.749090 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.760840 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.760896 (XEN) No periodic timer
Apr 26 15:13:05.760938 (XEN)   UNIT22 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.760985 (XEN)     VCPU22: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.772918 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.772976 (XEN) GICH_LRs (vcpu 22) mask=0
Apr 26 15:13:05.773021 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.784917 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.784973 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.785015 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.785057 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.785098 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.785140 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.796911 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.796967 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.797009 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.797050 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.797091 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.797131 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.808917 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.808974 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.809016 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.809057 (XEN) No periodic timer
Apr 26 15:13:05.809098 (XEN)   UNIT23 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.820933 (XEN)     VCPU23: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.820997 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.832908 (XEN) GICH_LRs (vcpu 23) mask=0
Apr 26 15:13:05.832969 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.833011 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.833052 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.833092 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.833132 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.844896 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.844952 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.844995 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.845036 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.845077 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.845117 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.856832 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.856863 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.856886 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.856909 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.856931 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.856953 (XEN) No periodic timer
Apr 26 15:13:05.868884 (XEN)   UNIT24 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.868962 (XEN)     VCPU24: CPU7 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.880877 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.880937 (XEN) GICH_LRs (vcpu 24) mask=0
Apr 26 15:13:05.880981 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.881022 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.881063 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.892865 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.892921 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.892963 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.893004 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.893044 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.904911 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.904968 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.905011 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.905052 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.905092 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.905132 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.916916 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.916972 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.917015 (XEN) No periodic timer
Apr 26 15:13:05.917057 (XEN)   UNIT25 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.917104 (XEN)     VCPU25: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.928921 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.928980 (XEN) GICH_LRs (vcpu 25) mask=0
Apr 26 15:13:05.929024 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.940798 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.940829 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.940851 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.940873 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:05.940895 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:05.940917 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:05.952850 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:05.952905 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:05.952947 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:05.952988 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:05.953028 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:05.953068 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:05.964855 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:05.964911 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:05.964953 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:05.964994 (XEN) No periodic timer
Apr 26 15:13:05.965035 (XEN)   UNIT26 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:05.976857 (XEN)     VCPU26: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:05.976921 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:05.988852 (XEN) GICH_LRs (vcpu 26) mask=0
Apr 26 15:13:05.988911 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:05.988953 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:05.988994 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:05.989034 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:05.989074 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.000853 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.000909 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.000951 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.000991 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.001030 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.001071 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.012858 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.012914 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.012956 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.012997 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.013037 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.024847 (XEN) No periodic timer
Apr 26 15:13:06.024903 (XEN)   UNIT27 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.024951 (XEN)     VCPU27: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.036865 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.036923 (XEN) GICH_LRs (vcpu 27) mask=0
Apr 26 15:13:06.036967 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.037007 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.048851 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.048907 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.048949 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.048990 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.049029 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.049069 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.060861 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.060917 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.060959 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.061000 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.061041 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.061099 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.072857 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.072913 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.072955 (XEN) No periodic timer
Apr 26 15:13:06.072996 (XEN)   UNIT28 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.073042 (XEN)     VCPU28: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.084870 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.084928 (XEN) GICH_LRs (vcpu 28) mask=0
Apr 26 15:13:06.096861 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.096917 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.096959 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.096999 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.097039 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.097079 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.108857 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.108915 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.108956 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.108997 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.109038 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.109078 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.120908 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.120965 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.121007 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.121047 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.121087 (XEN) No periodic timer
Apr 26 15:13:06.121128 (XEN)   UNIT29 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.132918 (XEN)     VCPU29: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.132982 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.144885 (XEN) GICH_LRs (vcpu 29) mask=0
Apr 26 15:13:06.144943 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.144985 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.145026 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.145065 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.156921 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.156976 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.157018 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.157058 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.157097 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.157137 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.168987 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.169042 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.169084 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.169125 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.169166 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.169206 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.180929 (XEN) No periodic timer
Apr 26 15:13:06.180985 (XEN)   UNIT30 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.181033 (XEN)     VCPU30: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.192924 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.192983 (XEN) GICH_LRs (vcpu 30) mask=0
Apr 26 15:13:06.193027 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.193069 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.204918 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.204974 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.205015 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.205055 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.205094 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.205134 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.216919 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.216976 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.217018 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.217058 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.217098 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.217138 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.228921 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.228977 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.229019 (XEN) No periodic timer
Apr 26 15:13:06.229060 (XEN)   UNIT31 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.240920 (XEN)     VCPU31: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.240986 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.241031 (XEN) GICH_LRs (vcpu 31) mask=0
Apr 26 15:13:06.252920 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.252977 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.253019 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.253059 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.253099 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.253138 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.264906 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.264962 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.265004 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.265062 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.265106 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.265146 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.276812 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.276843 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.276866 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.276888 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.276910 (XEN) No periodic timer
Apr 26 15:13:06.288922 (XEN)   UNIT32 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.288983 (XEN)     VCPU32: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.289033 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.300925 (XEN) GICH_LRs (vcpu 32) mask=0
Apr 26 15:13:06.300983 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.301025 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.301065 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.301105 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.312913 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.312969 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.313010 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.313051 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.313091 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.313131 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.324915 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.324970 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.325011 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.325052 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.325091 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.336901 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.336959 (XEN) No periodic timer
Apr 26 15:13:06.337002 (XEN)   UNIT33 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.337048 (XEN)     VCPU33: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.348913 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.348971 (XEN) GICH_LRs (vcpu 33) mask=0
Apr 26 15:13:06.349015 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.349056 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.360923 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.360979 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.361020 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.361061 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.361100 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.361140 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.372883 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.372939 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.372980 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.373020 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.373060 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.373100 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.384912 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.384968 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.385009 (XEN) No periodic timer
Apr 26 15:13:06.385051 (XEN)   UNIT34 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.396894 (XEN)     VCPU34: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.396959 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.397004 (XEN) GICH_LRs (vcpu 34) mask=0
Apr 26 15:13:06.408916 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.408971 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.409012 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.409052 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.409092 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.420922 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.420978 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.421019 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.421060 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.421099 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.421139 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.432916 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.432972 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.433014 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.433055 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.433095 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.433135 (XEN) No periodic timer
Apr 26 15:13:06.444914 (XEN)   UNIT35 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.444975 (XEN)     VCPU35: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.445025 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.456836 (XEN) GICH_LRs (vcpu 35) mask=0
Apr 26 15:13:06.456868 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.456890 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.456912 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.468912 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.468986 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.469031 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.469072 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.469111 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.469150 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.480823 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.480854 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.480877 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.480899 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.480921 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.480942 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.492824 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.492855 (XEN) No periodic timer
Apr 26 15:13:06.492878 (XEN)   UNIT36 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.492903 (XEN)     VCPU36: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.504919 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.504977 (XEN) GICH_LRs (vcpu 36) mask=0
Apr 26 15:13:06.505021 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.505062 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.516854 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.516909 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.516951 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.516991 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.517030 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.517070 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.528911 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.528966 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.529007 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.529047 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.529086 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.540912 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.540967 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.541009 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.541049 (XEN) No periodic timer
Apr 26 15:13:06.541090 (XEN)   UNIT37 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.552931 (XEN)     VCPU37: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.552995 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.564903 (XEN) GICH_LRs (vcpu 37) mask=0
Apr 26 15:13:06.564963 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.565005 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.565046 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.565086 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.565126 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.576762 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.576793 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.576815 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.576837 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.576859 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.576881 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.588855 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.588911 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.588952 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.588993 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.589033 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.589072 (XEN) No periodic timer
Apr 26 15:13:06.600854 (XEN)   UNIT38 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.600914 (XEN)     VCPU38: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.612861 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.612920 (XEN) GICH_LRs (vcpu 38) mask=0
Apr 26 15:13:06.612965 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.613006 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.613045 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.624857 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.624913 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.624955 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.624995 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.625035 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.625075 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.636852 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.636907 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.636949 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.636989 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.637029 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.637069 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.648852 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.648908 (XEN) No periodic timer
Apr 26 15:13:06.648950 (XEN)   UNIT39 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.648997 (XEN)     VCPU39: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.660865 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.660922 (XEN) GICH_LRs (vcpu 39) mask=0
Apr 26 15:13:06.660985 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.672854 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.672908 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.672949 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.672989 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.673029 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.673068 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.684852 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.684907 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.684949 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.684989 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.685029 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.685068 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.696858 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.696914 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.696955 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.696995 (XEN) No periodic timer
Apr 26 15:13:06.697036 (XEN)   UNIT40 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.708858 (XEN)     VCPU40: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.708923 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.720850 (XEN) GICH_LRs (vcpu 40) mask=0
Apr 26 15:13:06.720908 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.720950 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.720990 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.721030 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.721069 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.732912 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.732967 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.733009 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.733049 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.733088 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.733128 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.744909 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.744964 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.745007 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.745047 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.745087 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.745126 (XEN) No periodic timer
Apr 26 15:13:06.756916 (XEN)   UNIT41 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.756977 (XEN)     VCPU41: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.768901 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.768960 (XEN) GICH_LRs (vcpu 41) mask=0
Apr 26 15:13:06.769004 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.769045 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.769085 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.780899 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.780954 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.780995 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.781037 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.781077 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.792912 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.792968 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.793011 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.793052 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.793092 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.793132 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.804915 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.804971 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.805012 (XEN) No periodic timer
Apr 26 15:13:06.805055 (XEN)   UNIT42 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.805101 (XEN)     VCPU42: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.816925 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.816984 (XEN) GICH_LRs (vcpu 42) mask=0
Apr 26 15:13:06.828914 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.828970 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.829012 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.829052 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.829094 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.829133 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.840816 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.840847 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.840870 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.840891 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.840913 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.840935 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.852833 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.852864 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.852887 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.852908 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.852930 (XEN) No periodic timer
Apr 26 15:13:06.852952 (XEN)   UNIT43 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.864847 (XEN)     VCPU43: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.864883 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.876829 (XEN) GICH_LRs (vcpu 43) mask=0
Apr 26 15:13:06.876860 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.876883 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.876905 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.876927 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.876949 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.888886 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.888886 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.888886 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.888886 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.888886 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.888886 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.900933 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.900992 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.901034 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.901074 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.901113 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.912910 (XEN) No periodic timer
Apr 26 15:13:06.912967 (XEN)   UNIT44 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.913015 (XEN)     VCPU44: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.924926 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.924984 (XEN) GICH_LRs (vcpu 44) mask=0
Apr 26 15:13:06.925028 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.925069 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.936922 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.936978 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.937020 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.937060 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.937101 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.937141 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.948929 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.948985 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.949026 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.949067 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:06.949107 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:06.949146 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:06.960923 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:06.960978 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:06.961020 (XEN) No periodic timer
Apr 26 15:13:06.961061 (XEN)   UNIT45 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:06.972916 (XEN)     VCPU45: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:06.972981 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:06.973026 (XEN) GICH_LRs (vcpu 45) mask=0
Apr 26 15:13:06.984917 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:06.984973 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:06.985015 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:06.985055 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:06.985095 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:06.985134 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:06.996918 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:06.996974 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:06.997016 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:06.997056 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:06.997096 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:06.997135 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.008925 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.008981 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.009023 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.009063 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.009102 (XEN) No periodic timer
Apr 26 15:13:07.009142 (XEN)   UNIT46 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.020918 (XEN)     VCPU46: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.020982 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.032923 (XEN) GICH_LRs (vcpu 46) mask=0
Apr 26 15:13:07.032981 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.033023 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.033063 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.033103 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.044919 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.044974 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.045016 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.045056 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.045096 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.045136 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.056914 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.056970 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.057012 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.057052 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.057110 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.068805 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.068805 (XEN) No periodic timer
Apr 26 15:13:07.068805 (XEN)   UNIT47 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.068805 (XEN)     VCPU47: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.080910 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.080973 (XEN) GICH_LRs (vcpu 47) mask=0
Apr 26 15:13:07.081017 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.081058 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.092885 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.092940 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.092981 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.093021 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.093060 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.093100 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.104911 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.104966 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.105008 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.105048 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.105088 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.105128 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.116920 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.116975 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.117016 (XEN) No periodic timer
Apr 26 15:13:07.117058 (XEN)   UNIT48 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.128913 (XEN)     VCPU48: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.128978 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.129022 (XEN) GICH_LRs (vcpu 48) mask=0
Apr 26 15:13:07.140912 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.140967 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.141009 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.141049 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.141088 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.141128 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.152917 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.152973 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.153014 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.153053 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.153093 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.153132 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.164901 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.164957 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.164999 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.165039 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.165079 (XEN) No periodic timer
Apr 26 15:13:07.176912 (XEN)   UNIT49 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.176974 (XEN)     VCPU49: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.188914 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.188974 (XEN) GICH_LRs (vcpu 49) mask=0
Apr 26 15:13:07.189019 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.189059 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.189099 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.200912 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.200968 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.201009 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.201050 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.201089 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.201129 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.212910 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.212967 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.213009 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.213049 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.213090 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.213129 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.224914 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.224970 (XEN) No periodic timer
Apr 26 15:13:07.225013 (XEN)   UNIT50 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.225059 (XEN)     VCPU50: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.236916 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.236974 (XEN) GICH_LRs (vcpu 50) mask=0
Apr 26 15:13:07.237018 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.237059 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.248924 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.248980 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.249021 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.249062 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.249102 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.249141 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.260922 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.260997 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.261042 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.261082 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.261122 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.272903 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.272961 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.273003 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.273044 (XEN) No periodic timer
Apr 26 15:13:07.273085 (XEN)   UNIT51 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.284916 (XEN)     VCPU51: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.284980 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.296914 (XEN) GICH_LRs (vcpu 51) mask=0
Apr 26 15:13:07.296973 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.297015 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.297055 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.297095 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.297135 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.308916 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.308972 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.309014 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.309054 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.309093 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.309133 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.320914 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.320969 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.321011 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.321051 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.321091 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.321131 (XEN) No periodic timer
Apr 26 15:13:07.332914 (XEN)   UNIT52 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.332976 (XEN)     VCPU52: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.344902 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.344961 (XEN) GICH_LRs (vcpu 52) mask=0
Apr 26 15:13:07.345005 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.345046 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.345086 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.356913 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.356969 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.357010 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.357051 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.357091 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.357131 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.368922 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.368978 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.369019 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.369060 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.369100 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.369140 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.380906 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.380963 (XEN) No periodic timer
Apr 26 15:13:07.381005 (XEN)   UNIT53 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.381051 (XEN)     VCPU53: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.392899 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.392958 (XEN) GICH_LRs (vcpu 53) mask=0
Apr 26 15:13:07.393002 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.404909 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.404965 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.405008 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.405048 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.405088 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.405128 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.416783 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.416814 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.416837 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.416859 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.416881 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.428755 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.428780 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.428802 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.428824 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.428846 (XEN) No periodic timer
Apr 26 15:13:07.428868 (XEN)   UNIT54 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.440743 (XEN)     VCPU54: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.440773 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.452778 (XEN) GICH_LRs (vcpu 54) mask=0
Apr 26 15:13:07.452821 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.452846 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.452869 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.452891 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.452913 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.464878 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.464935 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.464976 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.465016 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.465055 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.465095 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.476854 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.476909 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.476949 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.476989 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.477029 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.488857 (XEN) No periodic timer
Apr 26 15:13:07.488915 (XEN)   UNIT55 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.488962 (XEN)     VCPU55: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.500861 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.500919 (XEN) GICH_LRs (vcpu 55) mask=0
Apr 26 15:13:07.500963 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.501004 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.501044 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.512844 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.512899 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.512941 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.512981 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.513021 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.513061 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.524857 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.524912 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.524953 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.524994 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.525034 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.525074 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.536869 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.536925 (XEN) No periodic timer
Apr 26 15:13:07.536967 (XEN)   UNIT56 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.537013 (XEN)     VCPU56: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.548933 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.548990 (XEN) GICH_LRs (vcpu 56) mask=0
Apr 26 15:13:07.560915 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.560971 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.561012 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.561053 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.561093 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.561132 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.572784 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.572815 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.572840 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.572863 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.572885 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.572906 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.584810 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.584859 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.584900 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.584940 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.584980 (XEN) No periodic timer
Apr 26 15:13:07.585020 (XEN)   UNIT57 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.596738 (XEN)     VCPU57: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.596768 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.608744 (XEN) GICH_LRs (vcpu 57) mask=0
Apr 26 15:13:07.608771 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.608794 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.608816 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.608838 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.620748 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.620775 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.620797 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.620819 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.620840 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.620862 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.632766 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.632797 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.632820 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.632843 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.632865 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.632887 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.644775 (XEN) No periodic timer
Apr 26 15:13:07.644806 (XEN)   UNIT58 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.644832 (XEN)     VCPU58: CPU67 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.656770 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.656801 (XEN) GICH_LRs (vcpu 58) mask=0
Apr 26 15:13:07.656839 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.656864 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.656886 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.668776 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.668806 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.668829 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.668851 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.668873 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.680768 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.680798 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.680821 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.680843 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.680865 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.680887 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.692863 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.692918 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.692961 (XEN) No periodic timer
Apr 26 15:13:07.693002 (XEN)   UNIT59 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.704854 (XEN)     VCPU59: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.704918 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.704964 (XEN) GICH_LRs (vcpu 59) mask=0
Apr 26 15:13:07.716855 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.716911 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.716953 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.716993 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.717033 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.717073 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.728863 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.728920 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.728961 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.729002 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.729042 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.729082 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.740857 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.740912 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.740954 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.740996 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.741036 (XEN) No periodic timer
Apr 26 15:13:07.741076 (XEN)   UNIT60 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.752920 (XEN)     VCPU60: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.752983 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.764918 (XEN) GICH_LRs (vcpu 60) mask=0
Apr 26 15:13:07.764976 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.765017 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.765058 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.765098 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.776910 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.776966 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.777008 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.777050 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.777090 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.777129 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.788915 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.788972 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.789014 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.789054 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.789094 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.789135 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.800906 (XEN) No periodic timer
Apr 26 15:13:07.800962 (XEN)   UNIT61 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.801010 (XEN)     VCPU61: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.812916 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.812974 (XEN) GICH_LRs (vcpu 61) mask=0
Apr 26 15:13:07.813018 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.813058 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.824914 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.824969 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.825011 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.825052 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.825092 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.825132 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.836915 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.836971 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.837012 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.837052 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.837092 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.837132 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.848921 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.848977 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.849018 (XEN) No periodic timer
Apr 26 15:13:07.849059 (XEN)   UNIT62 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.860933 (XEN)     VCPU62: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.860999 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.861043 (XEN) GICH_LRs (vcpu 62) mask=0
Apr 26 15:13:07.872925 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.872981 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.873023 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.873063 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.873103 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.873143 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.884915 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.884972 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.885014 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.885054 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.885094 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.885134 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.896929 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.896985 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.897027 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.897067 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.897108 (XEN) No periodic timer
Apr 26 15:13:07.897149 (XEN)   UNIT63 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.908920 (XEN)     VCPU63: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.908984 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.920918 (XEN) GICH_LRs (vcpu 63) mask=0
Apr 26 15:13:07.920976 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.921019 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.921060 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.932921 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.932978 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.933021 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.933062 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.933102 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.933143 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.944912 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.944969 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.945011 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.945052 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:07.945092 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:07.945132 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:07.956921 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:07.956977 (XEN) No periodic timer
Apr 26 15:13:07.957020 (XEN)   UNIT64 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:07.957066 (XEN)     VCPU64: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:07.968931 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:07.968989 (XEN) GICH_LRs (vcpu 64) mask=0
Apr 26 15:13:07.969033 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:07.980920 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:07.980977 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:07.981019 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:07.981059 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:07.981099 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:07.981139 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:07.992917 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:07.992974 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:07.993016 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:07.993057 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:07.993097 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:07.993137 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.004913 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.004970 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.005012 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.005053 (XEN) No periodic timer
Apr 26 15:13:08.005093 (XEN)   UNIT65 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.016911 (XEN)     VCPU65: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.016976 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.017021 (XEN) GICH_LRs (vcpu 65) mask=0
Apr 26 15:13:08.028893 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.028949 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.028990 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.029030 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.029070 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.029109 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.040918 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.040974 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.041015 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.041056 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.041096 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.041137 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.052905 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.052961 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.053021 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.053065 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.053105 (XEN) No periodic timer
Apr 26 15:13:08.064918 (XEN)   UNIT66 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.064979 (XEN)     VCPU66: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.076909 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.076968 (XEN) GICH_LRs (vcpu 66) mask=0
Apr 26 15:13:08.077014 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.077055 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.077096 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.088920 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.088976 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.089018 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.089058 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.089097 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.089137 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.100910 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.100965 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.101007 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.101048 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.101088 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.101128 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.112923 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.112979 (XEN) No periodic timer
Apr 26 15:13:08.113021 (XEN)   UNIT67 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.113067 (XEN)     VCPU67: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.124926 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.124984 (XEN) GICH_LRs (vcpu 67) mask=0
Apr 26 15:13:08.125029 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.136903 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.136959 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.137001 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.137042 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.137081 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.137121 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.148898 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.148954 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.148996 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.149037 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.149077 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.149117 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.160910 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.160966 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.161008 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.161049 (XEN) No periodic timer
Apr 26 15:13:08.161090 (XEN)   UNIT68 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.172914 (XEN)     VCPU68: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.172978 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.173022 (XEN) GICH_LRs (vcpu 68) mask=0
Apr 26 15:13:08.184918 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.184973 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.185015 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.185055 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.185095 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.196912 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.196967 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.197008 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.197049 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.197088 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.197127 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.208921 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.208977 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.209018 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.209058 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.209098 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.220908 (XEN) No periodic timer
Apr 26 15:13:08.220965 (XEN)   UNIT69 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.221013 (XEN)     VCPU69: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.232917 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.232975 (XEN) GICH_LRs (vcpu 69) mask=0
Apr 26 15:13:08.233020 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.233060 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.233100 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.244916 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.244972 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.245013 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.245054 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.245094 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.245134 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.256914 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.256989 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.257034 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.257075 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.257115 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.257154 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.268854 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.268909 (XEN) No periodic timer
Apr 26 15:13:08.268951 (XEN)   UNIT70 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.268997 (XEN)     VCPU70: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.280795 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.280795 (XEN) GICH_LRs (vcpu 70) mask=0
Apr 26 15:13:08.280795 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.292876 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.292936 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.292977 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.293017 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.293056 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.293096 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.304845 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.304900 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.304942 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.304982 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.305022 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.316855 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.316911 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.316953 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.316994 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.317033 (XEN) No periodic timer
Apr 26 15:13:08.317074 (XEN)   UNIT71 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.328877 (XEN)     VCPU71: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.328941 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.340858 (XEN) GICH_LRs (vcpu 71) mask=0
Apr 26 15:13:08.340915 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.340957 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.340998 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.341038 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.352861 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.352918 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.352960 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.353000 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.353040 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.353080 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.364906 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.364962 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.365005 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.365045 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.365085 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.365125 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.376913 (XEN) No periodic timer
Apr 26 15:13:08.376970 (XEN)   UNIT72 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.377017 (XEN)     VCPU72: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.388925 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.388983 (XEN) GICH_LRs (vcpu 72) mask=0
Apr 26 15:13:08.389028 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.389068 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.389108 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.400914 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.400969 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.401010 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.401051 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.401091 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.401131 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.412912 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.412967 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.413008 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.413048 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.413088 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.424913 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.424970 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.425012 (XEN) No periodic timer
Apr 26 15:13:08.425053 (XEN)   UNIT73 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.425099 (XEN)     VCPU73: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.436911 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.436969 (XEN) GICH_LRs (vcpu 73) mask=0
Apr 26 15:13:08.448919 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.448975 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.449018 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.449058 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.449098 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.449167 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.460912 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.460967 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.461009 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.461050 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.461089 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.461129 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.472913 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.472968 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.473010 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.473050 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.473089 (XEN) No periodic timer
Apr 26 15:13:08.473130 (XEN)   UNIT74 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.484931 (XEN)     VCPU74: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.484995 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.496918 (XEN) GICH_LRs (vcpu 74) mask=0
Apr 26 15:13:08.496976 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.497017 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.497058 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.497097 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.508923 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.508978 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.509020 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.509060 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.509101 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.509141 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.520915 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.520971 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.521013 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.521055 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.521095 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.521136 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.532921 (XEN) No periodic timer
Apr 26 15:13:08.532977 (XEN)   UNIT75 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.533024 (XEN)     VCPU75: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.544914 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.544972 (XEN) GICH_LRs (vcpu 75) mask=0
Apr 26 15:13:08.545016 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.545057 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.556900 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.556956 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.556998 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.557038 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.557079 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.557119 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.568920 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.568975 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.569016 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.569057 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.569097 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.580904 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.580960 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.581002 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.581042 (XEN) No periodic timer
Apr 26 15:13:08.581084 (XEN)   UNIT76 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.592916 (XEN)     VCPU76: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.592981 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.593025 (XEN) GICH_LRs (vcpu 76) mask=0
Apr 26 15:13:08.604827 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.604827 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.604827 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.604827 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.604827 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.604827 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.616933 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.616993 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.617034 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.617074 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.617114 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.617154 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.628927 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.628982 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.629023 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.629064 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.629104 (XEN) No periodic timer
Apr 26 15:13:08.640941 (XEN)   UNIT77 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.641003 (XEN)     VCPU77: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.641054 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.652928 (XEN) GICH_LRs (vcpu 77) mask=0
Apr 26 15:13:08.652986 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.653048 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.653092 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.653132 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.664913 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.664969 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.665011 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.665051 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.665091 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.665131 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.676916 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.676972 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.677014 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.677054 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.677095 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.677135 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.688920 (XEN) No periodic timer
Apr 26 15:13:08.688976 (XEN)   UNIT78 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.689024 (XEN)     VCPU78: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.700922 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.700980 (XEN) GICH_LRs (vcpu 78) mask=0
Apr 26 15:13:08.701024 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.712917 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.712973 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.713015 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.713055 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.713095 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.713134 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.724920 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.724976 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.725018 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.725059 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.725098 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.725138 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.736921 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.736977 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.737019 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.737059 (XEN) No periodic timer
Apr 26 15:13:08.737100 (XEN)   UNIT79 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.748926 (XEN)     VCPU79: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.748990 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.749034 (XEN) GICH_LRs (vcpu 79) mask=0
Apr 26 15:13:08.760923 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.760979 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.761020 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.761061 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.761100 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.761140 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.772909 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.772963 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.773005 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.773045 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.773086 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.773126 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.784871 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.784926 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.784967 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.785008 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.785048 (XEN) No periodic timer
Apr 26 15:13:08.796905 (XEN)   UNIT80 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.796965 (XEN)     VCPU80: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.797015 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.808913 (XEN) GICH_LRs (vcpu 80) mask=0
Apr 26 15:13:08.808970 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.809012 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.809052 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.820891 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.820946 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.820988 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.821029 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.821069 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.821109 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.832908 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.832964 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.833005 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.833046 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.833085 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.833125 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.844916 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.844972 (XEN) No periodic timer
Apr 26 15:13:08.845014 (XEN)   UNIT81 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.845060 (XEN)     VCPU81: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.856938 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.856997 (XEN) GICH_LRs (vcpu 81) mask=0
Apr 26 15:13:08.857041 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.868924 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.868979 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.869020 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.869061 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.869100 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.869140 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.880910 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.880966 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.881008 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.881048 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.881087 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.881127 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.892919 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.892974 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.893016 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.893056 (XEN) No periodic timer
Apr 26 15:13:08.893097 (XEN)   UNIT82 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.904918 (XEN)     VCPU82: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.904982 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.905027 (XEN) GICH_LRs (vcpu 82) mask=0
Apr 26 15:13:08.916918 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.916973 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.917014 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.917054 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.917094 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.928918 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.928974 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.929016 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.929056 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.929096 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.929136 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.940912 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.940968 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.941010 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.941050 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:08.941091 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:08.952914 (XEN) No periodic timer
Apr 26 15:13:08.952970 (XEN)   UNIT83 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:08.953017 (XEN)     VCPU83: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:08.964921 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:08.964980 (XEN) GICH_LRs (vcpu 83) mask=0
Apr 26 15:13:08.965024 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:08.965065 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:08.965105 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:08.976915 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:08.976971 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:08.977012 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:08.977052 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:08.977092 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:08.977131 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:08.988923 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:08.988978 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:08.989019 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:08.989060 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:08.989100 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:08.989140 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.000916 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.000971 (XEN) No periodic timer
Apr 26 15:13:09.001013 (XEN)   UNIT84 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.001059 (XEN)     VCPU84: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.012920 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.012978 (XEN) GICH_LRs (vcpu 84) mask=0
Apr 26 15:13:09.013023 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.024911 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.024966 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.025007 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.025048 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.025087 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.025127 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.036919 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.036974 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.037016 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.037056 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.037096 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.037136 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.048924 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.048980 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.049040 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.049084 (XEN) No periodic timer
Apr 26 15:13:09.049125 (XEN)   UNIT85 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.060912 (XEN)     VCPU85: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.060977 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.061021 (XEN) GICH_LRs (vcpu 85) mask=0
Apr 26 15:13:09.072909 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.072965 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.073006 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.073046 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.084906 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.084962 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.085004 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.085044 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.085084 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.085123 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.096883 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.096939 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.096980 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.097022 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.097062 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.097103 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.108862 (XEN) No periodic timer
Apr 26 15:13:09.108911 (XEN)   UNIT86 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.108957 (XEN)     VCPU86: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.120915 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.120974 (XEN) GICH_LRs (vcpu 86) mask=0
Apr 26 15:13:09.121018 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.121059 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.121099 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.132914 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.132969 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.133010 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.133050 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.133090 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.133130 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.144906 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.144961 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.145002 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.145043 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.145082 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.156921 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.156977 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.157019 (XEN) No periodic timer
Apr 26 15:13:09.157061 (XEN)   UNIT87 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.157107 (XEN)     VCPU87: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.168924 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.168982 (XEN) GICH_LRs (vcpu 87) mask=0
Apr 26 15:13:09.169026 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.180919 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.180974 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.181015 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.181056 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.181096 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.181136 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.192909 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.192964 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.193006 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.193046 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.193086 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.204917 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.204972 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.205014 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.205054 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.205094 (XEN) No periodic timer
Apr 26 15:13:09.205134 (XEN)   UNIT88 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.216920 (XEN)     VCPU88: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.216983 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.228926 (XEN) GICH_LRs (vcpu 88) mask=0
Apr 26 15:13:09.228983 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.229025 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.229065 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.229105 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.240908 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.240964 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.241006 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.241047 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.241087 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.241126 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.252932 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.252990 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.253032 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.253072 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.253111 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.253151 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.264917 (XEN) No periodic timer
Apr 26 15:13:09.264973 (XEN)   UNIT89 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.265020 (XEN)     VCPU89: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.276910 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.276968 (XEN) GICH_LRs (vcpu 89) mask=0
Apr 26 15:13:09.277013 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.277054 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.288932 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.288989 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.289030 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.289071 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.289110 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.289150 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.300919 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.300975 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.301018 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.301059 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.301099 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.301140 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.312847 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.312903 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.312945 (XEN) No periodic timer
Apr 26 15:13:09.312986 (XEN)   UNIT90 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.313032 (XEN)     VCPU90: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.324917 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.324975 (XEN) GICH_LRs (vcpu 90) mask=0
Apr 26 15:13:09.336916 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.336972 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.337014 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.337054 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.337095 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.337134 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.348896 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.348951 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.348993 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.349033 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.349073 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.349113 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.360904 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.360960 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.361002 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.361043 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.361083 (XEN) No periodic timer
Apr 26 15:13:09.372908 (XEN)   UNIT91 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.372970 (XEN)     VCPU91: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.373021 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.384930 (XEN) GICH_LRs (vcpu 91) mask=0
Apr 26 15:13:09.384988 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.385030 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.385071 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.385110 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.396913 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.396968 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.397010 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.397051 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.397091 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.397130 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.408922 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.408978 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.409020 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.409060 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.409100 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.409140 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.420918 (XEN) No periodic timer
Apr 26 15:13:09.420973 (XEN)   UNIT92 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.421021 (XEN)     VCPU92: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.432919 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.432976 (XEN) GICH_LRs (vcpu 92) mask=0
Apr 26 15:13:09.433021 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.433062 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.444873 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.444930 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.444971 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.445012 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.445070 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.456883 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.456939 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.456981 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.457021 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.457061 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.457100 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.468881 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.468937 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.468979 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.469020 (XEN) No periodic timer
Apr 26 15:13:09.469060 (XEN)   UNIT93 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.480885 (XEN)     VCPU93: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.480949 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.480994 (XEN) GICH_LRs (vcpu 93) mask=0
Apr 26 15:13:09.492881 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.492937 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.492978 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.493019 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.493059 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.493098 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.504856 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.504912 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.504953 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.504993 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.505033 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.505073 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.516883 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.516939 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.516980 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.517021 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.517061 (XEN) No periodic timer
Apr 26 15:13:09.528888 (XEN)   UNIT94 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.528949 (XEN)     VCPU94: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.528999 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.540891 (XEN) GICH_LRs (vcpu 94) mask=0
Apr 26 15:13:09.540949 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.540991 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.541031 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.541070 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.552885 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.552940 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.552981 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.553022 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.553061 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.553101 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.564883 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.564939 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.564981 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.565021 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.565061 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.565101 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.576875 (XEN) No periodic timer
Apr 26 15:13:09.576930 (XEN)   UNIT95 affinities: hard={0-95} soft={0-95}
Apr 26 15:13:09.576977 (XEN)     VCPU95: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Apr 26 15:13:09.588897 (XEN)     pause_count=0 pause_flags=1
Apr 26 15:13:09.588955 (XEN) GICH_LRs (vcpu 95) mask=0
Apr 26 15:13:09.588998 (XEN)    VCPU_LR[0]=0
Apr 26 15:13:09.600910 (XEN)    VCPU_LR[1]=0
Apr 26 15:13:09.600966 (XEN)    VCPU_LR[2]=0
Apr 26 15:13:09.601007 (XEN)    VCPU_LR[3]=0
Apr 26 15:13:09.601048 (XEN)    VCPU_LR[4]=0
Apr 26 15:13:09.601087 (XEN)    VCPU_LR[5]=0
Apr 26 15:13:09.601127 (XEN)    VCPU_LR[6]=0
Apr 26 15:13:09.612914 (XEN)    VCPU_LR[7]=0
Apr 26 15:13:09.612969 (XEN)    VCPU_LR[8]=0
Apr 26 15:13:09.613010 (XEN)    VCPU_LR[9]=0
Apr 26 15:13:09.613050 (XEN)    VCPU_LR[10]=0
Apr 26 15:13:09.613090 (XEN)    VCPU_LR[11]=0
Apr 26 15:13:09.613129 (XEN)    VCPU_LR[12]=0
Apr 26 15:13:09.624908 (XEN)    VCPU_LR[13]=0
Apr 26 15:13:09.624964 (XEN)    VCPU_LR[14]=0
Apr 26 15:13:09.625005 (XEN)    VCPU_LR[15]=0
Apr 26 15:13:09.625046 (XEN) No periodic timer
Apr 26 15:13:09.625087 (XEN) Notifying guest 0:0 (virq 1, port 0)
Apr 26 15:13:09.636915 (XEN) Notifying guest 0:1 (virq 1, port 0)
Apr 26 15:13:09.636975 (XEN) Notifying guest 0:2 (virq 1, port 0)
Apr 26 15:13:09.637019 (XEN) Notifying guest 0:3 (virq 1, port 0)
Apr 26 15:13:09.648903 (XEN) Notifying guest 0:4 (virq 1, port 0)
Apr 26 15:13:09.648982 (XEN) Notifying guest 0:5 (virq 1, port 0)
Apr 26 15:13:09.649030 (XEN) Notifying guest 0:6 (virq 1, port 0)
Apr 26 15:13:09.660924 (XEN) Notifying guest 0:7 (virq 1, port 0)
Apr 26 15:13:09.660984 (XEN) Notifying guest 0:8 (virq 1, port 0)
Apr 26 15:13:09.661029 (XEN) Notifying guest 0:9 (virq 1, port 0)
Apr 26 15:13:09.661073 (XEN) Notifying guest 0:10 (virq 1, port 0)
Apr 26 15:13:09.672912 (XEN) Notifying guest 0:11 (virq 1, port 0)
Apr 26 15:13:09.672971 (XEN) Notifying guest 0:12 (virq 1, port 0)
Apr 26 15:13:09.673016 (XEN) Notifying guest 0:13 (virq 1, port 0)
Apr 26 15:13:09.684918 (XEN) Notifying guest 0:14 (virq 1, port 0)
Apr 26 15:13:09.684976 (XEN) Notifying guest 0:15 (virq 1, port 0)
Apr 26 15:13:09.685021 (XEN) Notifying guest 0:16 (virq 1, port 0)
Apr 26 15:13:09.696915 (XEN) Notifying guest 0:17 (virq 1, port 0)
Apr 26 15:13:09.696975 (XEN) Notifying guest 0:18 (virq 1, port 0)
Apr 26 15:13:09.697019 (XEN) Notifying guest 0:19 (virq 1, port 0)
Apr 26 15:13:09.708911 (XEN) Notifying guest 0:20 (virq 1, port 0)
Apr 26 15:13:09.708969 (XEN) Notifying guest 0:21 (virq 1, port 0)
Apr 26 15:13:09.720912 (XEN) Notifying guest 0:22 (virq 1, port 0)
Apr 26 15:13:09.720973 (XEN) Notifying guest 0:23 (virq 1, port 0)
Apr 26 15:13:09.721018 (XEN) Notifying guest 0:24 (virq 1, port 0)
Apr 26 15:13:09.721061 (XEN) Notifying guest 0:25 (virq 1, port 0)
Apr 26 15:13:09.732916 (XEN) Notifying guest 0:26 (virq 1, port 0)
Apr 26 15:13:09.732975 (XEN) Notifying guest 0:27 (virq 1, port 0)
Apr 26 15:13:09.733020 (XEN) Notifying guest 0:28 (virq 1, port 0)
Apr 26 15:13:09.744921 (XEN) Notifying guest 0:29 (virq 1, port 0)
Apr 26 15:13:09.744980 (XEN) Notifying guest 0:30 (virq 1, port 0)
Apr 26 15:13:09.745025 (XEN) Notifying guest 0:31 (virq 1, port 0)
Apr 26 15:13:09.756913 (XEN) Notifying guest 0:32 (virq 1, port 0)
Apr 26 15:13:09.756971 (XEN) Notifying guest 0:33 (virq 1, port 0)
Apr 26 15:13:09.757016 (XEN) Notifying guest 0:34 (virq 1, port 0)
Apr 26 15:13:09.768927 (XEN) Notifying guest 0:35 (virq 1, port 0)
Apr 26 15:13:09.768986 (XEN) Notifying guest 0:36 (virq 1, port 0)
Apr 26 15:13:09.769031 (XEN) Notifying guest 0:37 (virq 1, port 0)
Apr 26 15:13:09.780915 (XEN) Notifying guest 0:38 (virq 1, port 0)
Apr 26 15:13:09.780974 (XEN) Notifying guest 0:39 (virq 1, port 0)
Apr 26 15:13:09.781020 (XEN) Notifying guest 0:40 (virq 1, port 0)
Apr 26 15:13:09.792925 (XEN) Notifying guest 0:41 (virq 1, port 0)
Apr 26 15:13:09.792984 (XEN) Notifying guest 0:42 (virq 1, port 0)
Apr 26 15:13:09.793029 (XEN) Notifying guest 0:43 (virq 1, port 0)
Apr 26 15:13:09.804922 (XEN) Notifying guest 0:44 (virq 1, port 0)
Apr 26 15:13:09.804981 (XEN) Notifying guest 0:45 (virq 1, port 0)
Apr 26 15:13:09.805025 (XEN) Notifying guest 0:46 (virq 1, port 0)
Apr 26 15:13:09.816915 (XEN) Notifying guest 0:47 (virq 1, port 0)
Apr 26 15:13:09.816975 (XEN) Notifying guest 0:48 (virq 1, port 0)
Apr 26 15:13:09.817020 (XEN) Notifying guest 0:49 (virq 1, port 0)
Apr 26 15:13:09.828906 (XEN) Notifying guest 0:50 (virq 1, port 0)
Apr 26 15:13:09.828965 (XEN) Notifying guest 0:51 (virq 1, port 0)
Apr 26 15:13:09.829010 (XEN) Notifying guest 0:52 (virq 1, port 0)
Apr 26 15:13:09.840915 (XEN) Notifying guest 0:53 (virq 1, port 0)
Apr 26 15:13:09.840974 (XEN) Notifying guest 0:54 (virq 1, port 0)
Apr 26 15:13:09.841018 (XEN) Notifying guest 0:55 (virq 1, port 0)
Apr 26 15:13:09.852902 (XEN) Notifying guest 0:56 (virq 1, port 0)
Apr 26 15:13:09.852960 (XEN) Notifying guest 0:57 (virq 1, port 0)
Apr 26 15:13:09.853005 (XEN) Notifying guest 0:58 (virq 1, port 0)
Apr 26 15:13:09.864876 (XEN) Notifying guest 0:59 (virq 1, port 0)
Apr 26 15:13:09.864934 (XEN) Notifying guest 0:60 (virq 1, port 0)
Apr 26 15:13:09.864979 (XEN) Notifying guest 0:61 (virq 1, port 0)
Apr 26 15:13:09.876912 (XEN) Notifying guest 0:62 (virq 1, port 0)
Apr 26 15:13:09.876971 (XEN) Notifying guest 0:63 (virq 1, port 0)
Apr 26 15:13:09.877015 (XEN) Notifying guest 0:64 (virq 1, port 0)
Apr 26 15:13:09.888941 (XEN) Notifying guest 0:65 (virq 1, port 0)
Apr 26 15:13:09.889001 (XEN) Notifying guest 0:66 (virq 1, port 0)
Apr 26 15:13:09.889046 (XEN) Notifying guest 0:67 (virq 1, port 0)
Apr 26 15:13:09.900910 (XEN) Notifying guest 0:68 (virq 1, port 0)
Apr 26 15:13:09.900970 (XEN) Notifying guest 0:69 (virq 1, port 0)
Apr 26 15:13:09.901015 (XEN) Notifying guest 0:70 (virq 1, port 0)
Apr 26 15:13:09.912923 (XEN) Notifying guest 0:71 (virq 1, port 0)
Apr 26 15:13:09.912982 (XEN) Notifying guest 0:72 (virq 1, port 0)
Apr 26 15:13:09.913027 (XEN) Notifying guest 0:73 (virq 1, port 0)
Apr 26 15:13:09.924876 (XEN) Notifying guest 0:74 (virq 1, port 0)
Apr 26 15:13:09.924935 (XEN) Notifying guest 0:75 (virq 1, port 0)
Apr 26 15:13:09.924979 (XEN) Notifying guest 0:76 (virq 1, port 0)
Apr 26 15:13:09.936804 (XEN) Notifying guest 0:77 (virq 1, port 0)
Apr 26 15:13:09.936854 (XEN) Notifying guest 0:78 (virq 1, port 0)
Apr 26 15:13:09.936898 (XEN) Notifying guest 0:79 (virq 1, port 0)
Apr 26 15:13:09.948767 (XEN) Notifying guest 0:80 (virq 1, port 0)
Apr 26 15:13:09.948799 (XEN) Notifying guest 0:81 (virq 1, port 0)
Apr 26 15:13:09.948824 (XEN) Notifying guest 0:82 (virq 1, port 0)
Apr 26 15:13:09.960755 (XEN) Notifying guest 0:83 (virq 1, port 0)
Apr 26 15:13:09.960788 (XEN) Notifying guest 0:84 (virq 1, port 0)
Apr 26 15:13:09.960813 (XEN) Notifying guest 0:85 (virq 1, port 0)
Apr 26 15:13:09.972858 (XEN) Notifying guest 0:86 (virq 1, port 0)
Apr 26 15:13:09.972917 (XEN) Notifying guest 0:87 (virq 1, port 0)
Apr 26 15:13:09.972962 (XEN) Notifying guest 0:88 (virq 1, port 0)
Apr 26 15:13:09.984855 (XEN) Notifying guest 0:89 (virq 1, port 0)
Apr 26 15:13:09.984914 (XEN) Notifying guest 0:90 (virq 1, port 0)
Apr 26 15:13:09.984958 (XEN) Notifying guest 0:91 (virq 1, port 0)
Apr 26 15:13:09.996914 (XEN) Notifying guest 0:92 (virq 1, port 0)
Apr 26 15:13:09.996973 (XEN) Notifying guest 0:93 (virq 1, port 0)
Apr 26 15:13:09.997019 (XEN) Notifying guest 0:94 (virq 1, port 0)
Apr 26 15:13:10.008881 (XEN) Notifying guest 0:95 (virq 1, port 0)
Apr 26 15:13:10.008940 Apr 26 15:13:16.506482 <client 0x195a580 connected - now 1 clients>
(XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input)
Apr 26 15:13:16.524814 Apr 26 15:13:16.526170 <client 0x195a580 disconnected - now 0 clients>