Apr 26 17:09:34.539062 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:34.539390 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:34.548656 (XEN) X18: 0000000000000000 X19: 00000a00003825cc X20: 000000000000003e Apr 26 17:09:34.548656 (XEN) X21: 00000a0000347380 X22: 0000000040000000 X23: 000000000000003e Apr 26 17:09:34.560693 (XEN) X24: 000000000000003e X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:34.560693 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffc0fe60 Apr 26 17:09:34.572656 (XEN) Apr 26 17:09:34.572656 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:34.572656 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:34.572656 (XEN) Apr 26 17:09:34.584654 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:34.584654 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:34.584654 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:34.584654 (XEN) Apr 26 17:09:34.584654 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:34.596653 (XEN) HPFAR_EL2: 0000009010804300 Apr 26 17:09:34.596653 (XEN) FAR_EL2: ffff80000b430100 Apr 26 17:09:34.596653 (XEN) Apr 26 17:09:34.596653 (XEN) Xen stack trace from sp=0000800fffc0fe60: Apr 26 17:09:34.608654 (XEN) 0000800fffc0fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:34.608654 (XEN) 000000000000003e 0000000000000000 0000000000000000 000000000001000e Apr 26 17:09:34.620658 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.620658 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.632668 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.632668 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.644665 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.656670 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.656670 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.668666 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.668666 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.680669 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.680669 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.692670 (XEN) Xen call trace: Apr 26 17:09:34.692670 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:34.704670 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:34.704670 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:34.716932 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:34.717020 (XEN) Apr 26 17:09:34.717063 (XEN) *** Dumping CPU63 host state: *** Apr 26 17:09:34.717109 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:34.728905 (XEN) CPU: 63 Apr 26 17:09:34.728960 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:34.729034 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:34.740932 (XEN) SP: 0000800ffdf9fe60 Apr 26 17:09:34.740990 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:34.741041 (XEN) X0: 0000000000000000 X1: 0000760fff8d8000 X2: 0000800fffc18078 Apr 26 17:09:34.752936 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:34.764936 (XEN) X6: 00000a00003825c8 X7: 0000800fffc1a280 X8: 0000000000000012 Apr 26 17:09:34.765000 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:34.776930 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:34.776993 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:34.788953 (XEN) X18: 0000000000000000 X19: 00000a00003825cc X20: 000000000000003f Apr 26 17:09:34.789040 (XEN) X21: 00000a0000347400 X22: 0000000080000000 X23: 000000000000003f Apr 26 17:09:34.800947 (XEN) X24: 000000000000003f X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:34.801009 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf9fe60 Apr 26 17:09:34.812947 (XEN) Apr 26 17:09:34.813001 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:34.813046 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:34.824932 (XEN) Apr 26 17:09:34.824985 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:34.825030 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:34.825074 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:34.825117 (XEN) Apr 26 17:09:34.825178 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:34.836922 (XEN) HPFAR_EL2: 0000009010804f00 Apr 26 17:09:34.836981 (XEN) FAR_EL2: ffff80000b4f0100 Apr 26 17:09:34.837026 (XEN) Apr 26 17:09:34.837065 (XEN) Xen stack trace from sp=0000800ffdf9fe60: Apr 26 17:09:34.848925 (XEN) 0000800ffdf9fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:34.848989 (XEN) 000000000000003f 0000000000000000 0000000000000000 000000000001000f Apr 26 17:09:34.860929 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.860991 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.872951 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.873035 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.884926 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.896937 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.896999 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.908923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.909008 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.920951 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.921013 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:34.932935 (XEN) Xen call trace: Apr 26 17:09:34.932991 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:34.944932 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:34.944998 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:34.956936 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:34.956998 (XEN) Apr 26 17:09:34.957039 (XEN) *** Dumping CPU64 host state: *** Apr 26 17:09:34.957107 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:34.968946 (XEN) CPU: 64 Apr 26 17:09:34.969002 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:34.980935 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:34.980993 (XEN) SP: 0000800ffdf97e60 Apr 26 17:09:34.981058 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:34.981109 (XEN) X0: 0000000000000000 X1: 0000760fff8c4000 X2: 0000800fffc04078 Apr 26 17:09:34.992939 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:35.004936 (XEN) X6: 00000a00003825c8 X7: 0000800fffc1a740 X8: 0000000000000012 Apr 26 17:09:35.005000 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:35.016937 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:35.016999 (XEN) X15: 0000000000000001 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:35.028941 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000040 Apr 26 17:09:35.029004 (XEN) X21: 00000a0000347480 X22: 0000000000000001 X23: 0000000000000040 Apr 26 17:09:35.040959 (XEN) X24: 0000000000000040 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:35.052918 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf97e60 Apr 26 17:09:35.052984 (XEN) Apr 26 17:09:35.053024 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:35.053068 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:35.064920 (XEN) Apr 26 17:09:35.064996 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:35.065042 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:35.065086 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:35.065129 (XEN) Apr 26 17:09:35.076920 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:35.077000 (XEN) HPFAR_EL2: 0000009010805d00 Apr 26 17:09:35.077047 (XEN) FAR_EL2: ffff80000b5d0100 Apr 26 17:09:35.077091 (XEN) Apr 26 17:09:35.077130 (XEN) Xen stack trace from sp=0000800ffdf97e60: Apr 26 17:09:35.088920 (XEN) 0000800ffdf97e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:35.089007 (XEN) 0000000000000040 0000000000000000 0000000000000000 0000000000010100 Apr 26 17:09:35.100935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.100997 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.112930 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.124927 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.125012 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.136920 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.136983 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.148923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.148986 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.160943 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.161005 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.172927 (XEN) Xen call trace: Apr 26 17:09:35.172983 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:35.184925 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:35.184990 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:35.196933 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:35.196992 (XEN) Apr 26 17:09:35.197032 (XEN) *** Dumping CPU65 host state: *** Apr 26 17:09:35.197077 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:35.208935 (XEN) CPU: 65 Apr 26 17:09:35.209012 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:35.220940 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:35.220997 (XEN) SP: 0000800ffdf8fe60 Apr 26 17:09:35.221041 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:35.232915 (XEN) X0: 0000000000000000 X1: 0000760fff8c2000 X2: 0000800fffc02078 Apr 26 17:09:35.233001 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:35.244928 (XEN) X6: 00000a00003825c8 X7: 0000800fffc1ac00 X8: 0000000000000012 Apr 26 17:09:35.244991 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:35.256931 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:35.256995 (XEN) X15: 0000000000000001 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:35.268941 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000041 Apr 26 17:09:35.269004 (XEN) X21: 00000a0000347500 X22: 0000000000000002 X23: 0000000000000041 Apr 26 17:09:35.280936 (XEN) X24: 0000000000000041 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:35.292935 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf8fe60 Apr 26 17:09:35.293017 (XEN) Apr 26 17:09:35.293083 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:35.293128 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:35.304941 (XEN) Apr 26 17:09:35.304993 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:35.305037 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:35.305101 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:35.316926 (XEN) Apr 26 17:09:35.316979 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:35.317024 (XEN) HPFAR_EL2: 0000000000030300 Apr 26 17:09:35.317068 (XEN) FAR_EL2: ffff80000b010100 Apr 26 17:09:35.317133 (XEN) Apr 26 17:09:35.317172 (XEN) Xen stack trace from sp=0000800ffdf8fe60: Apr 26 17:09:35.328931 (XEN) 0000800ffdf8fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:35.328995 (XEN) 0000000000000041 0000000000000000 0000000000000000 0000000000010101 Apr 26 17:09:35.340952 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.341039 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.352919 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.364913 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.364976 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.376940 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.377024 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.388926 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.388989 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.400942 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.412928 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.413013 (XEN) Xen call trace: Apr 26 17:09:35.413058 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:35.424934 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:35.425021 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:35.436927 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:35.436987 (XEN) Apr 26 17:09:35.437029 (XEN) *** Dumping CPU66 host state: *** Apr 26 17:09:35.448933 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:35.449020 (XEN) CPU: 66 Apr 26 17:09:35.449063 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:35.460918 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:35.460977 (XEN) SP: 0000800ffdf1fe60 Apr 26 17:09:35.461022 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:35.472937 (XEN) X0: 0000000000000000 X1: 0000760ffdc46000 X2: 0000800ffdf86078 Apr 26 17:09:35.473001 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:35.484928 (XEN) X6: 00000a00003825c8 X7: 0000800ffdf85150 X8: 0000000000000012 Apr 26 17:09:35.484992 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:35.496933 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:35.496995 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:35.508897 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000042 Apr 26 17:09:35.520944 (XEN) X21: 00000a0000347580 X22: 0000000000000004 X23: 0000000000000042 Apr 26 17:09:35.521007 (XEN) X24: 0000000000000042 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:35.532927 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf1fe60 Apr 26 17:09:35.532991 (XEN) Apr 26 17:09:35.533031 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:35.544921 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:35.544979 (XEN) Apr 26 17:09:35.545036 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:35.545084 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:35.545127 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:35.556924 (XEN) Apr 26 17:09:35.556977 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:35.557022 (XEN) HPFAR_EL2: 0000008010801500 Apr 26 17:09:35.557066 (XEN) FAR_EL2: ffff80000a950100 Apr 26 17:09:35.557108 (XEN) Apr 26 17:09:35.568921 (XEN) Xen stack trace from sp=0000800ffdf1fe60: Apr 26 17:09:35.568982 (XEN) 0000800ffdf1fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:35.569033 (XEN) 0000000000000042 0000000000000000 0000000000000000 0000000000010102 Apr 26 17:09:35.580932 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.592929 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.592991 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.604921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.604983 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.616921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.616984 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.628934 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.640934 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.640997 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.652920 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.652982 (XEN) Xen call trace: Apr 26 17:09:35.653026 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:35.664927 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:35.664992 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:35.676936 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:35.676995 (XEN) Apr 26 17:09:35.677035 (XEN) *** Dumping CPU67 host state: *** Apr 26 17:09:35.688922 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:35.688986 (XEN) CPU: 67 Apr 26 17:09:35.689028 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:35.700936 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:35.700993 (XEN) SP: 0000800ffdf17e60 Apr 26 17:09:35.701036 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:35.712930 (XEN) X0: 0000000000000000 X1: 0000760ffdc42000 X2: 0000800ffdf82078 Apr 26 17:09:35.712993 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:35.724944 (XEN) X6: 00000a00003825c8 X7: 0000800ffdf85590 X8: 0000800f21033000 Apr 26 17:09:35.725007 (XEN) X9: 0000000000000000 X10: 00000000000009d0 X11: 0000000000000000 Apr 26 17:09:35.736932 (XEN) X12: 0000000000000064 X13: 0000000000000000 X14: 0000000000000368 Apr 26 17:09:35.736994 (XEN) X15: ffff000002d14d58 X16: 00000000deadbeef X17: 0000000000000000 Apr 26 17:09:35.748942 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000043 Apr 26 17:09:35.760933 (XEN) X21: 00000a0000347600 X22: 0000000000000008 X23: 0000000000000043 Apr 26 17:09:35.760996 (XEN) X24: 0000000000000043 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:35.772928 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf17e60 Apr 26 17:09:35.772992 (XEN) Apr 26 17:09:35.773032 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:35.784926 (XEN) VTTBR_EL2: 00020107fc6da000 Apr 26 17:09:35.784984 (XEN) Apr 26 17:09:35.785023 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:35.785067 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:35.785109 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:35.796916 (XEN) Apr 26 17:09:35.796988 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:35.797035 (XEN) HPFAR_EL2: 0000000000030300 Apr 26 17:09:35.797078 (XEN) FAR_EL2: ffff80000b010100 Apr 26 17:09:35.808932 (XEN) Apr 26 17:09:35.808985 (XEN) Xen stack trace from sp=0000800ffdf17e60: Apr 26 17:09:35.809032 (XEN) 0000800ffdf17e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:35.820933 (XEN) 0000000000000043 0000000000000000 0000000000000000 0000000000010103 Apr 26 17:09:35.820996 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.832924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.832986 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.844929 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.844991 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.856916 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.856977 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.868906 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.880943 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.881004 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.892929 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:35.892990 (XEN) Xen call trace: Apr 26 17:09:35.893033 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:35.904936 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:35.916926 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:35.916988 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:35.917034 (XEN) Apr 26 17:09:35.917072 (XEN) *** Dumping CPU68 host state: *** Apr 26 17:09:35.928930 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:35.928993 (XEN) CPU: 68 Apr 26 17:09:35.929034 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:35.940928 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:35.940984 (XEN) SP: 0000800ffdf07e60 Apr 26 17:09:35.941028 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:35.952944 (XEN) X0: 0000000000000000 X1: 0000760ffdc40000 X2: 0000800ffdf80078 Apr 26 17:09:35.953008 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:35.964843 (XEN) X6: 00000a00003825c8 X7: 0000800ffdf85a50 X8: 0000000000000012 Apr 26 17:09:35.964843 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000001 Apr 26 17:09:35.976888 (XEN) X12: 0000000000000000 X13: 0000000000000000 X14: 0000000000000053 Apr 26 17:09:35.988928 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:35.988995 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000044 Apr 26 17:09:36.000829 (XEN) X21: 00000a0000347680 X22: 0000000000000010 X23: 0000000000000044 Apr 26 17:09:36.000892 (XEN) X24: 0000000000000044 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:36.016866 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf07e60 Apr 26 17:09:36.016929 (XEN) Apr 26 17:09:36.016968 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:36.017011 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:36.028852 (XEN) Apr 26 17:09:36.028905 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:36.028949 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:36.028992 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:36.029038 (XEN) Apr 26 17:09:36.029085 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:36.040716 (XEN) HPFAR_EL2: 0000008010000200 Apr 26 17:09:36.040716 (XEN) FAR_EL2: ffff80000a380090 Apr 26 17:09:36.040716 (XEN) Apr 26 17:09:36.040716 (XEN) Xen stack trace from sp=0000800ffdf07e60: Apr 26 17:09:36.048679 (XEN) 0000800ffdf07e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:36.060949 (XEN) 0000000000000044 0000000000000000 0000000000000000 0000000000010104 Apr 26 17:09:36.061016 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.072931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.072993 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.084936 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.084998 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.096934 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.112908 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.112970 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.113018 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.124891 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.124953 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.136713 (XEN) Xen call trace: Apr 26 17:09:36.136713 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:36.148907 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:36.148988 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:36.160755 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:36.160755 (XEN) Apr 26 17:09:36.160755 (XEN) *** Dumping CPU69 host state: *** Apr 26 17:09:36.160755 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:36.172929 (XEN) CPU: 69 Apr 26 17:09:36.172988 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:36.184871 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:36.184929 (XEN) SP: 0000800ffde9fe60 Apr 26 17:09:36.184972 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:36.192897 (XEN) X0: 0000000000000000 X1: 0000760ffdbcc000 X2: 0000800ffdf0c078 Apr 26 17:09:36.192961 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:36.204902 (XEN) X6: 00000a00003825c8 X7: 0000800ffdf0b010 X8: 0000000000000012 Apr 26 17:09:36.220839 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:36.220901 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:36.220951 (XEN) X15: 00000000d39a Apr 26 17:09:36.231265 7f64 X16: 000000002c3b9214 X17: ffff800009f15538 Apr 26 17:09:36.233836 (XEN) X18: ffff80001dd8bc38 X19: 00000a00003825d0 X20: 0000000000000045 Apr 26 17:09:36.233875 (XEN) X Apr 26 17:09:36.237086 21: 00000a0000347700 X22: 0000000000000020 X23: 0000000000000045 Apr 26 17:09:36.244751 (XEN) X24: 0000000000000045 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:36.256795 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde9fe60 Apr 26 17:09:36.256795 (XEN) Apr 26 17:09:36.256795 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:36.256795 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:36.268768 (XEN) Apr 26 17:09:36.268768 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:36.268768 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:36.268768 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:36.276912 (XEN) Apr 26 17:09:36.276972 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:36.277017 (XEN) HPFAR_EL2: 0000000000030300 Apr 26 17:09:36.277060 (XEN) FAR_EL2: ffff80000b010100 Apr 26 17:09:36.288909 (XEN) Apr 26 17:09:36.288963 (XEN) Xen stack trace from sp=0000800ffde9fe60: Apr 26 17:09:36.289030 (XEN) 0000800ffde9fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:36.300905 (XEN) 0000000000000045 0000000000000000 0000000000000000 0000000000010105 Apr 26 17:09:36.300967 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.312904 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.312967 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.324934 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.324997 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.336936 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.348928 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.348990 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.360931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.360993 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.372935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.372997 (XEN) Xen call trace: Apr 26 17:09:36.384931 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:36.384997 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:36.396928 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:36.396991 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:36.397038 (XEN) Apr 26 17:09:36.408922 (XEN) *** Dumping CPU70 host state: *** Apr 26 17:09:36.408982 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:36.409032 (XEN) CPU: 70 Apr 26 17:09:36.409072 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:36.420941 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:36.420998 (XEN) SP: 0000800ffde97e60 Apr 26 17:09:36.421042 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:36.432940 (XEN) X0: 0000000000000000 X1: 0000760ffdbc8000 X2: 0000800ffdf08078 Apr 26 17:09:36.433004 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:36.444930 (XEN) X6: 00000a00003825c8 X7: 0000800ffdf0b410 X8: 0000000000000012 Apr 26 17:09:36.456934 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:36.456997 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:36.468937 (XEN) X15: ffff0000289c9a0c X16: ffff80000929f0b8 X17: 0000000000000000 Apr 26 17:09:36.469001 (XEN) X18: ffff80000da73c58 X19: 00000a00003825d0 X20: 0000000000000046 Apr 26 17:09:36.480932 (XEN) X21: 00000a0000347780 X22: 0000000000000040 X23: 0000000000000046 Apr 26 17:09:36.480994 (XEN) X24: 0000000000000046 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:36.492928 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde97e60 Apr 26 17:09:36.492991 (XEN) Apr 26 17:09:36.504920 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:36.504978 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:36.505022 (XEN) Apr 26 17:09:36.505061 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:36.505103 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:36.516936 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:36.516994 (XEN) Apr 26 17:09:36.517034 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:36.517077 (XEN) HPFAR_EL2: 0000008010804500 Apr 26 17:09:36.517119 (XEN) FAR_EL2: ffff80000ac50100 Apr 26 17:09:36.528933 (XEN) Apr 26 17:09:36.528986 (XEN) Xen stack trace from sp=0000800ffde97e60: Apr 26 17:09:36.529033 (XEN) 0000800ffde97e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:36.540928 (XEN) 0000000000000046 0000000000000000 0000000000000000 0000000000010106 Apr 26 17:09:36.541009 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.552931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.552995 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.564937 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.576929 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.576992 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.588922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.588985 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.600927 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.600990 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.612925 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.612987 (XEN) Xen call trace: Apr 26 17:09:36.624926 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:36.624991 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:36.636939 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:36.637002 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:36.648927 (XEN) Apr 26 17:09:36.648980 (XEN) *** Dumping CPU71 host state: *** Apr 26 17:09:36.649027 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:36.649076 (XEN) CPU: 71 Apr 26 17:09:36.649116 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:36.660956 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:36.661013 (XEN) SP: 0000800ffde87e60 Apr 26 17:09:36.661057 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:36.672940 (XEN) X0: 0000000000000000 X1: 0000760ffdb4e000 X2: 0000800ffde8e078 Apr 26 17:09:36.684933 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:36.684998 (XEN) X6: 00000a00003825c8 X7: 0000800ffdf0b8d0 X8: 0000000000000012 Apr 26 17:09:36.696931 (XEN) X9: 0000000000000000 X10: 00000000000009d0 X11: 0000000000000001 Apr 26 17:09:36.696995 (XEN) X12: 0000000000000000 X13: 0000000000000000 X14: 00000000000000a1 Apr 26 17:09:36.708924 (XEN) X15: ffff80000800b7e0 X16: 000000000000001d X17: 0000000000000000 Apr 26 17:09:36.708987 (XEN) X18: 0000000000000006 X19: 00000a00003825d0 X20: 0000000000000047 Apr 26 17:09:36.720951 (XEN) X21: 00000a0000347800 X22: 0000000000000080 X23: 0000000000000047 Apr 26 17:09:36.721014 (XEN) X24: 0000000000000047 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:36.732935 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde87e60 Apr 26 17:09:36.744921 (XEN) Apr 26 17:09:36.744974 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:36.745019 (XEN) VTTBR_EL2: 000201072029e000 Apr 26 17:09:36.745062 (XEN) Apr 26 17:09:36.745101 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:36.745144 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:36.756934 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:36.756992 (XEN) Apr 26 17:09:36.757033 (XEN) ESR_EL2: 000000005a000ea1 Apr 26 17:09:36.757077 (XEN) HPFAR_EL2: 0000000000030300 Apr 26 17:09:36.768933 (XEN) FAR_EL2: ffff80000b010100 Apr 26 17:09:36.768992 (XEN) Apr 26 17:09:36.769032 (XEN) Xen stack trace from sp=0000800ffde87e60: Apr 26 17:09:36.769079 (XEN) 0000800ffde87e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:36.780938 (XEN) 0000000000000047 0000000000000000 0000000000000000 0000000000010107 Apr 26 17:09:36.781001 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.792923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.793004 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.804947 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.816936 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.816998 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.828924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.828986 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.840940 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.841002 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.852936 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:36.864922 (XEN) Xen call trace: Apr 26 17:09:36.864980 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:36.865034 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:36.876936 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:36.876999 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:36.888858 (XEN) Apr 26 17:09:36.888911 (XEN) *** Dumping CPU72 host state: *** Apr 26 17:09:36.888958 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:36.889007 (XEN) CPU: 72 Apr 26 17:09:36.900790 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:36.900790 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:36.900790 (XEN) SP: 0000800ffde1fe60 Apr 26 17:09:36.912786 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:36.912786 (XEN) X0: 0000000000000000 X1: 0000760ffdb4a000 X2: 0000800ffde8a078 Apr 26 17:09:36.924787 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:36.924787 (XEN) X6: 00000a00003825c8 X7: 0000800ffdf0bd90 X8: 0000000000000012 Apr 26 17:09:36.936783 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:36.936783 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:36.948783 (XEN) X15: ffff0000303d0f0c X16: ffff80000929f0b8 X17: 0000000000000000 Apr 26 17:09:36.948783 (XEN) X18: ffff80000daabc58 X19: 00000a00003825d0 X20: 0000000000000048 Apr 26 17:09:36.960788 (XEN) X21: 00000a0000347880 X22: 0000000000000100 X23: 0000000000000048 Apr 26 17:09:36.972779 (XEN) X24: 0000000000000048 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:36.972779 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde1fe60 Apr 26 17:09:36.984784 (XEN) Apr 26 17:09:36.984784 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:36.984784 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:36.984784 (XEN) Apr 26 17:09:36.984784 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:36.996784 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:36.996784 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:36.996784 (XEN) Apr 26 17:09:36.996784 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:36.996784 (XEN) HPFAR_EL2: 0000008010805d00 Apr 26 17:09:37.008772 (XEN) FAR_EL2: ffff80000add0100 Apr 26 17:09:37.008772 (XEN) Apr 26 17:09:37.008772 (XEN) Xen stack trace from sp=0000800ffde1fe60: Apr 26 17:09:37.008772 (XEN) 0000800ffde1fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:37.020791 (XEN) 0000000000000048 0000000000000000 0000000000000000 0000000000010108 Apr 26 17:09:37.020791 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.032782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.044785 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.044785 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.056782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.056782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.068782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.068782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.080793 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.092783 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.092783 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.104784 (XEN) Xen call trace: Apr 26 17:09:37.104784 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:37.104784 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:37.116785 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:37.116785 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:37.128780 (XEN) Apr 26 17:09:37.128780 (XEN) *** Dumping CPU73 host state: *** Apr 26 17:09:37.128780 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:37.140790 (XEN) CPU: 73 Apr 26 17:09:37.140790 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:37.140790 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:37.140790 (XEN) SP: 0000800ffde0fe60 Apr 26 17:09:37.152771 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:37.152771 (XEN) X0: 0000000000000000 X1: 0000760ffdad6000 X2: 0000800ffde16078 Apr 26 17:09:37.164780 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:37.164780 (XEN) X6: 00000a00003825c8 X7: 0000800ffde89280 X8: 0000000000000012 Apr 26 17:09:37.176781 (XEN) X9: 0000000000000000 X10: ffff800009d8ac08 X11: 000000000000012f Apr 26 17:09:37.176781 (XEN) X12: 000000000000038d X13: ffff800009d32c08 X14: 0000000000000000 Apr 26 17:09:37.188783 (XEN) X15: ffff80000800b7e0 X16: 000000000000001d X17: 0000000000000000 Apr 26 17:09:37.188783 (XEN) X18: 0000000000000006 X19: 00000a00003825d0 X20: 0000000000000049 Apr 26 17:09:37.200787 (XEN) X21: 00000a0000347900 X22: 0000000000000200 X23: 0000000000000049 Apr 26 17:09:37.212771 (XEN) X24: 0000000000000049 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:37.212771 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde0fe60 Apr 26 17:09:37.224781 (XEN) Apr 26 17:09:37.224781 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:37.224781 (XEN) VTTBR_EL2: 00020107202e9000 Apr 26 17:09:37.224781 (XEN) Apr 26 17:09:37.224781 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:37.236783 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:37.236783 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:37.236783 (XEN) Apr 26 17:09:37.236783 (XEN) ESR_EL2: 000000005a000ea1 Apr 26 17:09:37.236783 (XEN) HPFAR_EL2: 0000000000030300 Apr 26 17:09:37.248780 (XEN) FAR_EL2: ffff80000b010100 Apr 26 17:09:37.248780 (XEN) Apr 26 17:09:37.248780 (XEN) Xen stack trace from sp=0000800ffde0fe60: Apr 26 17:09:37.248780 (XEN) 0000800ffde0fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:37.260776 (XEN) 0000000000000049 0000000000000000 0000000000000000 0000000000010109 Apr 26 17:09:37.272788 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.272788 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.284784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.284784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.296779 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.296779 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.308782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.308782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.320792 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.332784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.332784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.344785 (XEN) Xen call trace: Apr 26 17:09:37.344785 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:37.344785 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:37.356784 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:37.356784 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:37.368774 (XEN) Apr 26 17:09:37.368774 (XEN) *** Dumping CPU74 host state: *** Apr 26 17:09:37.368774 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:37.380791 (XEN) CPU: 74 Apr 26 17:09:37.380791 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:37.380791 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:37.380791 (XEN) SP: 0000800ffde07e60 Apr 26 17:09:37.392785 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:37.392785 (XEN) X0: 0000000000000000 X1: 0000760ffdad4000 X2: 0000800ffde14078 Apr 26 17:09:37.404786 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:37.404786 (XEN) X6: 00000a00003825c8 X7: 0000800ffde89740 X8: 0000000000000012 Apr 26 17:09:37.416784 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:37.416784 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:37.428783 (XEN) X15: fffffc0000d60f40 X16: ffff80000929f0b8 X17: 0000000000000000 Apr 26 17:09:37.440790 (XEN) X18: ffff80000db6bc58 X19: 00000a00003825d0 X20: 000000000000004a Apr 26 17:09:37.440790 (XEN) X21: 00000a0000347980 X22: 0000000000000400 X23: 000000000000004a Apr 26 17:09:37.452784 (XEN) X24: 000000000000004a X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:37.452784 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde07e60 Apr 26 17:09:37.464773 (XEN) Apr 26 17:09:37.464773 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:37.464773 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:37.464773 (XEN) Apr 26 17:09:37.464773 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:37.476783 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:37.476783 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:37.476783 (XEN) Apr 26 17:09:37.476783 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:37.488781 (XEN) HPFAR_EL2: 0000009010801500 Apr 26 17:09:37.488781 (XEN) FAR_EL2: ffff80000b150100 Apr 26 17:09:37.488781 (XEN) Apr 26 17:09:37.488781 (XEN) Xen stack trace from sp=0000800ffde07e60: Apr 26 17:09:37.488781 (XEN) 0000800ffde07e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:37.500784 (XEN) 000000000000004a 0000000000000000 0000000000000000 000000000001010a Apr 26 17:09:37.512769 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.512769 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.524796 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.524796 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.536784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.536784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.548783 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.560792 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.560792 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.572782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.572782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.584783 (XEN) Xen call trace: Apr 26 17:09:37.584783 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:37.584783 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:37.596782 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:37.596782 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:37.608782 (XEN) Apr 26 17:09:37.608782 (XEN) *** Dumping CPU75 host state: *** Apr 26 17:09:37.608782 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:37.620796 (XEN) CPU: 75 Apr 26 17:09:37.620796 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:37.620796 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:37.632785 (XEN) SP: 0000800ffd99fe60 Apr 26 17:09:37.632785 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:37.632785 (XEN) X0: 0000000000000000 X1: 0000760ffdad0000 X2: 0000800ffde10078 Apr 26 17:09:37.644779 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:37.644779 (XEN) X6: 00000a00003825c8 X7: 0000800ffde89c00 X8: 0000000000000012 Apr 26 17:09:37.656927 (XEN) X9: 0000000000000000 X10: ffff800009d8ac08 X11: 000000000000012f Apr 26 17:09:37.668780 (XEN) X12: 000000000000038d X13: ffff800009d32c08 X14: 0000000000000000 Apr 26 17:09:37.668780 (XEN) X15: ffff80000800b7e0 X16: 000000000000001d X17: 0000000000000000 Apr 26 17:09:37.680785 (XEN) X18: 0000000000000006 X19: 00000a00003825d0 X20: 000000000000004b Apr 26 17:09:37.680785 (XEN) X21: 00000a0000347a00 X22: 0000000000000800 X23: 000000000000004b Apr 26 17:09:37.692785 (XEN) X24: 000000000000004b X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:37.692785 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd99fe60 Apr 26 17:09:37.704787 (XEN) Apr 26 17:09:37.704787 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:37.704787 (XEN) VTTBR_EL2: 00020107fc6da000 Apr 26 17:09:37.704787 (XEN) Apr 26 17:09:37.704787 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:37.716771 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:37.716771 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:37.716771 (XEN) Apr 26 17:09:37.716771 (XEN) ESR_EL2: 000000005a000ea1 Apr 26 17:09:37.728784 (XEN) HPFAR_EL2: 0000000000030300 Apr 26 17:09:37.728784 (XEN) FAR_EL2: ffff80000b010100 Apr 26 17:09:37.728784 (XEN) Apr 26 17:09:37.728784 (XEN) Xen stack trace from sp=0000800ffd99fe60: Apr 26 17:09:37.740788 (XEN) 0000800ffd99fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:37.740788 (XEN) 000000000000004b 0000000000000000 0000000000000000 000000000001010b Apr 26 17:09:37.752779 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.752779 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.764774 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.764774 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.776784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.776784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.788779 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.800777 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.800777 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.812781 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.812781 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.824786 (XEN) Xen call trace: Apr 26 17:09:37.824786 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:37.836785 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:37.836785 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:37.848906 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:37.848971 (XEN) Apr 26 17:09:37.849011 (XEN) *** Dumping CPU76 host state: *** Apr 26 17:09:37.849056 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:37.860781 (XEN) CPU: 76 Apr 26 17:09:37.860781 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:37.860781 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:37.872776 (XEN) SP: 0000800ffd98fe60 Apr 26 17:09:37.872776 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:37.872776 (XEN) X0: 0000000000000000 X1: 0000760ffd656000 X2: 0000800ffd996078 Apr 26 17:09:37.884786 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:37.884786 (XEN) X6: 00000a00003825c8 X7: 0000800ffd994150 X8: 0000000000000012 Apr 26 17:09:37.896784 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:37.908783 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:37.908783 (XEN) X15: 0000000000000001 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:37.920790 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 000000000000004c Apr 26 17:09:37.920790 (XEN) X21: 00000a0000347a80 X22: 0000000000001000 X23: 000000000000004c Apr 26 17:09:37.932778 (XEN) X24: 000000000000004c X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:37.932778 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd98fe60 Apr 26 17:09:37.944778 (XEN) Apr 26 17:09:37.944778 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:37.944778 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:37.944778 (XEN) Apr 26 17:09:37.956778 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:37.956778 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:37.956778 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:37.956778 (XEN) Apr 26 17:09:37.956778 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:37.968772 (XEN) HPFAR_EL2: 0000009010802d00 Apr 26 17:09:37.968772 (XEN) FAR_EL2: ffff80000b2d0100 Apr 26 17:09:37.968772 (XEN) Apr 26 17:09:37.968772 (XEN) Xen stack trace from sp=0000800ffd98fe60: Apr 26 17:09:37.980952 (XEN) 0000800ffd98fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:37.981010 (XEN) 000000000000004c 0000000000000000 0000000000000000 000000000001010c Apr 26 17:09:37.992784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:37.992784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.004778 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.004778 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.016774 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.028784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.028784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.040789 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.040789 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.052783 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.052783 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.064781 (XEN) Xen call trace: Apr 26 17:09:38.064781 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:38.076784 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:38.076784 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:38.088782 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:38.088782 (XEN) Apr 26 17:09:38.088782 (XEN) *** Dumping CPU77 host state: *** Apr 26 17:09:38.088782 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:38.100788 (XEN) CPU: 77 Apr 26 17:09:38.100788 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:38.100788 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:38.112782 (XEN) SP: 0000800ffd987e60 Apr 26 17:09:38.112782 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:38.112782 (XEN) X0: 0000000000000000 X1: 0000760ffd652000 X2: 0000800ffd992078 Apr 26 17:09:38.124786 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:38.136783 (XEN) X6: 00000a00003825c8 X7: 0000800ffd994590 X8: 0000000000000012 Apr 26 17:09:38.136783 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:38.148773 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:38.148773 (XEN) X15: ffff00002667810c X16: ffff80000929f0b8 X17: 0000000000000000 Apr 26 17:09:38.160779 (XEN) X18: ffff80000d10bc58 X19: 00000a00003825d0 X20: 000000000000004d Apr 26 17:09:38.160779 (XEN) X21: 00000a0000347b00 X22: 0000000000002000 X23: 000000000000004d Apr 26 17:09:38.172784 (XEN) X24: 000000000000004d X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:38.172784 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd987e60 Apr 26 17:09:38.184786 (XEN) Apr 26 17:09:38.184786 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:38.184786 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:38.196782 (XEN) Apr 26 17:09:38.196782 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:38.196782 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:38.196782 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:38.196782 (XEN) Apr 26 17:09:38.196782 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:38.208778 (XEN) HPFAR_EL2: 0000000000030300 Apr 26 17:09:38.208778 (XEN) FAR_EL2: ffff80000b010100 Apr 26 17:09:38.208778 (XEN) Apr 26 17:09:38.208778 (XEN) Xen stack trace from sp=0000800ffd987e60: Apr 26 17:09:38.220781 (XEN) 0000800ffd987e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:38.220781 (XEN) 000000000000004d 0000000000000000 0000000000000000 000000000001010d Apr 26 17:09:38.232782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.232782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.244786 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.244786 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.256778 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.268782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.268782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.280790 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.280790 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.292780 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.292780 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.304775 (XEN) Xen call trace: Apr 26 17:09:38.304775 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:38.316784 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:38.316784 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:38.328785 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:38.328785 (XEN) Apr 26 17:09:38.328785 (XEN) *** Dumping CPU78 host state: *** Apr 26 17:09:38.328785 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:38.340786 (XEN) CPU: 78 Apr 26 17:09:38.340786 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:38.352782 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:38.352782 (XEN) SP: 0000800ffd937e60 Apr 26 17:09:38.352782 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:38.352782 (XEN) X0: 0000000000000000 X1: 0000760ffd5fe000 X2: 0000800ffd93e078 Apr 26 17:09:38.364780 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:38.376782 (XEN) X6: 00000a00003825c8 X7: 0000800ffd994a50 X8: 0000000000000012 Apr 26 17:09:38.376782 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:38.388780 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:38.388780 (XEN) X15: ffff000033b7400c X16: ffff80000929f0b8 X17: 0000000000000000 Apr 26 17:09:38.400787 (XEN) X18: ffff80000d20bc58 X19: 00000a00003825d0 X20: 000000000000004e Apr 26 17:09:38.400787 (XEN) X21: 00000a0000347b80 X22: 0000000000004000 X23: 000000000000004e Apr 26 17:09:38.412784 (XEN) X24: 000000000000004e X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:38.424783 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd937e60 Apr 26 17:09:38.424783 (XEN) Apr 26 17:09:38.424783 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:38.424783 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:38.436778 (XEN) Apr 26 17:09:38.436778 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:38.436778 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:38.436778 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:38.436778 (XEN) Apr 26 17:09:38.448778 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:38.448778 (XEN) HPFAR_EL2: 0000009010804500 Apr 26 17:09:38.448778 (XEN) FAR_EL2: ffff80000b450100 Apr 26 17:09:38.448778 (XEN) Apr 26 17:09:38.448778 (XEN) Xen stack trace from sp=0000800ffd937e60: Apr 26 17:09:38.460785 (XEN) 0000800ffd937e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:38.460785 (XEN) 000000000000004e 0000000000000000 0000000000000000 000000000001010e Apr 26 17:09:38.472782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.472782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.484785 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.496785 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.496785 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.508781 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.508781 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.520784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.520784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.532782 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.544781 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.544781 (XEN) Xen call trace: Apr 26 17:09:38.544781 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:38.556786 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:38.556786 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:38.568781 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:38.568781 (XEN) Apr 26 17:09:38.568781 (XEN) *** Dumping CPU79 host state: *** Apr 26 17:09:38.568781 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:38.580785 (XEN) CPU: 79 Apr 26 17:09:38.580785 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:38.592783 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:38.592783 (XEN) SP: 0000800ffd92fe60 Apr 26 17:09:38.592783 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:38.604786 (XEN) X0: 0000000000000000 X1: 0000760ffd5fc000 X2: 0000800ffd93c078 Apr 26 17:09:38.604786 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:38.616783 (XEN) X6: 00000a00003825c8 X7: 0000800ffd93a010 X8: 0000000000000012 Apr 26 17:09:38.616783 (XEN) X9: 0000000000000000 X10: ffff800009d8ac08 X11: 000000000000012f Apr 26 17:09:38.628781 (XEN) X12: 000000000000038d X13: ffff800009d32c08 X14: 0000000000000000 Apr 26 17:09:38.628781 (XEN) X15: ffff80000800b7e0 X16: 000000000000001d X17: 0000000000000000 Apr 26 17:09:38.640788 (XEN) X18: 0000000000000006 X19: 00000a00003825d0 X20: 000000000000004f Apr 26 17:09:38.640788 (XEN) X21: 00000a0000347c00 X22: 0000000000008000 X23: 000000000000004f Apr 26 17:09:38.652856 (XEN) X24: 000000000000004f X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:38.664949 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd92fe60 Apr 26 17:09:38.665017 (XEN) Apr 26 17:09:38.665057 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:38.665100 (XEN) VTTBR_EL2: 00020107221f4000 Apr 26 17:09:38.676940 (XEN) Apr 26 17:09:38.676993 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:38.677038 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:38.677081 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:38.688926 (XEN) Apr 26 17:09:38.688980 (XEN) ESR_EL2: 000000005a000ea1 Apr 26 17:09:38.689025 (XEN) HPFAR_EL2: 0000000000030300 Apr 26 17:09:38.689068 (XEN) FAR_EL2: ffff80000b010100 Apr 26 17:09:38.689111 (XEN) Apr 26 17:09:38.689149 (XEN) Xen stack trace from sp=0000800ffd92fe60: Apr 26 17:09:38.700934 (XEN) 0000800ffd92fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:38.700997 (XEN) 000000000000004f 0000000000000000 0000000000000000 000000000001010f Apr 26 17:09:38.712927 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.712989 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.724945 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.736931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.736994 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.748924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.748987 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.760923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.760985 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.772941 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.784897 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.784959 (XEN) Xen call trace: Apr 26 17:09:38.785002 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:38.796932 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:38.796997 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:38.808943 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:38.809001 (XEN) Apr 26 17:09:38.809041 (XEN) *** Dumping CPU80 host state: *** Apr 26 17:09:38.820927 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:38.821009 (XEN) CPU: 80 Apr 26 17:09:38.821054 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:38.832935 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:38.832993 (XEN) SP: 0000800ffd8bfe60 Apr 26 17:09:38.833037 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:38.844924 (XEN) X0: 0000000000000000 X1: 0000760ffd5f8000 X2: 0000800ffd938078 Apr 26 17:09:38.844988 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:38.856928 (XEN) X6: 00000a00003825c8 X7: 0000800ffd93a410 X8: 0000000000000012 Apr 26 17:09:38.856991 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:38.868926 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:38.868988 (XEN) X15: 0000000000000003 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:38.880942 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000050 Apr 26 17:09:38.892924 (XEN) X21: 00000a0000347c80 X22: 0000000000010000 X23: 0000000000000050 Apr 26 17:09:38.892987 (XEN) X24: 0000000000000050 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:38.904928 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd8bfe60 Apr 26 17:09:38.904992 (XEN) Apr 26 17:09:38.905032 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:38.916920 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:38.916978 (XEN) Apr 26 17:09:38.917018 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:38.917062 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:38.917104 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:38.928929 (XEN) Apr 26 17:09:38.928982 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:38.929026 (XEN) HPFAR_EL2: 0000009010805f00 Apr 26 17:09:38.929070 (XEN) FAR_EL2: ffff80000b5f0100 Apr 26 17:09:38.929112 (XEN) Apr 26 17:09:38.940925 (XEN) Xen stack trace from sp=0000800ffd8bfe60: Apr 26 17:09:38.940985 (XEN) 0000800ffd8bfe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:38.941036 (XEN) 0000000000000050 0000000000000000 0000000000000000 0000000000010200 Apr 26 17:09:38.952937 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.964918 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.964980 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.976935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.976997 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.988942 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:38.989004 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.000934 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.012912 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.012974 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.024947 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.025009 (XEN) Xen call trace: Apr 26 17:09:39.025052 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:39.036932 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:39.036996 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:39.048931 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:39.048990 (XEN) Apr 26 17:09:39.049030 (XEN) *** Dumping CPU81 host state: *** Apr 26 17:09:39.060924 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:39.060987 (XEN) CPU: 81 Apr 26 17:09:39.061029 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:39.072953 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:39.073049 (XEN) SP: 0000800ffd8b7e60 Apr 26 17:09:39.073098 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:39.084930 (XEN) X0: 0000000000000000 X1: 0000760ffd5e4000 X2: 0000800ffd924078 Apr 26 17:09:39.084993 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:39.096928 (XEN) X6: 00000a00003825c8 X7: 0000800ffd93a8d0 X8: 0000000000000012 Apr 26 17:09:39.096991 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:39.108930 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:39.108992 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:39.120938 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000051 Apr 26 17:09:39.132911 (XEN) X21: 00000a0000347d00 X22: 0000000000020000 X23: 0000000000000051 Apr 26 17:09:39.132974 (XEN) X24: 0000000000000051 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:39.144922 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd8b7e60 Apr 26 17:09:39.144986 (XEN) Apr 26 17:09:39.145026 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:39.156932 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:39.156990 (XEN) Apr 26 17:09:39.157030 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:39.157073 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:39.157115 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:39.168936 (XEN) Apr 26 17:09:39.168988 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:39.169032 (XEN) HPFAR_EL2: 0000008010800b00 Apr 26 17:09:39.169075 (XEN) FAR_EL2: ffff80000a8b0100 Apr 26 17:09:39.180927 (XEN) Apr 26 17:09:39.180980 (XEN) Xen stack trace from sp=0000800ffd8b7e60: Apr 26 17:09:39.181028 (XEN) 0000800ffd8b7e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:39.192925 (XEN) 0000000000000051 0000000000000000 0000000000000000 0000000000010201 Apr 26 17:09:39.192988 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.204924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.204987 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.216916 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.216979 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.228934 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.228996 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.240927 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.252923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.252986 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.264916 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.265017 (XEN) Xen call trace: Apr 26 17:09:39.265062 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:39.276948 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:39.288924 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:39.288987 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:39.289033 (XEN) Apr 26 17:09:39.289072 (XEN) *** Dumping CPU82 host state: *** Apr 26 17:09:39.300918 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:39.300981 (XEN) CPU: 82 Apr 26 17:09:39.301022 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:39.312943 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:39.313000 (XEN) SP: 0000800ffd8afe60 Apr 26 17:09:39.313043 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:39.324945 (XEN) X0: 0000000000000000 X1: 0000760ffd5e2000 X2: 0000800ffd922078 Apr 26 17:09:39.325027 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:39.336934 (XEN) X6: 00000a00003825c8 X7: 0000800ffd93ad90 X8: 0000000000000012 Apr 26 17:09:39.336998 (XEN) X9: 0000000000000000 X10: 00000000000009d0 X11: 0000000000000000 Apr 26 17:09:39.348938 (XEN) X12: 0000000000000001 X13: 0000000000000386 X14: 0000000000000386 Apr 26 17:09:39.360932 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:39.360994 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000052 Apr 26 17:09:39.372934 (XEN) X21: 00000a0000347d80 X22: 0000000000040000 X23: 0000000000000052 Apr 26 17:09:39.372997 (XEN) X24: 0000000000000052 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:39.384923 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd8afe60 Apr 26 17:09:39.384986 (XEN) Apr 26 17:09:39.385026 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:39.396926 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:39.396984 (XEN) Apr 26 17:09:39.397024 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:39.397067 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:39.408921 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:39.408980 (XEN) Apr 26 17:09:39.409020 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:39.409063 (XEN) HPFAR_EL2: 0000008010801700 Apr 26 17:09:39.409106 (XEN) FAR_EL2: ffff80000a970100 Apr 26 17:09:39.420932 (XEN) Apr 26 17:09:39.420985 (XEN) Xen stack trace from sp=0000800ffd8afe60: Apr 26 17:09:39.421032 (XEN) 0000800ffd8afe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:39.432922 (XEN) 0000000000000052 0000000000000000 0000000000000000 0000000000010202 Apr 26 17:09:39.432985 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.444939 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.445001 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.456930 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.456992 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.468922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.480945 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.481007 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.492939 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.493001 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.504941 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.505004 (XEN) Xen call trace: Apr 26 17:09:39.516918 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:39.516983 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:39.528937 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:39.529000 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:39.529046 (XEN) Apr 26 17:09:39.529085 (XEN) *** Dumping CPU83 host state: *** Apr 26 17:09:39.540928 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:39.540991 (XEN) CPU: 83 Apr 26 17:09:39.541033 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:39.552934 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:39.552991 (XEN) SP: 0000800ffd83fe60 Apr 26 17:09:39.553035 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:39.564933 (XEN) X0: 0000000000000000 X1: 0000760ffd566000 X2: 0000800ffd8a6078 Apr 26 17:09:39.564996 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:39.576935 (XEN) X6: 00000a00003825c8 X7: 0000800ffd920280 X8: 0000000000000012 Apr 26 17:09:39.588945 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Apr 26 17:09:39.589009 (XEN) X12: 0000000000000001 X13: 0000000000000046 X14: 0000000000000046 Apr 26 17:09:39.600923 (XEN) X15: ffff0000289e070c X16: ffff80000929f0b8 X17: 0000000000000000 Apr 26 17:09:39.600987 (XEN) X18: ffff80000cc43c58 X19: 00000a00003825d0 X20: 0000000000000053 Apr 26 17:09:39.612927 (XEN) X21: 00000a0000347e00 X22: 0000000000080000 X23: 0000000000000053 Apr 26 17:09:39.612990 (XEN) X24: 0000000000000053 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:39.624932 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd83fe60 Apr 26 17:09:39.624996 (XEN) Apr 26 17:09:39.625036 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:39.636925 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:39.636983 (XEN) Apr 26 17:09:39.637022 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:39.637065 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:39.648916 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:39.648974 (XEN) Apr 26 17:09:39.649013 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:39.649056 (XEN) HPFAR_EL2: 0000008010000200 Apr 26 17:09:39.649098 (XEN) FAR_EL2: ffff80000a380090 Apr 26 17:09:39.660946 (XEN) Apr 26 17:09:39.660998 (XEN) Xen stack trace from sp=0000800ffd83fe60: Apr 26 17:09:39.661044 (XEN) 0000800ffd83fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:39.672922 (XEN) 0000000000000053 0000000000000000 0000000000000000 0000000000010203 Apr 26 17:09:39.672985 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.684941 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.685003 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.696937 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.696999 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.708932 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.720935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.720997 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.732930 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.732992 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.744933 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.744994 (XEN) Xen call trace: Apr 26 17:09:39.756932 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:39.756997 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:39.768896 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:39.768958 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:39.769004 (XEN) Apr 26 17:09:39.780934 (XEN) *** Dumping CPU84 host state: *** Apr 26 17:09:39.780993 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:39.781042 (XEN) CPU: 84 Apr 26 17:09:39.781082 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:39.792938 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:39.792995 (XEN) SP: 0000800ffd837e60 Apr 26 17:09:39.793038 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:39.808839 (XEN) X0: 0000000000000000 X1: 0000760ffd562000 X2: 0000800ffd8a2078 Apr 26 17:09:39.808839 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:39.820947 (XEN) X6: 00000a00003825c8 X7: 0000800ffd920740 X8: 0000000000000012 Apr 26 17:09:39.821015 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000003 Apr 26 17:09:39.832905 (XEN) X12: 0000000000000001 X13: 00000000000002c7 X14: 00000000000002c7 Apr 26 17:09:39.832988 (XEN) X15: 528005a317ffffac X16: a9ba7bfd17ffffaa X17: f947ec42b0000182 Apr 26 17:09:39.844934 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000054 Apr 26 17:09:39.844996 (XEN) X21: 00000a0000347e80 X22: 0000000000100000 X23: 0000000000000054 Apr 26 17:09:39.856935 (XEN) X24: 0000000000000054 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:39.868922 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd837e60 Apr 26 17:09:39.868985 (XEN) Apr 26 17:09:39.869026 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:39.869069 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:39.880948 (XEN) Apr 26 17:09:39.881000 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:39.881044 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:39.881086 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:39.892926 (XEN) Apr 26 17:09:39.892978 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:39.893023 (XEN) HPFAR_EL2: 0000008010802f00 Apr 26 17:09:39.893065 (XEN) FAR_EL2: ffff80000aaf0100 Apr 26 17:09:39.893107 (XEN) Apr 26 17:09:39.893145 (XEN) Xen stack trace from sp=0000800ffd837e60: Apr 26 17:09:39.904938 (XEN) 0000800ffd837e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:39.905001 (XEN) 0000000000000054 0000000000000000 0000000000000000 0000000000010204 Apr 26 17:09:39.916935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.928925 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.928987 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.940928 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.940990 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.952928 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.952989 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.964933 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.964995 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.976941 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.988936 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:39.988998 (XEN) Xen call trace: Apr 26 17:09:39.989040 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:40.000939 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:40.001003 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:40.012932 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:40.012991 (XEN) Apr 26 17:09:40.013031 (XEN) *** Dumping CPU85 host state: *** Apr 26 17:09:40.024942 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:40.025005 (XEN) CPU: 85 Apr 26 17:09:40.025046 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:40.036933 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:40.036990 (XEN) SP: 0000800ffd827e60 Apr 26 17:09:40.037033 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:40.048931 (XEN) X0: 0000000000000000 X1: 0000760ffd560000 X2: 0000800ffd8a0078 Apr 26 17:09:40.048994 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:40.060939 (XEN) X6: 00000a00003825c8 X7: 0000800ffd920c00 X8: 0000000000000012 Apr 26 17:09:40.061003 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Apr 26 17:09:40.072931 (XEN) X12: 0000000000000001 X13: 00000000000003ee X14: 00000000000003ee Apr 26 17:09:40.072994 (XEN) X15: 00003d0900000000 X16: ffff80000929f0b8 X17: 0000000000000000 Apr 26 17:09:40.084938 (XEN) X18: ffff80000cf4bc58 X19: 00000a00003825d0 X20: 0000000000000055 Apr 26 17:09:40.096940 (XEN) X21: 00000a0000347f00 X22: 0000000000200000 X23: 0000000000000055 Apr 26 17:09:40.097005 (XEN) X24: 0000000000000055 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:40.108933 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd827e60 Apr 26 17:09:40.108996 (XEN) Apr 26 17:09:40.109035 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:40.120929 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:40.120987 (XEN) Apr 26 17:09:40.121027 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:40.121069 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:40.121111 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:40.132920 (XEN) Apr 26 17:09:40.132972 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:40.133017 (XEN) HPFAR_EL2: 0000008010803b00 Apr 26 17:09:40.133059 (XEN) FAR_EL2: ffff80000abb0100 Apr 26 17:09:40.133101 (XEN) Apr 26 17:09:40.144923 (XEN) Xen stack trace from sp=0000800ffd827e60: Apr 26 17:09:40.144984 (XEN) 0000800ffd827e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:40.145034 (XEN) 0000000000000055 0000000000000000 0000000000000000 0000000000010205 Apr 26 17:09:40.156945 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.168937 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.168999 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.180933 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.180995 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.192934 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.192996 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.204933 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.216931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.216993 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.228937 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.228999 (XEN) Xen call trace: Apr 26 17:09:40.229042 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:40.240944 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:40.252927 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:40.252990 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:40.253036 (XEN) Apr 26 17:09:40.253074 (XEN) *** Dumping CPU86 host state: *** Apr 26 17:09:40.264926 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:40.264989 (XEN) CPU: 86 Apr 26 17:09:40.265030 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:40.276945 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:40.277002 (XEN) SP: 0000800ffb7bfe60 Apr 26 17:09:40.277045 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:40.288924 (XEN) X0: 0000000000000000 X1: 0000760ffd4ec000 X2: 0000800ffd82c078 Apr 26 17:09:40.288987 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:40.300929 (XEN) X6: 00000a00003825c8 X7: 0000800ffd82b150 X8: 0000000000000012 Apr 26 17:09:40.300992 (XEN) X9: 0000000000000080 X10: 0000000000000000 X11: 00000000000000d3 Apr 26 17:09:40.312944 (XEN) X12: 0000000000000000 X13: 0000000000000327 X14: ffff80000cfe3c98 Apr 26 17:09:40.324924 (XEN) X15: 0000fffff7766d88 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:40.324987 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000056 Apr 26 17:09:40.336922 (XEN) X21: 00000a0000347f80 X22: 0000000000400000 X23: 0000000000000056 Apr 26 17:09:40.336985 (XEN) X24: 0000000000000056 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:40.348958 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb7bfe60 Apr 26 17:09:40.349023 (XEN) Apr 26 17:09:40.349062 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:40.360933 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:40.360991 (XEN) Apr 26 17:09:40.361031 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:40.361074 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:40.361116 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:40.372931 (XEN) Apr 26 17:09:40.372984 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:40.373028 (XEN) HPFAR_EL2: 0000008010804700 Apr 26 17:09:40.373071 (XEN) FAR_EL2: ffff80000ac70100 Apr 26 17:09:40.384933 (XEN) Apr 26 17:09:40.384986 (XEN) Xen stack trace from sp=0000800ffb7bfe60: Apr 26 17:09:40.385033 (XEN) 0000800ffb7bfe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:40.396920 (XEN) 0000000000000056 0000000000000000 0000000000000000 0000000000010206 Apr 26 17:09:40.396982 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.408924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.408986 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.420932 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.420994 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.432930 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.432991 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.444938 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.456922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.456983 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.468918 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.468980 (XEN) Xen call trace: Apr 26 17:09:40.469022 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:40.480957 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:40.492929 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:40.492991 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:40.493036 (XEN) Apr 26 17:09:40.493074 (XEN) *** Dumping CPU87 host state: *** Apr 26 17:09:40.504931 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:40.504994 (XEN) CPU: 87 Apr 26 17:09:40.505035 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:40.516922 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:40.516979 (XEN) SP: 0000800ffb7b7e60 Apr 26 17:09:40.517022 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:40.528945 (XEN) X0: 0000000000000000 X1: 0000760ffd4e8000 X2: 0000800ffd828078 Apr 26 17:09:40.529008 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:40.540939 (XEN) X6: 00000a00003825c8 X7: 0000800ffd82b590 X8: 0000000000000012 Apr 26 17:09:40.541002 (XEN) X9: 0000000000000080 X10: 0000000000000000 X11: 0000000000000039 Apr 26 17:09:40.552936 (XEN) X12: 0000000000000000 X13: 000000000000028d X14: 000000000000031b Apr 26 17:09:40.564924 (XEN) X15: 0000000000000003 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:40.564986 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000057 Apr 26 17:09:40.576935 (XEN) X21: 00000a0000348000 X22: 0000000000800000 X23: 0000000000000057 Apr 26 17:09:40.576997 (XEN) X24: 0000000000000057 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:40.588930 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb7b7e60 Apr 26 17:09:40.588993 (XEN) Apr 26 17:09:40.589053 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:40.600922 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:40.600980 (XEN) Apr 26 17:09:40.601020 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:40.601063 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:40.612931 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:40.612988 (XEN) Apr 26 17:09:40.613028 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:40.613070 (XEN) HPFAR_EL2: 0000008010805300 Apr 26 17:09:40.613113 (XEN) FAR_EL2: ffff80000ad30100 Apr 26 17:09:40.624930 (XEN) Apr 26 17:09:40.624982 (XEN) Xen stack trace from sp=0000800ffb7b7e60: Apr 26 17:09:40.625029 (XEN) 0000800ffb7b7e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:40.636926 (XEN) 0000000000000057 0000000000000000 0000000000000000 0000000000010207 Apr 26 17:09:40.636988 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.648923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.648985 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.660942 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.661004 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.672932 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.684926 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.684989 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.696929 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.696991 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.708926 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.708988 (XEN) Xen call trace: Apr 26 17:09:40.720923 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:40.720989 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:40.732934 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:40.732996 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:40.733042 (XEN) Apr 26 17:09:40.733080 (XEN) *** Dumping CPU88 host state: *** Apr 26 17:09:40.744931 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:40.744994 (XEN) CPU: 88 Apr 26 17:09:40.745035 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:40.756931 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:40.756988 (XEN) SP: 0000800ffb7a7e60 Apr 26 17:09:40.757031 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:40.768922 (XEN) X0: 0000000000000000 X1: 0000760ffb46e000 X2: 0000800ffb7ae078 Apr 26 17:09:40.768986 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:40.780949 (XEN) X6: 00000a00003825c8 X7: 0000800ffd82ba50 X8: 0000000000000012 Apr 26 17:09:40.792926 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:40.792988 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:40.804922 (XEN) X15: ffff0000323f740c X16: ffff80000929f0b8 X17: 0000000000000000 Apr 26 17:09:40.804986 (XEN) X18: ffff80000d0d3c58 X19: 00000a00003825d0 X20: 0000000000000058 Apr 26 17:09:40.816942 (XEN) X21: 00000a0000348080 X22: 0000000001000000 X23: 0000000000000058 Apr 26 17:09:40.817004 (XEN) X24: 0000000000000058 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:40.828931 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb7a7e60 Apr 26 17:09:40.828993 (XEN) Apr 26 17:09:40.840931 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:40.840990 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:40.841034 (XEN) Apr 26 17:09:40.841072 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:40.841133 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:40.852927 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:40.852985 (XEN) Apr 26 17:09:40.853025 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:40.853067 (XEN) HPFAR_EL2: 0000008010805f00 Apr 26 17:09:40.853109 (XEN) FAR_EL2: ffff80000adf0100 Apr 26 17:09:40.864926 (XEN) Apr 26 17:09:40.864979 (XEN) Xen stack trace from sp=0000800ffb7a7e60: Apr 26 17:09:40.865026 (XEN) 0000800ffb7a7e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:40.876936 (XEN) 0000000000000058 0000000000000000 0000000000000000 0000000000010208 Apr 26 17:09:40.876998 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.888864 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.888926 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.900781 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.912760 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.912760 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.924784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.924784 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.936783 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.936783 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.948779 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:40.948779 (XEN) Xen call trace: Apr 26 17:09:40.960783 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:40.960783 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:40.972770 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:40.972770 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:40.972770 (XEN) Apr 26 17:09:40.988791 (XEN) *** Dumping CPU89 host state: *** Apr 26 17:09:40.988791 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:40.988791 (XEN) CPU: 89 Apr 26 17:09:40.988791 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:40.996930 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:40.996991 (XEN) SP: 0000800ffb73fe60 Apr 26 17:09:40.997035 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:41.008936 (XEN) X0: 0000000000000000 X1: 0000760ffb46a000 X2: 0000800ffb7aa078 Apr 26 17:09:41.020930 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:41.020995 (XEN) X6: 00000a00003825c8 X7: 0000800ffb7a9010 X8: 0000000000000012 Apr 26 17:09:41.032925 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:41.032987 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:41.044928 (XEN) X15: 0000000000000001 X16: 0000000000000000 X17: ffff800033880000 Apr 26 17:09:41.044991 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 0000000000000059 Apr 26 17:09:41.056929 (XEN) X21: 00000a0000348100 X22: 0000000002000000 X23: 0000000000000059 Apr 26 17:09:41.056992 (XEN) X24: 0000000000000059 X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:41.068927 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb73fe60 Apr 26 17:09:41.080940 (XEN) Apr 26 17:09:41.080993 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:41.081037 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:41.081081 (XEN) Apr 26 17:09:41.081119 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:41.081161 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:41.092931 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:41.092989 (XEN) Apr 26 17:09:41.093028 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:41.093090 (XEN) HPFAR_EL2: 0000009010800b00 Apr 26 17:09:41.104921 (XEN) FAR_EL2: ffff80000b0b0100 Apr 26 17:09:41.104979 (XEN) Apr 26 17:09:41.105018 (XEN) Xen stack trace from sp=0000800ffb73fe60: Apr 26 17:09:41.105063 (XEN) 0000800ffb73fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:41.116933 (XEN) 0000000000000059 0000000000000000 0000000000000000 0000000000010209 Apr 26 17:09:41.116995 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.128930 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.128992 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.140940 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.152918 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.152980 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.164935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.164997 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.176931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.176993 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.188930 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.200931 (XEN) Xen call trace: Apr 26 17:09:41.200988 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:41.201040 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:41.212932 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:41.212994 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:41.224923 (XEN) Apr 26 17:09:41.224975 (XEN) *** Dumping CPU90 host state: *** Apr 26 17:09:41.225021 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:41.225069 (XEN) CPU: 90 Apr 26 17:09:41.236930 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:41.236994 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:41.237038 (XEN) SP: 0000800ffb72fe60 Apr 26 17:09:41.248919 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:41.248985 (XEN) X0: 0000000000000000 X1: 0000760ffb3f6000 X2: 0000800ffb736078 Apr 26 17:09:41.260927 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:41.260991 (XEN) X6: 00000a00003825c8 X7: 0000800ffb7a9410 X8: 0000000000000012 Apr 26 17:09:41.272930 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:41.272993 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:41.284934 (XEN) X15: ffff00002a582c0c X16: ffff80000929f0b8 X17: 0000000000000000 Apr 26 17:09:41.284997 (XEN) X18: ffff80000d3cbc58 X19: 00000a00003825d0 X20: 000000000000005a Apr 26 17:09:41.296940 (XEN) X21: 00000a0000348180 X22: 0000000004000000 X23: 000000000000005a Apr 26 17:09:41.297003 (XEN) X24: 000000000000005a X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:41.308927 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb72fe60 Apr 26 17:09:41.320944 (XEN) Apr 26 17:09:41.320997 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:41.321041 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:41.321083 (XEN) Apr 26 17:09:41.321121 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:41.321162 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:41.332932 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:41.332989 (XEN) Apr 26 17:09:41.333029 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:41.333071 (XEN) HPFAR_EL2: 0000009010801700 Apr 26 17:09:41.344928 (XEN) FAR_EL2: ffff80000b170100 Apr 26 17:09:41.344987 (XEN) Apr 26 17:09:41.345045 (XEN) Xen stack trace from sp=0000800ffb72fe60: Apr 26 17:09:41.345094 (XEN) 0000800ffb72fe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:41.356934 (XEN) 000000000000005a 0000000000000000 0000000000000000 000000000001020a Apr 26 17:09:41.356996 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.368936 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.380931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.380994 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.392927 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.392989 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.404924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.404986 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.416931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.416992 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.428935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.440924 (XEN) Xen call trace: Apr 26 17:09:41.440988 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:41.441040 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:41.452932 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:41.452994 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:41.464933 (XEN) Apr 26 17:09:41.464986 (XEN) *** Dumping CPU91 host state: *** Apr 26 17:09:41.465031 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:41.465079 (XEN) CPU: 91 Apr 26 17:09:41.476931 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:41.476995 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:41.477038 (XEN) SP: 0000800ffb727e60 Apr 26 17:09:41.488928 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:41.488992 (XEN) X0: 0000000000000000 X1: 0000760ffb3f4000 X2: 0000800ffb734078 Apr 26 17:09:41.500925 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:41.500996 (XEN) X6: 00000a00003825c8 X7: 0000800ffb7a98d0 X8: 0000000000000012 Apr 26 17:09:41.512924 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:41.512986 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:41.524888 (XEN) X15: ffff00002c1e460c X16: ffff80000929f0b8 X17: 0000000000000000 Apr 26 17:09:41.524951 (XEN) X18: ffff80000d38bc58 X19: 00000a00003825d0 X20: 000000000000005b Apr 26 17:09:41.536927 (XEN) X21: 00000a0000348200 X22: 0000000008000000 X23: 000000000000005b Apr 26 17:09:41.549194 (XEN) X24: 000000000000005b X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:41.549257 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb727e60 Apr 26 17:09:41.560674 (XEN) Apr 26 17:09:41.560674 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:41.560674 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:41.560674 (XEN) Apr 26 17:09:41.560674 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:41.572864 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:41.572925 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:41.572969 (XEN) Apr 26 17:09:41.573008 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:41.573050 (XEN) HPFAR_EL2: 0000009010802300 Apr 26 17:09:41.584897 (XEN) FAR_EL2: ffff80000b230100 Apr 26 17:09:41.584955 (XEN) Apr 26 17:09:41.584995 (XEN) Xen stack trace from sp=0000800ffb727e60: Apr 26 17:09:41.585040 (XEN) 0000800ffb727e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:41.596924 (XEN) 000000000000005b 0000000000000000 0000000000000000 000000000001020b Apr 26 17:09:41.597004 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.608929 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.620924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.620994 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.632924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.632986 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.644919 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.644981 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.656928 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.668931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.668994 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.680959 (XEN) Xen call trace: Apr 26 17:09:41.681016 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:41.681068 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:41.692938 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:41.692999 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:41.704933 (XEN) Apr 26 17:09:41.704986 (XEN) *** Dumping CPU92 host state: *** Apr 26 17:09:41.705033 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:41.716930 (XEN) CPU: 92 Apr 26 17:09:41.716984 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:41.717036 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:41.717078 (XEN) SP: 0000800ffb6bfe60 Apr 26 17:09:41.728929 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:41.728993 (XEN) X0: 0000000000000000 X1: 0000760ffb3f0000 X2: 0000800ffb730078 Apr 26 17:09:41.740931 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:41.741000 (XEN) X6: 00000a00003825c8 X7: 0000800ffb7a9d90 X8: 0000000000000012 Apr 26 17:09:41.752943 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:41.753005 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:41.764941 (XEN) X15: 0000000000000003 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:41.776927 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 000000000000005c Apr 26 17:09:41.776992 (XEN) X21: 00000a0000348280 X22: 0000000010000000 X23: 000000000000005c Apr 26 17:09:41.788919 (XEN) X24: 000000000000005c X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:41.788982 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb6bfe60 Apr 26 17:09:41.800940 (XEN) Apr 26 17:09:41.801000 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:41.801044 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:41.801087 (XEN) Apr 26 17:09:41.801125 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:41.812933 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:41.812991 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:41.813035 (XEN) Apr 26 17:09:41.813073 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:41.813115 (XEN) HPFAR_EL2: 0000009010802f00 Apr 26 17:09:41.824934 (XEN) FAR_EL2: ffff80000b2f0100 Apr 26 17:09:41.824991 (XEN) Apr 26 17:09:41.825030 (XEN) Xen stack trace from sp=0000800ffb6bfe60: Apr 26 17:09:41.825075 (XEN) 0000800ffb6bfe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:41.836936 (XEN) 000000000000005c 0000000000000000 0000000000000000 000000000001020c Apr 26 17:09:41.848903 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.848965 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.860947 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.861018 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.872930 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.872992 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.884936 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.884998 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.896933 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.908921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.908984 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:41.920929 (XEN) Xen call trace: Apr 26 17:09:41.920993 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:41.921047 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:41.932935 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:41.932996 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:41.944933 (XEN) Apr 26 17:09:41.944987 (XEN) *** Dumping CPU93 host state: *** Apr 26 17:09:41.945032 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:41.956930 (XEN) CPU: 93 Apr 26 17:09:41.956985 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:41.957037 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:41.957079 (XEN) SP: 0000800ffb6afe60 Apr 26 17:09:41.968935 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:41.969001 (XEN) X0: 0000000000000000 X1: 0000760ffb374000 X2: 0000800ffb6b4078 Apr 26 17:09:41.980934 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:41.981004 (XEN) X6: 00000a00003825c8 X7: 0000800ffb6b7280 X8: 0000000000000012 Apr 26 17:09:41.992945 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:41.993008 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:42.004937 (XEN) X15: 0000000000000001 X16: 0000000000000000 X17: 0000000000000000 Apr 26 17:09:42.016932 (XEN) X18: 0000000000000000 X19: 00000a00003825d0 X20: 000000000000005d Apr 26 17:09:42.016995 (XEN) X21: 00000a0000348300 X22: 0000000020000000 X23: 000000000000005d Apr 26 17:09:42.028931 (XEN) X24: 000000000000005d X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:42.028993 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb6afe60 Apr 26 17:09:42.040923 (XEN) Apr 26 17:09:42.040981 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:42.041026 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:42.041069 (XEN) Apr 26 17:09:42.041107 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:42.052929 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:42.052987 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:42.053031 (XEN) Apr 26 17:09:42.053069 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:42.064922 (XEN) HPFAR_EL2: 0000009010803b00 Apr 26 17:09:42.064981 (XEN) FAR_EL2: ffff80000b3b0100 Apr 26 17:09:42.065025 (XEN) Apr 26 17:09:42.065063 (XEN) Xen stack trace from sp=0000800ffb6afe60: Apr 26 17:09:42.065108 (XEN) 0000800ffb6afe70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:42.076946 (XEN) 000000000000005d 0000000000000000 0000000000000000 000000000001020d Apr 26 17:09:42.088940 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.089002 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.100923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.100993 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.112946 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.113010 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.124935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.136930 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.136992 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.148920 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.148982 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.160921 (XEN) Xen call trace: Apr 26 17:09:42.160986 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:42.172931 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:42.172996 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:42.173044 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:42.184932 (XEN) Apr 26 17:09:42.184985 (XEN) *** Dumping CPU94 host state: *** Apr 26 17:09:42.185030 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:42.196927 (XEN) CPU: 94 Apr 26 17:09:42.196981 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:42.197032 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:42.208924 (XEN) SP: 0000800ffb6a7e60 Apr 26 17:09:42.208981 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:42.209033 (XEN) X0: 0000000000000000 X1: 0000760ffb372000 X2: 0000800ffb6b2078 Apr 26 17:09:42.220931 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:42.221002 (XEN) X6: 00000a00003825c8 X7: 0000800ffb6b7740 X8: 0000000000000012 Apr 26 17:09:42.232939 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:42.244926 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:42.244990 (XEN) X15: 00000000da648c41 X16: 000000006e4c965a X17: ffff800009f15538 Apr 26 17:09:42.256929 (XEN) X18: ffff80001dd0bc38 X19: 00000a00003825d0 X20: 000000000000005e Apr 26 17:09:42.256992 (XEN) X21: 00000a0000348380 X22: 0000000040000000 X23: 000000000000005e Apr 26 17:09:42.268923 (XEN) X24: 000000000000005e X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:42.268985 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb6a7e60 Apr 26 17:09:42.280933 (XEN) Apr 26 17:09:42.280993 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:42.281038 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:42.281081 (XEN) Apr 26 17:09:42.292922 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:42.292981 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:42.293025 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:42.293067 (XEN) Apr 26 17:09:42.293105 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:42.304929 (XEN) HPFAR_EL2: 0000009010804700 Apr 26 17:09:42.304986 (XEN) FAR_EL2: ffff80000b470100 Apr 26 17:09:42.305030 (XEN) Apr 26 17:09:42.305069 (XEN) Xen stack trace from sp=0000800ffb6a7e60: Apr 26 17:09:42.316930 (XEN) 0000800ffb6a7e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:42.316995 (XEN) 000000000000005e 0000000000000000 0000000000000000 000000000001020e Apr 26 17:09:42.328927 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.328989 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.340923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.340993 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.352935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.353015 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.364943 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.376903 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.376964 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.388935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.388997 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.400925 (XEN) Xen call trace: Apr 26 17:09:42.400989 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:42.412924 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:42.412989 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:42.424928 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:42.424987 (XEN) Apr 26 17:09:42.425027 (XEN) *** Dumping CPU95 host state: *** Apr 26 17:09:42.425071 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Apr 26 17:09:42.436933 (XEN) CPU: 95 Apr 26 17:09:42.436987 (XEN) PC: 00000a0000276fec arch/arm/domain.c#idle_loop+0x12c/0x194 Apr 26 17:09:42.437038 (XEN) LR: 00000a0000276fd0 Apr 26 17:09:42.448927 (XEN) SP: 0000800ffb657e60 Apr 26 17:09:42.448984 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Apr 26 17:09:42.449035 (XEN) X0: 0000000000000000 X1: 0000760ffb31e000 X2: 0000800ffb65e078 Apr 26 17:09:42.460935 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003825c0 Apr 26 17:09:42.461004 (XEN) X6: 00000a00003825c8 X7: 0000800ffb6b7c00 X8: 0000000000000012 Apr 26 17:09:42.472922 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Apr 26 17:09:42.484934 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Apr 26 17:09:42.484997 (XEN) X15: 00000000d1cad277 X16: 000000008181c4f8 X17: ffff800009f15538 Apr 26 17:09:42.496933 (XEN) X18: ffff80001dd3bc38 X19: 00000a00003825d0 X20: 000000000000005f Apr 26 17:09:42.496996 (XEN) X21: 00000a0000348400 X22: 0000000080000000 X23: 000000000000005f Apr 26 17:09:42.508930 (XEN) X24: 000000000000005f X25: 0000000000000000 X26: 0000000000000000 Apr 26 17:09:42.508992 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb657e60 Apr 26 17:09:42.520926 (XEN) Apr 26 17:09:42.520979 (XEN) VTCR_EL2: 00000000800d3590 Apr 26 17:09:42.521031 (XEN) VTTBR_EL2: 00010107fb649000 Apr 26 17:09:42.532925 (XEN) Apr 26 17:09:42.532977 (XEN) SCTLR_EL2: 0000000030cd183d Apr 26 17:09:42.533023 (XEN) HCR_EL2: 00000000807c663f Apr 26 17:09:42.533066 (XEN) TTBR0_EL2: 000001071e466000 Apr 26 17:09:42.533109 (XEN) Apr 26 17:09:42.533147 (XEN) ESR_EL2: 0000000007e00000 Apr 26 17:09:42.544936 (XEN) HPFAR_EL2: 0000009010805100 Apr 26 17:09:42.544993 (XEN) FAR_EL2: ffff80000b510100 Apr 26 17:09:42.545037 (XEN) Apr 26 17:09:42.545075 (XEN) Xen stack trace from sp=0000800ffb657e60: Apr 26 17:09:42.556934 (XEN) 0000800ffb657e70 00000a0000283a5c 00000a0000341420 00000a00003785a8 Apr 26 17:09:42.556997 (XEN) 000000000000005f 0000000000000000 0000000000000000 000000000001020f Apr 26 17:09:42.568935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.568997 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.580931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.580999 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.592931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.604922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.604984 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.616948 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.617012 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.628928 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.628989 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Apr 26 17:09:42.640922 (XEN) Xen call trace: Apr 26 17:09:42.640977 (XEN) [<00000a0000276fec>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Apr 26 17:09:42.652919 (XEN) [<00000a0000276fd0>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Apr 26 17:09:42.652984 (XEN) [<00000a0000283a5c>] start_secondary+0x218/0x21c Apr 26 17:09:42.664905 (XEN) [<00000a00003785a8>] 00000a00003785a8 Apr 26 17:09:42.664964 (XEN) Apr 26 17:09:42.665004 Apr 26 17:09:48.226355 (XEN) 'q' pressed -> dumping domain info (now = 1286490864370) Apr 26 17:09:48.248939 (XEN) General informati Apr 26 17:09:48.250431 on for domain 0: Apr 26 17:09:48.260771 (XEN) refcnt=3 dying=0 pause_count=0 Apr 26 17:09:48.260771 (XEN) nr_pages=131072 xenheap_pages=2 dirty_cpus={} max_pages=131072 Apr 26 17:09:48.260771 (XEN) handle=00000000-0000-0000-0000-000000000000 vm_assist=00000020 Apr 26 17:09:48.272864 (XEN) p2m mappings for domain 0 (vmid 1): Apr 26 17:09:48.272864 (XEN) 1G mappings: 4984 (shattered 3) Apr 26 17:09:48.284775 (XEN) 2M mappings: 1444448 (shattered 102) Apr 26 17:09:48.284775 (XEN) 4K mappings: 52240 Apr 26 17:09:48.284775 (XEN) Rangesets belonging to domain 0: Apr 26 17:09:48.296772 (XEN) Interrupts { 32, 38, 48-51 } Apr 26 17:09:48.296772 (XEN) I/O Memory { 802000000-808000000, 810000000-820000000, 838000000-844000000, 846000000-848002000, 849000000-849002000, 84a000000-84a002000, 84b000000-84b002000, 868000000-880000000, 88001f000-880058000, 881010000-883000010, 902000000-908000000, 910000000-920000000, 938000000-944000000, 946000000-948002000, 949000000-949002000, 94a000000-94a002000, 94b000000-94b002000, 968000000-980000000 } Apr 26 17:09:48.332786 (XEN) NODE affinity for domain 0: [0] Apr 26 17:09:48.332786 (XEN) VCPU information and callbacks for domain 0: Apr 26 17:09:48.332786 (XEN) UNIT0 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.344787 (XEN) VCPU0: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.344787 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.356783 (XEN) GICH_LRs (vcpu 0) mask=0 Apr 26 17:09:48.356783 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.356783 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.356783 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.356783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.356783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.368780 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.368780 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.368780 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.368780 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.368780 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.368780 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.380769 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.380769 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.380769 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.380769 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.380769 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.392784 (XEN) No periodic timer Apr 26 17:09:48.392784 (XEN) UNIT1 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.392784 (XEN) VCPU1: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.404773 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.404773 (XEN) GICH_LRs (vcpu 1) mask=0 Apr 26 17:09:48.404773 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.404773 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.416783 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.416783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.416783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.416783 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.416783 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.416783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.428780 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.428780 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.428780 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.428780 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.428780 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.428780 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.440771 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.440771 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.440771 (XEN) No periodic timer Apr 26 17:09:48.440771 (XEN) UNIT2 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.452787 (XEN) VCPU2: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.452787 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.452787 (XEN) GICH_LRs (vcpu 2) mask=0 Apr 26 17:09:48.464785 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.464785 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.464785 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.464785 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.464785 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.464785 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.476777 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.476777 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.476777 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.476777 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.476777 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.476777 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.488778 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.488778 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.488778 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.488778 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.488778 (XEN) No periodic timer Apr 26 17:09:48.488778 (XEN) UNIT3 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.500795 (XEN) VCPU3: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.500795 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.512782 (XEN) GICH_LRs (vcpu 3) mask=0 Apr 26 17:09:48.512782 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.512782 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.512782 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.512782 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.512782 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.524779 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.524779 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.524779 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.524779 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.524779 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.524779 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.536774 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.536774 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.536774 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.536774 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.536774 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.548784 (XEN) No periodic timer Apr 26 17:09:48.548784 (XEN) UNIT4 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.548784 (XEN) VCPU4: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.560782 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.560782 (XEN) GICH_LRs (vcpu 4) mask=0 Apr 26 17:09:48.560782 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.560782 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.572770 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.572770 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.572770 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.572770 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.572770 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.572770 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.584795 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.584795 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.584795 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.584795 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.584795 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.584795 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.596784 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.596784 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.596784 (XEN) No periodic timer Apr 26 17:09:48.596784 (XEN) UNIT5 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.596784 (XEN) VCPU5: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.608777 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.608777 (XEN) GICH_LRs (vcpu 5) mask=0 Apr 26 17:09:48.608777 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.620776 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.620776 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.620776 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.620776 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.620776 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.620776 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.632782 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.632782 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.632782 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.632782 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.632782 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.644785 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.644785 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.644785 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.644785 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.644785 (XEN) No periodic timer Apr 26 17:09:48.644785 (XEN) UNIT6 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.656770 (XEN) VCPU6: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.656770 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.668778 (XEN) GICH_LRs (vcpu 6) mask=0 Apr 26 17:09:48.668778 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.668778 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.668778 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.668778 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.680783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.680783 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.680783 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.680783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.680783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.680783 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.692783 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.692783 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.692783 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.692783 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.692783 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.692783 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.704787 (XEN) No periodic timer Apr 26 17:09:48.704787 (XEN) UNIT7 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.704787 (XEN) VCPU7: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.716782 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.716782 (XEN) GICH_LRs (vcpu 7) mask=0 Apr 26 17:09:48.716782 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.716782 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.728779 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.728779 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.728779 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.728779 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.728779 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.728779 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.740783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.740783 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.740783 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.740783 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.740783 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.740783 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.752781 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.752781 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.752781 (XEN) No periodic timer Apr 26 17:09:48.752781 (XEN) UNIT8 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.752781 (XEN) VCPU8: CPU34 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.764776 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.764776 (XEN) GICH_LRs (vcpu 8) mask=0 Apr 26 17:09:48.764776 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.776779 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.776779 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.776779 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.776779 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.776779 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.776779 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.788773 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.788773 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.788773 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.788773 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.788773 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.800784 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.800784 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.800784 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.800784 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.800784 (XEN) No periodic timer Apr 26 17:09:48.800784 (XEN) UNIT9 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.812770 (XEN) VCPU9: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.812770 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.824805 (XEN) GICH_LRs (vcpu 9) mask=0 Apr 26 17:09:48.824805 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.824805 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.824805 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.824805 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.836783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.836783 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.836783 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.836783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.836783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.836783 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.848782 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.848782 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.848782 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.848782 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.848782 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.848782 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.860782 (XEN) No periodic timer Apr 26 17:09:48.860782 (XEN) UNIT10 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.860782 (XEN) VCPU10: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.872780 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.872780 (XEN) GICH_LRs (vcpu 10) mask=0 Apr 26 17:09:48.872780 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.872780 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.884775 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.884775 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.884775 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.884775 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.884775 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.884775 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.896785 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.896785 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.896785 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.896785 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.896785 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.896785 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.908774 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.908774 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.908774 (XEN) No periodic timer Apr 26 17:09:48.908774 (XEN) UNIT11 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.920782 (XEN) VCPU11: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.920782 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.920782 (XEN) GICH_LRs (vcpu 11) mask=0 Apr 26 17:09:48.932784 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.932784 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.932784 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.932784 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.932784 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.932784 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.944783 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.944783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.944783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.944783 (XEN) VCPU_LR[9]=0 Apr 26 17:09:48.944783 (XEN) VCPU_LR[10]=0 Apr 26 17:09:48.944783 (XEN) VCPU_LR[11]=0 Apr 26 17:09:48.956787 (XEN) VCPU_LR[12]=0 Apr 26 17:09:48.956787 (XEN) VCPU_LR[13]=0 Apr 26 17:09:48.956787 (XEN) VCPU_LR[14]=0 Apr 26 17:09:48.956787 (XEN) VCPU_LR[15]=0 Apr 26 17:09:48.956787 (XEN) No periodic timer Apr 26 17:09:48.956787 (XEN) UNIT12 affinities: hard={0-95} soft={0-95} Apr 26 17:09:48.968782 (XEN) VCPU12: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:48.968782 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:48.980770 (XEN) GICH_LRs (vcpu 12) mask=0 Apr 26 17:09:48.980770 (XEN) VCPU_LR[0]=0 Apr 26 17:09:48.980770 (XEN) VCPU_LR[1]=0 Apr 26 17:09:48.980770 (XEN) VCPU_LR[2]=0 Apr 26 17:09:48.980770 (XEN) VCPU_LR[3]=0 Apr 26 17:09:48.992785 (XEN) VCPU_LR[4]=0 Apr 26 17:09:48.992785 (XEN) VCPU_LR[5]=0 Apr 26 17:09:48.992785 (XEN) VCPU_LR[6]=0 Apr 26 17:09:48.992785 (XEN) VCPU_LR[7]=0 Apr 26 17:09:48.992785 (XEN) VCPU_LR[8]=0 Apr 26 17:09:48.992785 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.004784 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.004784 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.004784 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.004784 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.004784 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.004784 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.016786 (XEN) No periodic timer Apr 26 17:09:49.016786 (XEN) UNIT13 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.016786 (XEN) VCPU13: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.028769 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.028769 (XEN) GICH_LRs (vcpu 13) mask=0 Apr 26 17:09:49.028769 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.028769 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.040772 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.040772 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.040772 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.040772 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.040772 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.052785 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.052785 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.052785 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.052785 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.052785 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.052785 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.064779 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.064779 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.064779 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.064779 (XEN) No periodic timer Apr 26 17:09:49.064779 (XEN) UNIT14 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.076775 (XEN) VCPU14: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.076775 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.076775 (XEN) GICH_LRs (vcpu 14) mask=0 Apr 26 17:09:49.088780 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.088780 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.088780 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.088780 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.088780 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.088780 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.100785 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.100785 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.100785 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.100785 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.100785 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.100785 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.112781 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.112781 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.112781 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.112781 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.112781 (XEN) No periodic timer Apr 26 17:09:49.124783 (XEN) UNIT15 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.124783 (XEN) VCPU15: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.124783 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.136784 (XEN) GICH_LRs (vcpu 15) mask=0 Apr 26 17:09:49.136784 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.136784 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.136784 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.136784 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.148783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.148783 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.148783 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.148783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.148783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.148783 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.160925 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.160925 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.160925 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.160925 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.160925 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.160925 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.172776 (XEN) No periodic timer Apr 26 17:09:49.172776 (XEN) UNIT16 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.172776 (XEN) VCPU16: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.184784 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.184784 (XEN) GICH_LRs (vcpu 16) mask=0 Apr 26 17:09:49.184784 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.196788 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.196788 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.196788 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.196788 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.196788 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.196788 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.208794 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.208794 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.208794 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.208794 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.208794 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.208794 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.220781 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.220781 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.220781 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.220781 (XEN) No periodic timer Apr 26 17:09:49.220781 (XEN) UNIT17 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.232771 (XEN) VCPU17: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.232771 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.232771 (XEN) GICH_LRs (vcpu 17) mask=0 Apr 26 17:09:49.244783 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.244783 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.244783 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.244783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.244783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.256789 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.256789 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.256789 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.256789 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.256789 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.256789 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.268781 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.268781 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.268781 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.268781 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.268781 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.268781 (XEN) No periodic timer Apr 26 17:09:49.280769 (XEN) UNIT18 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.280769 (XEN) VCPU18: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.280769 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.292777 (XEN) GICH_LRs (vcpu 18) mask=0 Apr 26 17:09:49.292777 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.292777 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.292777 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.304783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.304783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.304783 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.304783 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.304783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.304783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.316776 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.316776 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.316776 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.316776 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.316776 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.316776 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.328784 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.328784 (XEN) No periodic timer Apr 26 17:09:49.328784 (XEN) UNIT19 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.328784 (XEN) VCPU19: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.340782 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.340782 (XEN) GICH_LRs (vcpu 19) mask=0 Apr 26 17:09:49.340782 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.352784 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.352784 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.352784 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.352784 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.352784 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.352784 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.364784 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.364784 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.364784 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.364784 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.364784 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.364784 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.376780 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.376780 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.376780 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.376780 (XEN) No periodic timer Apr 26 17:09:49.376780 (XEN) UNIT20 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.388777 (XEN) VCPU20: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.388777 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.388777 (XEN) GICH_LRs (vcpu 20) mask=0 Apr 26 17:09:49.400787 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.400787 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.400787 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.400787 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.400787 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.412783 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.412783 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.412783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.412783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.412783 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.412783 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.424774 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.424774 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.424774 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.424774 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.424774 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.436785 (XEN) No periodic timer Apr 26 17:09:49.436785 (XEN) UNIT21 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.436785 (XEN) VCPU21: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.448781 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.448781 (XEN) GICH_LRs (vcpu 21) mask=0 Apr 26 17:09:49.448781 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.448781 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.448781 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.460783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.460783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.460783 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.460783 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.460783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.460783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.472780 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.472780 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.472780 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.472780 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.472780 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.484745 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.484745 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.484745 (XEN) No periodic timer Apr 26 17:09:49.484745 (XEN) UNIT22 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.484745 (XEN) VCPU22: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.496783 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.496783 (XEN) GICH_LRs (vcpu 22) mask=0 Apr 26 17:09:49.496783 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.508787 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.508787 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.508787 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.508787 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.508787 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.508787 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.520785 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.520785 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.520785 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.520785 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.520785 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.520785 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.532762 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.532762 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.532762 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.532762 (XEN) No periodic timer Apr 26 17:09:49.532762 (XEN) UNIT23 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.544777 (XEN) VCPU23: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.544777 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.556787 (XEN) GICH_LRs (vcpu 23) mask=0 Apr 26 17:09:49.556787 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.556787 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.556787 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.556787 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.568780 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.568780 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.568780 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.568780 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.568780 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.568780 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.580781 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.580781 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.580781 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.580781 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.580781 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.580781 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.592783 (XEN) No periodic timer Apr 26 17:09:49.592783 (XEN) UNIT24 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.592783 (XEN) VCPU24: CPU70 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.604785 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.604785 (XEN) GICH_LRs (vcpu 24) mask=0 Apr 26 17:09:49.604785 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.604785 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.616771 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.616771 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.616771 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.616771 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.616771 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.616771 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.628780 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.628780 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.628780 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.628780 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.628780 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.628780 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.640781 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.640781 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.640781 (XEN) No periodic timer Apr 26 17:09:49.640781 (XEN) UNIT25 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.640781 (XEN) VCPU25: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.652784 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.652784 (XEN) GICH_LRs (vcpu 25) mask=0 Apr 26 17:09:49.652784 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.664776 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.664776 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.664776 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.664776 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.664776 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.664776 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.676775 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.676775 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.676775 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.676775 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.676775 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.688782 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.688782 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.688782 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.688782 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.688782 (XEN) No periodic timer Apr 26 17:09:49.700782 (XEN) UNIT26 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.700782 (XEN) VCPU26: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.700782 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.712787 (XEN) GICH_LRs (vcpu 26) mask=0 Apr 26 17:09:49.712787 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.712787 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.712787 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.712787 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.724782 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.724782 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.724782 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.724782 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.724782 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.724782 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.736777 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.736777 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.736777 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.736777 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.736777 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.736777 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.748781 (XEN) No periodic timer Apr 26 17:09:49.748781 (XEN) UNIT27 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.748781 (XEN) VCPU27: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.760783 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.760783 (XEN) GICH_LRs (vcpu 27) mask=0 Apr 26 17:09:49.760783 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.760783 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.772781 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.772781 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.772781 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.772781 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.772781 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.772781 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.784778 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.784778 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.784778 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.784778 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.784778 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.784778 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.796781 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.796781 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.796781 (XEN) No periodic timer Apr 26 17:09:49.796781 (XEN) UNIT28 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.808776 (XEN) VCPU28: CPU72 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.808776 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.808776 (XEN) GICH_LRs (vcpu 28) mask=0 Apr 26 17:09:49.820777 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.820777 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.820777 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.820777 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.820777 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.820777 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.832793 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.832793 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.832793 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.832793 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.832793 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.832793 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.844915 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.844977 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.845019 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.845060 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.845100 (XEN) No periodic timer Apr 26 17:09:49.856785 (XEN) UNIT29 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.856785 (XEN) VCPU29: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.856785 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.868783 (XEN) GICH_LRs (vcpu 29) mask=0 Apr 26 17:09:49.868783 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.868783 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.868783 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.868783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.880778 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.880778 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.880778 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.880778 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.880778 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.880778 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.892781 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.892781 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.892781 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.892781 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.892781 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.892781 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.904784 (XEN) No periodic timer Apr 26 17:09:49.904784 (XEN) UNIT30 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.904784 (XEN) VCPU30: CPU6 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.916786 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.916786 (XEN) GICH_LRs (vcpu 30) mask=0 Apr 26 17:09:49.916786 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.916786 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.928770 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.928770 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.928770 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.928770 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.928770 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.940782 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.940782 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.940782 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.940782 (XEN) VCPU_LR[10]=0 Apr 26 17:09:49.940782 (XEN) VCPU_LR[11]=0 Apr 26 17:09:49.940782 (XEN) VCPU_LR[12]=0 Apr 26 17:09:49.952783 (XEN) VCPU_LR[13]=0 Apr 26 17:09:49.952783 (XEN) VCPU_LR[14]=0 Apr 26 17:09:49.952783 (XEN) VCPU_LR[15]=0 Apr 26 17:09:49.952783 (XEN) No periodic timer Apr 26 17:09:49.952783 (XEN) UNIT31 affinities: hard={0-95} soft={0-95} Apr 26 17:09:49.964782 (XEN) VCPU31: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:49.964782 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:49.964782 (XEN) GICH_LRs (vcpu 31) mask=0 Apr 26 17:09:49.976772 (XEN) VCPU_LR[0]=0 Apr 26 17:09:49.976772 (XEN) VCPU_LR[1]=0 Apr 26 17:09:49.976772 (XEN) VCPU_LR[2]=0 Apr 26 17:09:49.976772 (XEN) VCPU_LR[3]=0 Apr 26 17:09:49.976772 (XEN) VCPU_LR[4]=0 Apr 26 17:09:49.988775 (XEN) VCPU_LR[5]=0 Apr 26 17:09:49.988775 (XEN) VCPU_LR[6]=0 Apr 26 17:09:49.988775 (XEN) VCPU_LR[7]=0 Apr 26 17:09:49.988775 (XEN) VCPU_LR[8]=0 Apr 26 17:09:49.988775 (XEN) VCPU_LR[9]=0 Apr 26 17:09:49.988775 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.000780 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.000780 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.000780 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.000780 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.000780 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.000780 (XEN) No periodic timer Apr 26 17:09:50.012789 (XEN) UNIT32 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.012789 (XEN) VCPU32: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.012789 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.024779 (XEN) GICH_LRs (vcpu 32) mask=0 Apr 26 17:09:50.024779 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.024779 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.024779 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.024779 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.036775 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.036775 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.036775 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.036775 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.036775 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.036775 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.048782 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.048782 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.048782 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.048782 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.048782 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.060774 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.060774 (XEN) No periodic timer Apr 26 17:09:50.060774 (XEN) UNIT33 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.060774 (XEN) VCPU33: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.072778 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.072778 (XEN) GICH_LRs (vcpu 33) mask=0 Apr 26 17:09:50.072778 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.084779 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.084779 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.084779 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.084779 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.084779 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.084779 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.096788 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.096788 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.096788 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.096788 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.096788 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.096788 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.108779 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.108779 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.108779 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.108779 (XEN) No periodic timer Apr 26 17:09:50.108779 (XEN) UNIT34 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.120773 (XEN) VCPU34: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.120773 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.120773 (XEN) GICH_LRs (vcpu 34) mask=0 Apr 26 17:09:50.132783 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.132783 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.132783 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.132783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.132783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.144793 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.144793 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.144793 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.144793 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.144793 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.144793 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.156780 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.156780 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.156780 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.156780 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.156780 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.156780 (XEN) No periodic timer Apr 26 17:09:50.168780 (XEN) UNIT35 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.168780 (XEN) VCPU35: CPU89 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.168780 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.180771 (XEN) GICH_LRs (vcpu 35) mask=0 Apr 26 17:09:50.180771 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.180771 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.180771 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.192783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.192783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.192783 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.192783 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.192783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.192783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.204782 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.204782 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.204782 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.204782 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.204782 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.216785 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.216785 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.216785 (XEN) No periodic timer Apr 26 17:09:50.216785 (XEN) UNIT36 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.216785 (XEN) VCPU36: CPU7 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.228780 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.228780 (XEN) GICH_LRs (vcpu 36) mask=0 Apr 26 17:09:50.228780 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.240778 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.240778 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.240778 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.240778 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.240778 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.240778 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.252783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.252783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.252783 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.252783 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.252783 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.252783 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.264786 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.264786 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.264786 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.264786 (XEN) No periodic timer Apr 26 17:09:50.264786 (XEN) UNIT37 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.276779 (XEN) VCPU37: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.276779 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.288771 (XEN) GICH_LRs (vcpu 37) mask=0 Apr 26 17:09:50.288771 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.288771 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.288771 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.288771 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.288771 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.300780 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.300780 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.300780 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.300780 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.300780 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.300780 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.312775 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.312775 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.312775 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.312775 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.312775 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.324782 (XEN) No periodic timer Apr 26 17:09:50.324782 (XEN) UNIT38 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.324782 (XEN) VCPU38: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.336785 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.336785 (XEN) GICH_LRs (vcpu 38) mask=0 Apr 26 17:09:50.336785 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.336785 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.348782 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.348782 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.348782 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.348782 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.348782 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.348782 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.360784 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.360784 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.360784 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.360784 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.360784 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.360784 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.372783 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.372783 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.372783 (XEN) No periodic timer Apr 26 17:09:50.372783 (XEN) UNIT39 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.372783 (XEN) VCPU39: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.384773 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.384773 (XEN) GICH_LRs (vcpu 39) mask=0 Apr 26 17:09:50.384773 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.396786 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.396786 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.396786 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.396786 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.396786 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.396786 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.408783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.408783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.408783 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.408783 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.408783 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.408783 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.420783 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.420783 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.420783 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.420783 (XEN) No periodic timer Apr 26 17:09:50.420783 (XEN) UNIT40 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.432773 (XEN) VCPU40: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.432773 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.444771 (XEN) GICH_LRs (vcpu 40) mask=0 Apr 26 17:09:50.444771 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.444771 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.444771 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.444771 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.456793 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.456793 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.456793 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.456793 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.456793 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.456793 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.468782 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.468782 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.468782 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.468782 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.468782 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.468782 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.480781 (XEN) No periodic timer Apr 26 17:09:50.480781 (XEN) UNIT41 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.480781 (XEN) VCPU41: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.492781 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.492781 (XEN) GICH_LRs (vcpu 41) mask=0 Apr 26 17:09:50.492781 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.492781 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.504784 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.504784 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.504784 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.504784 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.504784 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.504784 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.516787 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.516787 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.516787 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.516787 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.516787 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.516787 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.528780 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.528780 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.528780 (XEN) No periodic timer Apr 26 17:09:50.528780 (XEN) UNIT42 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.528780 (XEN) VCPU42: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.540780 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.540780 (XEN) GICH_LRs (vcpu 42) mask=0 Apr 26 17:09:50.552787 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.552787 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.552787 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.552787 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.552787 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.552787 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.564775 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.564775 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.564775 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.564775 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.564775 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.564775 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.576772 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.576772 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.576772 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.576772 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.576772 (XEN) No periodic timer Apr 26 17:09:50.588783 (XEN) UNIT43 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.588783 (XEN) VCPU43: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.588783 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.600783 (XEN) GICH_LRs (vcpu 43) mask=0 Apr 26 17:09:50.600783 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.600783 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.600783 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.600783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.612781 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.612781 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.612781 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.612781 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.612781 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.612781 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.624780 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.624780 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.624780 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.624780 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.624780 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.624780 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.636785 (XEN) No periodic timer Apr 26 17:09:50.636785 (XEN) UNIT44 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.636785 (XEN) VCPU44: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.648780 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.648780 (XEN) GICH_LRs (vcpu 44) mask=0 Apr 26 17:09:50.648780 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.648780 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.660772 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.660772 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.660772 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.660772 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.660772 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.660772 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.672784 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.672784 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.672784 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.672784 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.672784 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.672784 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.684785 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.684785 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.684785 (XEN) No periodic timer Apr 26 17:09:50.684785 (XEN) UNIT45 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.696773 (XEN) VCPU45: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.696773 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.696773 (XEN) GICH_LRs (vcpu 45) mask=0 Apr 26 17:09:50.708781 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.708781 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.708781 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.708781 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.708781 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.720783 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.720783 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.720783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.720783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.720783 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.720783 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.732770 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.732770 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.732770 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.732770 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.732770 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.732770 (XEN) No periodic timer Apr 26 17:09:50.744782 (XEN) UNIT46 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.744782 (XEN) VCPU46: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.744782 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.756783 (XEN) GICH_LRs (vcpu 46) mask=0 Apr 26 17:09:50.756783 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.756783 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.756783 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.756783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.768794 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.768794 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.768794 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.768794 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.768794 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.768794 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.780771 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.780771 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.780771 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.780771 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.780771 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.792784 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.792784 (XEN) No periodic timer Apr 26 17:09:50.792784 (XEN) UNIT47 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.792784 (XEN) VCPU47: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.804784 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.804784 (XEN) GICH_LRs (vcpu 47) mask=0 Apr 26 17:09:50.804784 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.804784 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.816767 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.816767 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.816767 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.816767 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.816767 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.828782 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.828782 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.828782 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.828782 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.828782 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.828782 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.840804 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.840804 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.840804 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.840804 (XEN) No periodic timer Apr 26 17:09:50.840804 (XEN) UNIT48 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.852784 (XEN) VCPU48: CPU9 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.852784 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.852784 (XEN) GICH_LRs (vcpu 48) mask=0 Apr 26 17:09:50.864783 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.864783 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.864783 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.864783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.864783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.876781 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.876781 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.876781 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.876781 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.876781 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.876781 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.888876 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.888937 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.888979 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.889020 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.889060 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.889100 (XEN) No periodic timer Apr 26 17:09:50.900782 (XEN) UNIT49 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.900782 (XEN) VCPU49: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.900782 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.912788 (XEN) GICH_LRs (vcpu 49) mask=0 Apr 26 17:09:50.912788 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.912788 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.912788 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.924783 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.924783 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.924783 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.924783 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.924783 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.924783 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.936779 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.936779 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.936779 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.936779 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.936779 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.936779 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.948769 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.948769 (XEN) No periodic timer Apr 26 17:09:50.948769 (XEN) UNIT50 affinities: hard={0-95} soft={0-95} Apr 26 17:09:50.948769 (XEN) VCPU50: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:50.960777 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:50.960777 (XEN) GICH_LRs (vcpu 50) mask=0 Apr 26 17:09:50.960777 (XEN) VCPU_LR[0]=0 Apr 26 17:09:50.972933 (XEN) VCPU_LR[1]=0 Apr 26 17:09:50.973081 (XEN) VCPU_LR[2]=0 Apr 26 17:09:50.973127 (XEN) VCPU_LR[3]=0 Apr 26 17:09:50.973169 (XEN) VCPU_LR[4]=0 Apr 26 17:09:50.973210 (XEN) VCPU_LR[5]=0 Apr 26 17:09:50.973253 (XEN) VCPU_LR[6]=0 Apr 26 17:09:50.984777 (XEN) VCPU_LR[7]=0 Apr 26 17:09:50.984777 (XEN) VCPU_LR[8]=0 Apr 26 17:09:50.984777 (XEN) VCPU_LR[9]=0 Apr 26 17:09:50.984777 (XEN) VCPU_LR[10]=0 Apr 26 17:09:50.984777 (XEN) VCPU_LR[11]=0 Apr 26 17:09:50.984777 (XEN) VCPU_LR[12]=0 Apr 26 17:09:50.996787 (XEN) VCPU_LR[13]=0 Apr 26 17:09:50.996787 (XEN) VCPU_LR[14]=0 Apr 26 17:09:50.996787 (XEN) VCPU_LR[15]=0 Apr 26 17:09:50.996787 (XEN) No periodic timer Apr 26 17:09:50.996787 (XEN) UNIT51 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.008783 (XEN) VCPU51: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.008783 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.020782 (XEN) GICH_LRs (vcpu 51) mask=0 Apr 26 17:09:51.020782 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.020782 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.020782 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.020782 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.020782 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.032773 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.032773 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.032773 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.032773 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.032773 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.032773 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.044783 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.044783 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.044783 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.044783 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.044783 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.044783 (XEN) No periodic timer Apr 26 17:09:51.056779 (XEN) UNIT52 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.056779 (XEN) VCPU52: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.068940 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.069004 (XEN) GICH_LRs (vcpu 52) mask=0 Apr 26 17:09:51.069048 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.069090 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.080920 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.080976 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.081019 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.081060 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.081101 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.081142 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.092918 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.092975 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.093017 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.093058 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.093099 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.093139 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.104919 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.104976 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.105018 (XEN) No periodic timer Apr 26 17:09:51.105060 (XEN) UNIT53 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.105106 (XEN) VCPU53: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.116941 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.116999 (XEN) GICH_LRs (vcpu 53) mask=0 Apr 26 17:09:51.117044 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.128935 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.128991 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.129033 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.129073 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.129114 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.129154 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.140928 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.140984 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.141026 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.141067 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.141107 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.152922 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.152981 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.153024 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.153065 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.153106 (XEN) No periodic timer Apr 26 17:09:51.153147 (XEN) UNIT54 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.164940 (XEN) VCPU54: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.165004 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.176939 (XEN) GICH_LRs (vcpu 54) mask=0 Apr 26 17:09:51.176998 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.177041 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.177082 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.177123 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.177163 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.188927 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.188983 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.189025 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.189066 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.189106 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.189146 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.200916 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.200972 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.201015 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.201056 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.201097 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.212944 (XEN) No periodic timer Apr 26 17:09:51.213002 (XEN) UNIT55 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.213050 (XEN) VCPU55: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.224940 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.224999 (XEN) GICH_LRs (vcpu 55) mask=0 Apr 26 17:09:51.225044 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.225085 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.236918 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.236974 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.237057 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.237099 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.237140 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.237181 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.248927 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.248983 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.249025 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.249066 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.249106 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.249147 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.260920 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.260976 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.261018 (XEN) No periodic timer Apr 26 17:09:51.261060 (XEN) UNIT56 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.261106 (XEN) VCPU56: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.272933 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.272991 (XEN) GICH_LRs (vcpu 56) mask=0 Apr 26 17:09:51.284930 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.284986 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.285064 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.285108 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.285149 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.285190 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.296923 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.296979 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.297022 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.297063 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.297105 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.297145 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.308936 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.308992 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.309035 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.309076 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.309116 (XEN) No periodic timer Apr 26 17:09:51.309158 (XEN) UNIT57 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.320936 (XEN) VCPU57: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.321000 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.332913 (XEN) GICH_LRs (vcpu 57) mask=0 Apr 26 17:09:51.332972 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.333015 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.333056 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.333096 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.344922 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.344978 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.345020 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.345061 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.345102 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.345142 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.356923 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.356979 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.357021 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.357062 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.357102 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.368926 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.368984 (XEN) No periodic timer Apr 26 17:09:51.369028 (XEN) UNIT58 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.369075 (XEN) VCPU58: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.380930 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.380990 (XEN) GICH_LRs (vcpu 58) mask=0 Apr 26 17:09:51.381034 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.381075 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.392901 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.392956 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.392998 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.393038 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.393078 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.393117 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.404890 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.404946 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.404989 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.405048 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.405092 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.405133 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.416929 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.416985 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.417028 (XEN) No periodic timer Apr 26 17:09:51.417070 (XEN) UNIT59 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.428928 (XEN) VCPU59: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.428992 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.429038 (XEN) GICH_LRs (vcpu 59) mask=0 Apr 26 17:09:51.440927 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.440983 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.441026 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.441066 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.441106 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.441146 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.452919 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.452976 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.453018 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.453059 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.453099 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.464917 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.464973 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.465015 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.465055 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.465095 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.465135 (XEN) No periodic timer Apr 26 17:09:51.476929 (XEN) UNIT60 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.476991 (XEN) VCPU60: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.477042 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.488926 (XEN) GICH_LRs (vcpu 60) mask=0 Apr 26 17:09:51.488984 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.489027 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.489067 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.500918 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.500976 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.501018 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.501059 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.501100 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.501140 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.512919 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.512977 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.513019 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.513060 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.513100 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.513140 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.524926 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.524983 (XEN) No periodic timer Apr 26 17:09:51.525026 (XEN) UNIT61 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.525074 (XEN) VCPU61: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.536925 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.536984 (XEN) GICH_LRs (vcpu 61) mask=0 Apr 26 17:09:51.537029 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.537070 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.548927 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.548983 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.549026 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.549067 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.549107 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.549147 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.560925 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.560980 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.561022 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.561062 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.561102 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.561141 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.572924 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.572979 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.573020 (XEN) No periodic timer Apr 26 17:09:51.573062 (XEN) UNIT62 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.584922 (XEN) VCPU62: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.584986 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.596916 (XEN) GICH_LRs (vcpu 62) mask=0 Apr 26 17:09:51.596976 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.597018 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.597059 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.597098 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.597138 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.608887 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.608942 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.609000 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.609043 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.609084 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.609124 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.620904 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.620961 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.621003 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.621043 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.621084 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.621124 (XEN) No periodic timer Apr 26 17:09:51.632929 (XEN) UNIT63 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.632990 (XEN) VCPU63: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.644924 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.644984 (XEN) GICH_LRs (vcpu 63) mask=0 Apr 26 17:09:51.645028 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.645069 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.645109 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.656919 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.656976 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.657018 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.657059 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.657099 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.657138 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.668935 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.668991 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.669033 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.669074 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.669114 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.669153 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.680926 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.680982 (XEN) No periodic timer Apr 26 17:09:51.681025 (XEN) UNIT64 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.681071 (XEN) VCPU64: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.692942 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.693000 (XEN) GICH_LRs (vcpu 64) mask=0 Apr 26 17:09:51.693044 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.704910 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.704968 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.705010 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.705051 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.705091 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.705131 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.716921 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.716976 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.717018 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.717058 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.717098 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.717138 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.728929 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.728984 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.729026 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.729067 (XEN) No periodic timer Apr 26 17:09:51.729108 (XEN) UNIT65 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.740925 (XEN) VCPU65: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.740990 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.752925 (XEN) GICH_LRs (vcpu 65) mask=0 Apr 26 17:09:51.752984 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.753026 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.753066 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.753106 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.753146 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.764948 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.765004 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.795769 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.795844 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.795889 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.795929 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.796030 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.796072 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.796113 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.796152 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.796193 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.796233 (XEN) No periodic timer Apr 26 17:09:51.796274 (XEN) UNIT66 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.796319 (XEN) VCPU66: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.800923 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.800981 (XEN) GICH_LRs (vcpu 66) mask=0 Apr 26 17:09:51.801138 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.801191 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.801250 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.812922 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.812978 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.813020 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.813060 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.813100 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.813140 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.824935 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.824991 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.825033 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.825073 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.825113 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.825153 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.836911 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.836968 (XEN) No periodic timer Apr 26 17:09:51.837010 (XEN) UNIT67 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.837057 (XEN) VCPU67: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.848931 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.848989 (XEN) GICH_LRs (vcpu 67) mask=0 Apr 26 17:09:51.860909 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.860965 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.861007 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.861047 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.861087 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.861127 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.872927 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.872983 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.873026 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.873066 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.873106 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.873146 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.884911 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.884967 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.885009 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.885050 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.885090 (XEN) No periodic timer Apr 26 17:09:51.885131 (XEN) UNIT68 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.896942 (XEN) VCPU68: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.897006 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.908928 (XEN) GICH_LRs (vcpu 68) mask=0 Apr 26 17:09:51.908986 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.909029 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.909069 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.909110 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.909150 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.920929 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.920985 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.921027 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.921067 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.921106 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.921146 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.932929 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.932985 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.933027 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.933067 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.933107 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.944927 (XEN) No periodic timer Apr 26 17:09:51.944984 (XEN) UNIT69 affinities: hard={0-95} soft={0-95} Apr 26 17:09:51.945031 (XEN) VCPU69: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:51.956925 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:51.956984 (XEN) GICH_LRs (vcpu 69) mask=0 Apr 26 17:09:51.957028 (XEN) VCPU_LR[0]=0 Apr 26 17:09:51.957069 (XEN) VCPU_LR[1]=0 Apr 26 17:09:51.957109 (XEN) VCPU_LR[2]=0 Apr 26 17:09:51.968904 (XEN) VCPU_LR[3]=0 Apr 26 17:09:51.968960 (XEN) VCPU_LR[4]=0 Apr 26 17:09:51.969001 (XEN) VCPU_LR[5]=0 Apr 26 17:09:51.969042 (XEN) VCPU_LR[6]=0 Apr 26 17:09:51.969082 (XEN) VCPU_LR[7]=0 Apr 26 17:09:51.980941 (XEN) VCPU_LR[8]=0 Apr 26 17:09:51.980997 (XEN) VCPU_LR[9]=0 Apr 26 17:09:51.981038 (XEN) VCPU_LR[10]=0 Apr 26 17:09:51.981079 (XEN) VCPU_LR[11]=0 Apr 26 17:09:51.981119 (XEN) VCPU_LR[12]=0 Apr 26 17:09:51.981159 (XEN) VCPU_LR[13]=0 Apr 26 17:09:51.992919 (XEN) VCPU_LR[14]=0 Apr 26 17:09:51.992975 (XEN) VCPU_LR[15]=0 Apr 26 17:09:51.993017 (XEN) No periodic timer Apr 26 17:09:51.993059 (XEN) UNIT70 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.004862 (XEN) VCPU70: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.004946 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.004994 (XEN) GICH_LRs (vcpu 70) mask=0 Apr 26 17:09:52.016936 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.016992 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.017034 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.017074 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.017115 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.017155 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.028932 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.028988 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.029030 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.029070 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.029110 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.029149 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.040921 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.040977 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.041019 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.041059 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.041099 (XEN) No periodic timer Apr 26 17:09:52.041139 (XEN) UNIT71 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.052931 (XEN) VCPU71: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.052995 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.064945 (XEN) GICH_LRs (vcpu 71) mask=0 Apr 26 17:09:52.065003 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.065045 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.065085 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.065125 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.076926 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.076982 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.077024 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.077065 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.077105 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.077144 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.088914 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.088971 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.089013 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.089053 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.089093 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.100918 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.100975 (XEN) No periodic timer Apr 26 17:09:52.101018 (XEN) UNIT72 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.101064 (XEN) VCPU72: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.112923 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.112981 (XEN) GICH_LRs (vcpu 72) mask=0 Apr 26 17:09:52.113026 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.113067 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.124907 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.124962 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.125003 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.125044 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.125083 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.125124 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.136934 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.136990 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.137032 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.137072 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.137112 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.137152 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.148928 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.148984 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.149026 (XEN) No periodic timer Apr 26 17:09:52.149067 (XEN) UNIT73 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.160928 (XEN) VCPU73: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.160992 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.161037 (XEN) GICH_LRs (vcpu 73) mask=0 Apr 26 17:09:52.172942 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.172997 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.173039 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.173079 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.173119 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.173160 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.184929 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.184984 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.185026 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.185067 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.185107 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.185146 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.196919 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.196974 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.197017 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.197057 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.197115 (XEN) No periodic timer Apr 26 17:09:52.197160 (XEN) UNIT74 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.208934 (XEN) VCPU74: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.208998 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.220908 (XEN) GICH_LRs (vcpu 74) mask=0 Apr 26 17:09:52.220966 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.221008 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.221048 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.232927 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.232983 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.233024 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.233064 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.233104 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.233144 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.244918 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.244974 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.245017 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.245057 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.245097 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.245137 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.256928 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.256984 (XEN) No periodic timer Apr 26 17:09:52.257027 (XEN) UNIT75 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.257073 (XEN) VCPU75: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.268930 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.268988 (XEN) GICH_LRs (vcpu 75) mask=0 Apr 26 17:09:52.269032 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.269073 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.280931 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.280986 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.281028 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.281067 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.281107 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.281146 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.292921 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.292977 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.293018 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.293058 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.293098 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.304911 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.304968 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.305010 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.305050 (XEN) No periodic timer Apr 26 17:09:52.305091 (XEN) UNIT76 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.316883 (XEN) VCPU76: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.316948 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.316993 (XEN) GICH_LRs (vcpu 76) mask=0 Apr 26 17:09:52.328879 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.328936 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.328978 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.329018 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.329058 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.329097 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.340813 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.340861 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.340902 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.340942 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.340981 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.352778 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.352809 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.352832 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.352854 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.352875 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.352897 (XEN) No periodic timer Apr 26 17:09:52.364796 (XEN) UNIT77 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.364830 (XEN) VCPU77: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.376887 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.376946 (XEN) GICH_LRs (vcpu 77) mask=0 Apr 26 17:09:52.376991 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.377032 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.377072 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.388864 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.388920 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.388962 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.389002 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.389042 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.389082 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.400839 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.400895 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.400955 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.400999 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.401039 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.401079 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.412857 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.412912 (XEN) No periodic timer Apr 26 17:09:52.412955 (XEN) UNIT78 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.413001 (XEN) VCPU78: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.424859 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.424917 (XEN) GICH_LRs (vcpu 78) mask=0 Apr 26 17:09:52.424961 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.436850 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.436906 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.436948 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.436988 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.437029 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.437068 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.448868 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.448925 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.448967 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.449007 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.449047 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.449087 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.460891 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.460947 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.460990 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.461030 (XEN) No periodic timer Apr 26 17:09:52.461071 (XEN) UNIT79 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.472879 (XEN) VCPU79: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.472943 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.484894 (XEN) GICH_LRs (vcpu 79) mask=0 Apr 26 17:09:52.484953 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.484995 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.485035 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.485076 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.485116 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.496888 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.496944 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.496986 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.497026 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.497066 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.497105 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.508892 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.508947 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.508990 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.509030 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.509070 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.520883 (XEN) No periodic timer Apr 26 17:09:52.520940 (XEN) UNIT80 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.520988 (XEN) VCPU80: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.532884 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.532943 (XEN) GICH_LRs (vcpu 80) mask=0 Apr 26 17:09:52.532987 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.533028 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.533068 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.544885 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.544940 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.544983 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.545046 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.545110 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.545173 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.556886 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.556941 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.556984 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.557025 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.557065 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.557105 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.568883 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.568939 (XEN) No periodic timer Apr 26 17:09:52.568982 (XEN) UNIT81 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.569029 (XEN) VCPU81: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.580898 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.580956 (XEN) GICH_LRs (vcpu 81) mask=0 Apr 26 17:09:52.581000 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.592885 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.592942 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.592984 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.593025 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.593065 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.593104 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.604894 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.604926 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.604949 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.604995 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.605036 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.616810 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.616836 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.616859 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.616881 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.616903 (XEN) No periodic timer Apr 26 17:09:52.616926 (XEN) UNIT82 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.628899 (XEN) VCPU82: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.628962 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.640921 (XEN) GICH_LRs (vcpu 82) mask=0 Apr 26 17:09:52.640980 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.641022 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.641063 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.641103 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.652914 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.652972 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.653015 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.653056 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.653096 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.653136 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.664927 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.664985 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.665027 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.665068 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.665109 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.665149 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.676924 (XEN) No periodic timer Apr 26 17:09:52.676981 (XEN) UNIT83 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.677029 (XEN) VCPU83: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.688929 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.688987 (XEN) GICH_LRs (vcpu 83) mask=0 Apr 26 17:09:52.689032 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.689073 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.689113 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.700929 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.700985 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.701026 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.701067 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.701107 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.701147 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.712926 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.712981 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.713023 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.713064 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.713104 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.713144 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.724905 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.724961 (XEN) No periodic timer Apr 26 17:09:52.725004 (XEN) UNIT84 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.736928 (XEN) VCPU84: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.736993 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.737038 (XEN) GICH_LRs (vcpu 84) mask=0 Apr 26 17:09:52.748920 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.748977 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.749019 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.749060 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.749100 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.749140 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.760928 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.760985 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.761029 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.761070 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.761111 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.761151 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.772937 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.772993 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.773035 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.773075 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.773115 (XEN) No periodic timer Apr 26 17:09:52.773156 (XEN) UNIT85 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.784932 (XEN) VCPU85: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.784997 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.796923 (XEN) GICH_LRs (vcpu 85) mask=0 Apr 26 17:09:52.796980 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.797022 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.797081 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.797125 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.808907 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.808963 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.809005 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.809045 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.809086 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.809126 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.820908 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.820966 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.821008 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.821048 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.821088 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.821128 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.832928 (XEN) No periodic timer Apr 26 17:09:52.832984 (XEN) UNIT86 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.833032 (XEN) VCPU86: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.844933 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.844992 (XEN) GICH_LRs (vcpu 86) mask=0 Apr 26 17:09:52.845036 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.845077 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.856819 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.856850 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.856873 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.856895 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.856917 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.856938 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.868918 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.868974 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.869015 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.869055 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.869095 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.880929 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.880987 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.881029 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.881070 (XEN) No periodic timer Apr 26 17:09:52.881111 (XEN) UNIT87 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.892937 (XEN) VCPU87: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.893001 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.893045 (XEN) GICH_LRs (vcpu 87) mask=0 Apr 26 17:09:52.904927 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.904982 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.905023 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.905064 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.905103 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.905142 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.916928 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.916984 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.917025 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.917065 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.917105 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.917144 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.928930 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.928985 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.929027 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.929067 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.929107 (XEN) No periodic timer Apr 26 17:09:52.929148 (XEN) UNIT88 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.940918 (XEN) VCPU88: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:52.940981 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:52.952937 (XEN) GICH_LRs (vcpu 88) mask=0 Apr 26 17:09:52.952994 (XEN) VCPU_LR[0]=0 Apr 26 17:09:52.953036 (XEN) VCPU_LR[1]=0 Apr 26 17:09:52.953076 (XEN) VCPU_LR[2]=0 Apr 26 17:09:52.953116 (XEN) VCPU_LR[3]=0 Apr 26 17:09:52.964935 (XEN) VCPU_LR[4]=0 Apr 26 17:09:52.964991 (XEN) VCPU_LR[5]=0 Apr 26 17:09:52.965034 (XEN) VCPU_LR[6]=0 Apr 26 17:09:52.965074 (XEN) VCPU_LR[7]=0 Apr 26 17:09:52.965114 (XEN) VCPU_LR[8]=0 Apr 26 17:09:52.965154 (XEN) VCPU_LR[9]=0 Apr 26 17:09:52.976922 (XEN) VCPU_LR[10]=0 Apr 26 17:09:52.976978 (XEN) VCPU_LR[11]=0 Apr 26 17:09:52.977020 (XEN) VCPU_LR[12]=0 Apr 26 17:09:52.977060 (XEN) VCPU_LR[13]=0 Apr 26 17:09:52.977100 (XEN) VCPU_LR[14]=0 Apr 26 17:09:52.988923 (XEN) VCPU_LR[15]=0 Apr 26 17:09:52.988979 (XEN) No periodic timer Apr 26 17:09:52.989021 (XEN) UNIT89 affinities: hard={0-95} soft={0-95} Apr 26 17:09:52.989068 (XEN) VCPU89: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:53.000948 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:53.001008 (XEN) GICH_LRs (vcpu 89) mask=0 Apr 26 17:09:53.001053 (XEN) VCPU_LR[0]=0 Apr 26 17:09:53.012938 (XEN) VCPU_LR[1]=0 Apr 26 17:09:53.012994 (XEN) VCPU_LR[2]=0 Apr 26 17:09:53.013037 (XEN) VCPU_LR[3]=0 Apr 26 17:09:53.013078 (XEN) VCPU_LR[4]=0 Apr 26 17:09:53.013118 (XEN) VCPU_LR[5]=0 Apr 26 17:09:53.013157 (XEN) VCPU_LR[6]=0 Apr 26 17:09:53.024930 (XEN) VCPU_LR[7]=0 Apr 26 17:09:53.024986 (XEN) VCPU_LR[8]=0 Apr 26 17:09:53.025028 (XEN) VCPU_LR[9]=0 Apr 26 17:09:53.025068 (XEN) VCPU_LR[10]=0 Apr 26 17:09:53.025109 (XEN) VCPU_LR[11]=0 Apr 26 17:09:53.025149 (XEN) VCPU_LR[12]=0 Apr 26 17:09:53.036917 (XEN) VCPU_LR[13]=0 Apr 26 17:09:53.036974 (XEN) VCPU_LR[14]=0 Apr 26 17:09:53.037016 (XEN) VCPU_LR[15]=0 Apr 26 17:09:53.037056 (XEN) No periodic timer Apr 26 17:09:53.037097 (XEN) UNIT90 affinities: hard={0-95} soft={0-95} Apr 26 17:09:53.048921 (XEN) VCPU90: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:53.048986 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:53.049031 (XEN) GICH_LRs (vcpu 90) mask=0 Apr 26 17:09:53.060925 (XEN) VCPU_LR[0]=0 Apr 26 17:09:53.060982 (XEN) VCPU_LR[1]=0 Apr 26 17:09:53.061024 (XEN) VCPU_LR[2]=0 Apr 26 17:09:53.061064 (XEN) VCPU_LR[3]=0 Apr 26 17:09:53.061104 (XEN) VCPU_LR[4]=0 Apr 26 17:09:53.061144 (XEN) VCPU_LR[5]=0 Apr 26 17:09:53.072928 (XEN) VCPU_LR[6]=0 Apr 26 17:09:53.072984 (XEN) VCPU_LR[7]=0 Apr 26 17:09:53.073026 (XEN) VCPU_LR[8]=0 Apr 26 17:09:53.073067 (XEN) VCPU_LR[9]=0 Apr 26 17:09:53.073107 (XEN) VCPU_LR[10]=0 Apr 26 17:09:53.073147 (XEN) VCPU_LR[11]=0 Apr 26 17:09:53.084936 (XEN) VCPU_LR[12]=0 Apr 26 17:09:53.084991 (XEN) VCPU_LR[13]=0 Apr 26 17:09:53.085033 (XEN) VCPU_LR[14]=0 Apr 26 17:09:53.085073 (XEN) VCPU_LR[15]=0 Apr 26 17:09:53.085113 (XEN) No periodic timer Apr 26 17:09:53.096927 (XEN) UNIT91 affinities: hard={0-95} soft={0-95} Apr 26 17:09:53.096990 (XEN) VCPU91: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:53.097040 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:53.108910 (XEN) GICH_LRs (vcpu 91) mask=0 Apr 26 17:09:53.108968 (XEN) VCPU_LR[0]=0 Apr 26 17:09:53.109010 (XEN) VCPU_LR[1]=0 Apr 26 17:09:53.109050 (XEN) VCPU_LR[2]=0 Apr 26 17:09:53.120914 (XEN) VCPU_LR[3]=0 Apr 26 17:09:53.120970 (XEN) VCPU_LR[4]=0 Apr 26 17:09:53.121011 (XEN) VCPU_LR[5]=0 Apr 26 17:09:53.121052 (XEN) VCPU_LR[6]=0 Apr 26 17:09:53.121092 (XEN) VCPU_LR[7]=0 Apr 26 17:09:53.121132 (XEN) VCPU_LR[8]=0 Apr 26 17:09:53.132935 (XEN) VCPU_LR[9]=0 Apr 26 17:09:53.132991 (XEN) VCPU_LR[10]=0 Apr 26 17:09:53.133033 (XEN) VCPU_LR[11]=0 Apr 26 17:09:53.133073 (XEN) VCPU_LR[12]=0 Apr 26 17:09:53.133113 (XEN) VCPU_LR[13]=0 Apr 26 17:09:53.133153 (XEN) VCPU_LR[14]=0 Apr 26 17:09:53.144940 (XEN) VCPU_LR[15]=0 Apr 26 17:09:53.144996 (XEN) No periodic timer Apr 26 17:09:53.145039 (XEN) UNIT92 affinities: hard={0-95} soft={0-95} Apr 26 17:09:53.145085 (XEN) VCPU92: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:53.156929 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:53.156987 (XEN) GICH_LRs (vcpu 92) mask=0 Apr 26 17:09:53.157032 (XEN) VCPU_LR[0]=0 Apr 26 17:09:53.168930 (XEN) VCPU_LR[1]=0 Apr 26 17:09:53.168986 (XEN) VCPU_LR[2]=0 Apr 26 17:09:53.169028 (XEN) VCPU_LR[3]=0 Apr 26 17:09:53.169068 (XEN) VCPU_LR[4]=0 Apr 26 17:09:53.169108 (XEN) VCPU_LR[5]=0 Apr 26 17:09:53.169147 (XEN) VCPU_LR[6]=0 Apr 26 17:09:53.180931 (XEN) VCPU_LR[7]=0 Apr 26 17:09:53.180987 (XEN) VCPU_LR[8]=0 Apr 26 17:09:53.181029 (XEN) VCPU_LR[9]=0 Apr 26 17:09:53.181070 (XEN) VCPU_LR[10]=0 Apr 26 17:09:53.181110 (XEN) VCPU_LR[11]=0 Apr 26 17:09:53.181149 (XEN) VCPU_LR[12]=0 Apr 26 17:09:53.192925 (XEN) VCPU_LR[13]=0 Apr 26 17:09:53.192982 (XEN) VCPU_LR[14]=0 Apr 26 17:09:53.193024 (XEN) VCPU_LR[15]=0 Apr 26 17:09:53.193083 (XEN) No periodic timer Apr 26 17:09:53.193128 (XEN) UNIT93 affinities: hard={0-95} soft={0-95} Apr 26 17:09:53.204929 (XEN) VCPU93: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:53.204993 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:53.205037 (XEN) GICH_LRs (vcpu 93) mask=0 Apr 26 17:09:53.216931 (XEN) VCPU_LR[0]=0 Apr 26 17:09:53.216986 (XEN) VCPU_LR[1]=0 Apr 26 17:09:53.217029 (XEN) VCPU_LR[2]=0 Apr 26 17:09:53.217069 (XEN) VCPU_LR[3]=0 Apr 26 17:09:53.217109 (XEN) VCPU_LR[4]=0 Apr 26 17:09:53.228909 (XEN) VCPU_LR[5]=0 Apr 26 17:09:53.228966 (XEN) VCPU_LR[6]=0 Apr 26 17:09:53.229008 (XEN) VCPU_LR[7]=0 Apr 26 17:09:53.229048 (XEN) VCPU_LR[8]=0 Apr 26 17:09:53.229088 (XEN) VCPU_LR[9]=0 Apr 26 17:09:53.229127 (XEN) VCPU_LR[10]=0 Apr 26 17:09:53.240926 (XEN) VCPU_LR[11]=0 Apr 26 17:09:53.240982 (XEN) VCPU_LR[12]=0 Apr 26 17:09:53.241024 (XEN) VCPU_LR[13]=0 Apr 26 17:09:53.241064 (XEN) VCPU_LR[14]=0 Apr 26 17:09:53.241104 (XEN) VCPU_LR[15]=0 Apr 26 17:09:53.252911 (XEN) No periodic timer Apr 26 17:09:53.252967 (XEN) UNIT94 affinities: hard={0-95} soft={0-95} Apr 26 17:09:53.253015 (XEN) VCPU94: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:53.264927 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:53.264985 (XEN) GICH_LRs (vcpu 94) mask=0 Apr 26 17:09:53.265029 (XEN) VCPU_LR[0]=0 Apr 26 17:09:53.265070 (XEN) VCPU_LR[1]=0 Apr 26 17:09:53.265109 (XEN) VCPU_LR[2]=0 Apr 26 17:09:53.276931 (XEN) VCPU_LR[3]=0 Apr 26 17:09:53.276987 (XEN) VCPU_LR[4]=0 Apr 26 17:09:53.277029 (XEN) VCPU_LR[5]=0 Apr 26 17:09:53.277069 (XEN) VCPU_LR[6]=0 Apr 26 17:09:53.277108 (XEN) VCPU_LR[7]=0 Apr 26 17:09:53.277148 (XEN) VCPU_LR[8]=0 Apr 26 17:09:53.288930 (XEN) VCPU_LR[9]=0 Apr 26 17:09:53.288986 (XEN) VCPU_LR[10]=0 Apr 26 17:09:53.289027 (XEN) VCPU_LR[11]=0 Apr 26 17:09:53.289067 (XEN) VCPU_LR[12]=0 Apr 26 17:09:53.289107 (XEN) VCPU_LR[13]=0 Apr 26 17:09:53.289147 (XEN) VCPU_LR[14]=0 Apr 26 17:09:53.300924 (XEN) VCPU_LR[15]=0 Apr 26 17:09:53.300980 (XEN) No periodic timer Apr 26 17:09:53.301022 (XEN) UNIT95 affinities: hard={0-95} soft={0-95} Apr 26 17:09:53.301069 (XEN) VCPU95: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Apr 26 17:09:53.312928 (XEN) pause_count=0 pause_flags=1 Apr 26 17:09:53.312986 (XEN) GICH_LRs (vcpu 95) mask=0 Apr 26 17:09:53.313030 (XEN) VCPU_LR[0]=0 Apr 26 17:09:53.324937 (XEN) VCPU_LR[1]=0 Apr 26 17:09:53.324992 (XEN) VCPU_LR[2]=0 Apr 26 17:09:53.325034 (XEN) VCPU_LR[3]=0 Apr 26 17:09:53.325074 (XEN) VCPU_LR[4]=0 Apr 26 17:09:53.325115 (XEN) VCPU_LR[5]=0 Apr 26 17:09:53.325155 (XEN) VCPU_LR[6]=0 Apr 26 17:09:53.336930 (XEN) VCPU_LR[7]=0 Apr 26 17:09:53.336986 (XEN) VCPU_LR[8]=0 Apr 26 17:09:53.337028 (XEN) VCPU_LR[9]=0 Apr 26 17:09:53.337068 (XEN) VCPU_LR[10]=0 Apr 26 17:09:53.337108 (XEN) VCPU_LR[11]=0 Apr 26 17:09:53.337148 (XEN) VCPU_LR[12]=0 Apr 26 17:09:53.348917 (XEN) VCPU_LR[13]=0 Apr 26 17:09:53.348973 (XEN) VCPU_LR[14]=0 Apr 26 17:09:53.349015 (XEN) VCPU_LR[15]=0 Apr 26 17:09:53.349055 (XEN) No periodic timer Apr 26 17:09:53.349097 (XEN) Notifying guest 0:0 (virq 1, port 0) Apr 26 17:09:53.360916 (XEN) Notifying guest 0:1 (virq 1, port 0) Apr 26 17:09:53.360975 (XEN) Notifying guest 0:2 (virq 1, port 0) Apr 26 17:09:53.361020 (XEN) Notifying guest 0:3 (virq 1, port 0) Apr 26 17:09:53.372921 (XEN) Notifying guest 0:4 (virq 1, port 0) Apr 26 17:09:53.372980 (XEN) Notifying guest 0:5 (virq 1, port 0) Apr 26 17:09:53.373025 (XEN) Notifying guest 0:6 (virq 1, port 0) Apr 26 17:09:53.384940 (XEN) Notifying guest 0:7 (virq 1, port 0) Apr 26 17:09:53.384999 (XEN) Notifying guest 0:8 (virq 1, port 0) Apr 26 17:09:53.385044 (XEN) Notifying guest 0:9 (virq 1, port 0) Apr 26 17:09:53.396936 (XEN) Notifying guest 0:10 (virq 1, port 0) Apr 26 17:09:53.396996 (XEN) Notifying guest 0:11 (virq 1, port 0) Apr 26 17:09:53.397041 (XEN) Notifying guest 0:12 (virq 1, port 0) Apr 26 17:09:53.408942 (XEN) Notifying guest 0:13 (virq 1, port 0) Apr 26 17:09:53.409003 (XEN) Notifying guest 0:14 (virq 1, port 0) Apr 26 17:09:53.409048 (XEN) Notifying guest 0:15 (virq 1, port 0) Apr 26 17:09:53.420917 (XEN) Notifying guest 0:16 (virq 1, port 0) Apr 26 17:09:53.420976 (XEN) Notifying guest 0:17 (virq 1, port 0) Apr 26 17:09:53.421022 (XEN) Notifying guest 0:18 (virq 1, port 0) Apr 26 17:09:53.432924 (XEN) Notifying guest 0:19 (virq 1, port 0) Apr 26 17:09:53.432984 (XEN) Notifying guest 0:20 (virq 1, port 0) Apr 26 17:09:53.433029 (XEN) Notifying guest 0:21 (virq 1, port 0) Apr 26 17:09:53.444901 (XEN) Notifying guest 0:22 (virq 1, port 0) Apr 26 17:09:53.444961 (XEN) Notifying guest 0:23 (virq 1, port 0) Apr 26 17:09:53.445006 (XEN) Notifying guest 0:24 (virq 1, port 0) Apr 26 17:09:53.456927 (XEN) Notifying guest 0:25 (virq 1, port 0) Apr 26 17:09:53.456989 (XEN) Notifying guest 0:26 (virq 1, port 0) Apr 26 17:09:53.457033 (XEN) Notifying guest 0:27 (virq 1, port 0) Apr 26 17:09:53.457077 (XEN) Notifying guest 0:28 (virq 1, port 0) Apr 26 17:09:53.468922 (XEN) Notifying guest 0:29 (virq 1, port 0) Apr 26 17:09:53.468981 (XEN) Notifying guest 0:30 (virq 1, port 0) Apr 26 17:09:53.469027 (XEN) Notifying guest 0:31 (virq 1, port 0) Apr 26 17:09:53.480921 (XEN) Notifying guest 0:32 (virq 1, port 0) Apr 26 17:09:53.480980 (XEN) Notifying guest 0:33 (virq 1, port 0) Apr 26 17:09:53.481025 (XEN) Notifying guest 0:34 (virq 1, port 0) Apr 26 17:09:53.492922 (XEN) Notifying guest 0:35 (virq 1, port 0) Apr 26 17:09:53.492981 (XEN) Notifying guest 0:36 (virq 1, port 0) Apr 26 17:09:53.504918 (XEN) Notifying guest 0:37 (virq 1, port 0) Apr 26 17:09:53.504979 (XEN) Notifying guest 0:38 (virq 1, port 0) Apr 26 17:09:53.505024 (XEN) Notifying guest 0:39 (virq 1, port 0) Apr 26 17:09:53.516928 (XEN) Notifying guest 0:40 (virq 1, port 0) Apr 26 17:09:53.516988 (XEN) Notifying guest 0:41 (virq 1, port 0) Apr 26 17:09:53.517033 (XEN) Notifying guest 0:42 (virq 1, port 0) Apr 26 17:09:53.528921 (XEN) Notifying guest 0:43 (virq 1, port 0) Apr 26 17:09:53.528981 (XEN) Notifying guest 0:44 (virq 1, port 0) Apr 26 17:09:53.529027 (XEN) Notifying guest 0:45 (virq 1, port 0) Apr 26 17:09:53.529070 (XEN) Notifying guest 0:46 (virq 1, port 0) Apr 26 17:09:53.540938 (XEN) Notifying guest 0:47 (virq 1, port 0) Apr 26 17:09:53.540997 (XEN) Notifying guest 0:48 (virq 1, port 0) Apr 26 17:09:53.541042 (XEN) Notifying guest 0:49 (virq 1, port 0) Apr 26 17:09:53.552925 (XEN) Notifying guest 0:50 (virq 1, port 0) Apr 26 17:09:53.552983 (XEN) Notifying guest 0:51 (virq 1, port 0) Apr 26 17:09:53.553029 (XEN) Notifying guest 0:52 (virq 1, port 0) Apr 26 17:09:53.564917 (XEN) Notifying guest 0:53 (virq 1, port 0) Apr 26 17:09:53.564976 (XEN) Notifying guest 0:54 (virq 1, port 0) Apr 26 17:09:53.565021 (XEN) Notifying guest 0:55 (virq 1, port 0) Apr 26 17:09:53.576941 (XEN) Notifying guest 0:56 (virq 1, port 0) Apr 26 17:09:53.577000 (XEN) Notifying guest 0:57 (virq 1, port 0) Apr 26 17:09:53.577045 (XEN) Notifying guest 0:58 (virq 1, port 0) Apr 26 17:09:53.588937 (XEN) Notifying guest 0:59 (virq 1, port 0) Apr 26 17:09:53.588995 (XEN) Notifying guest 0:60 (virq 1, port 0) Apr 26 17:09:53.589040 (XEN) Notifying guest 0:61 (virq 1, port 0) Apr 26 17:09:53.600929 (XEN) Notifying guest 0:62 (virq 1, port 0) Apr 26 17:09:53.600988 (XEN) Notifying guest 0:63 (virq 1, port 0) Apr 26 17:09:53.601033 (XEN) Notifying guest 0:64 (virq 1, port 0) Apr 26 17:09:53.612909 (XEN) Notifying guest 0:65 (virq 1, port 0) Apr 26 17:09:53.612968 (XEN) Notifying guest 0:66 (virq 1, port 0) Apr 26 17:09:53.613013 (XEN) Notifying guest 0:67 (virq 1, port 0) Apr 26 17:09:53.624910 (XEN) Notifying guest 0:68 (virq 1, port 0) Apr 26 17:09:53.624968 (XEN) Notifying guest 0:69 (virq 1, port 0) Apr 26 17:09:53.625013 (XEN) Notifying guest 0:70 (virq 1, port 0) Apr 26 17:09:53.636933 (XEN) Notifying guest 0:71 (virq 1, port 0) Apr 26 17:09:53.636992 (XEN) Notifying guest 0:72 (virq 1, port 0) Apr 26 17:09:53.637056 (XEN) Notifying guest 0:73 (virq 1, port 0) Apr 26 17:09:53.648930 (XEN) Notifying guest 0:74 (virq 1, port 0) Apr 26 17:09:53.648988 (XEN) Notifying guest 0:75 (virq 1, port 0) Apr 26 17:09:53.649034 (XEN) Notifying guest 0:76 (virq 1, port 0) Apr 26 17:09:53.660858 (XEN) Notifying guest 0:77 (virq 1, port 0) Apr 26 17:09:53.660858 (XEN) Notifying guest 0:78 (virq 1, port 0) Apr 26 17:09:53.660858 (XEN) Notifying guest 0:79 (virq 1, port 0) Apr 26 17:09:53.672944 (XEN) Notifying guest 0:80 (virq 1, port 0) Apr 26 17:09:53.673007 (XEN) Notifying guest 0:81 (virq 1, port 0) Apr 26 17:09:53.673052 (XEN) Notifying guest 0:82 (virq 1, port 0) Apr 26 17:09:53.684935 (XEN) Notifying guest 0:83 (virq 1, port 0) Apr 26 17:09:53.684994 (XEN) Notifying guest 0:84 (virq 1, port 0) Apr 26 17:09:53.685040 (XEN) Notifying guest 0:85 (virq 1, port 0) Apr 26 17:09:53.696933 (XEN) Notifying guest 0:86 (virq 1, port 0) Apr 26 17:09:53.696993 (XEN) Notifying guest 0:87 (virq 1, port 0) Apr 26 17:09:53.697038 (XEN) Notifying guest 0:88 (virq 1, port 0) Apr 26 17:09:53.708925 (XEN) Notifying guest 0:89 (virq 1, port 0) Apr 26 17:09:53.708985 (XEN) Notifying guest 0:90 (virq 1, port 0) Apr 26 17:09:53.709030 (XEN) Notifying guest 0:91 (virq 1, port 0) Apr 26 17:09:53.720927 (XEN) Notifying guest 0:92 (virq 1, port 0) Apr 26 17:09:53.720986 (XEN) Notifying guest 0:93 (virq 1, port 0) Apr 26 17:09:53.721031 (XEN) Notifying guest 0:94 (virq 1, port 0) Apr 26 17:09:53.732886 (XEN) Notifying guest 0:95 (virq 1, port 0) Apr 26 17:09:53.732946 Apr 26 17:10:00.230496 (XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input) Apr 26 17:10:00.256950 Apr 26 17:10:00.258370