Jun 27 15:18:16.835450 (XEN) Jun 27 15:18:16.835739 (XEN) VTCR_EL2: 00000000800d3590 Jun 27 15:18:16.844860 (XEN) VTTBR_EL2: 00010107fd822000 Jun 27 15:18:16.844918 (XEN) Jun 27 15:18:16.844958 (XEN) SCTLR_EL2: 0000000030cd183d Jun 27 15:18:16.845020 (XEN) HCR_EL2: 00000000807c663f Jun 27 15:18:16.845064 (XEN) TTBR0_EL2: 000001071e31f000 Jun 27 15:18:16.856848 (XEN) Jun 27 15:18:16.856901 (XEN) ESR_EL2: 0000000007e00000 Jun 27 15:18:16.856945 (XEN) HPFAR_EL2: 0000009010802300 Jun 27 15:18:16.857011 (XEN) FAR_EL2: ffff800083230100 Jun 27 15:18:16.868855 (XEN) Jun 27 15:18:16.868909 (XEN) Xen stack trace from sp=0000800ffd8bfe60: Jun 27 15:18:16.868956 (XEN) 0000800ffd8bfe70 00000a0000278f28 00000a0000329320 00000a00003625d8 Jun 27 15:18:16.880846 (XEN) 000000000000005b 0000000000000000 0000000000000000 000000000001020b Jun 27 15:18:16.880933 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:16.892858 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:16.892921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:16.904854 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:16.904916 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:16.920881 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:16.920944 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:16.928831 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:16.944872 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:16.944935 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:16.945010 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:16.952837 (XEN) Xen call trace: Jun 27 15:18:16.952893 (XEN) [<00000a000026d1ac>] domain.c#idle_loop+0x128/0x190 (PC) Jun 27 15:18:16.964858 (XEN) [<00000a000026d190>] domain.c#idle_loop+0x10c/0x190 (LR) Jun 27 15:18:16.964920 (XEN) [<00000a0000278f28>] start_secondary+0x21c/0x220 Jun 27 15:18:16.976855 (XEN) [<00000a00003625d8>] 00000a00003625d8 Jun 27 15:18:16.976914 (XEN) Jun 27 15:18:16.976954 (XEN) *** Dumping CPU92 host state: *** Jun 27 15:18:16.988847 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Jun 27 15:18:16.988911 (XEN) CPU: 92 Jun 27 15:18:16.988976 (XEN) PC: 00000a000026d1ac domain.c#idle_loop+0x128/0x190 Jun 27 15:18:17.000852 (XEN) LR: 00000a000026d190 Jun 27 15:18:17.000910 (XEN) SP: 0000800ffd8afe60 Jun 27 15:18:17.000955 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Jun 27 15:18:17.012859 (XEN) X0: 0000000000000000 X1: 0000760ffd600000 X2: 0000800ffd928048 Jun 27 15:18:17.012923 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003625a8 Jun 27 15:18:17.024852 (XEN) X6: 00000a00003625b0 X7: 0000800ffd9a8d90 X8: 0000000000000012 Jun 27 15:18:17.024916 (XEN) X9: 0000000000000000 X10: ffff800082099958 X11: 0000000000000137 Jun 27 15:18:17.036853 (XEN) X12: 00000000000003a5 X13: ffff800082041958 X14: 0000000000000000 Jun 27 15:18:17.036916 (XEN) X15: ffff80008000b720 X16: 000000000000001d X17: 0000000000000000 Jun 27 15:18:17.048860 (XEN) X18: 0000000000000006 X19: 00000a00003625b8 X20: 000000000000005c Jun 27 15:18:17.048947 (XEN) X21: 00000a0000330d80 X22: 0000000010000000 X23: 000000000000005c Jun 27 15:18:17.060859 (XEN) X24: 000000000000005c X25: 0000000000000000 X26: 0000000000000000 Jun 27 15:18:17.076778 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd8afe60 Jun 27 15:18:17.076778 (XEN) Jun 27 15:18:17.076778 (XEN) VTCR_EL2: 00000000800d3590 Jun 27 15:18:17.076778 (XEN) VTTBR_EL2: 00020107fc4fd000 Jun 27 15:18:17.076778 (XEN) Jun 27 15:18:17.076778 (XEN) SCTLR_EL2: 0000000030cd183d Jun 27 15:18:17.088787 (XEN) HCR_EL2: 00000000807c663f Jun 27 15:18:17.088787 (XEN) TTBR0_EL2: 000001071e31f000 Jun 27 15:18:17.088787 (XEN) Jun 27 15:18:17.088787 (XEN) ESR_EL2: 000000005a000ea1 Jun 27 15:18:17.100765 (XEN) HPFAR_EL2: 0000000000030300 Jun 27 15:18:17.100765 (XEN) FAR_EL2: ffff800083010100 Jun 27 15:18:17.100765 (XEN) Jun 27 15:18:17.100765 (XEN) Xen stack trace from sp=0000800ffd8afe60: Jun 27 15:18:17.100765 (XEN) 0000800ffd8afe70 00000a0000278f28 00000a0000329320 00000a00003625d8 Jun 27 15:18:17.108913 (XEN) 000000000000005c 0000000000000000 0000000000000000 000000000001020c Jun 27 15:18:17.120933 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.132914 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.133009 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.144916 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.144978 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.156916 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.156979 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.168897 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.168960 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.180923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.192894 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.192956 (XEN) Xen call trace: Jun 27 15:18:17.193024 (XEN) [<00000a000026d1ac>] domain.c#idle_loop+0x128/0x190 (PC) Jun 27 15:18:17.204912 (XEN) [<00000a000026d190>] domain.c#idle_loop+0x10c/0x190 (LR) Jun 27 15:18:17.204975 (XEN) [<00000a0000278f28>] start_secondary+0x21c/0x220 Jun 27 15:18:17.216919 (XEN) [<00000a00003625d8>] 00000a00003625d8 Jun 27 15:18:17.216979 (XEN) Jun 27 15:18:17.217042 (XEN) *** Dumping CPU93 host state: *** Jun 27 15:18:17.217088 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Jun 27 15:18:17.228926 (XEN) CPU: 93 Jun 27 15:18:17.228980 (XEN) PC: 00000a000026d1ac domain.c#idle_loop+0x128/0x190 Jun 27 15:18:17.229035 (XEN) LR: 00000a000026d190 Jun 27 15:18:17.240919 (XEN) SP: 0000800ffd8a7e60 Jun 27 15:18:17.240977 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Jun 27 15:18:17.241028 (XEN) X0: 0000000000000000 X1: 0000760ffd58c000 X2: 0000800ffd8b4048 Jun 27 15:18:17.252918 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003625a8 Jun 27 15:18:17.264925 (XEN) X6: 00000a00003625b0 X7: 0000800ffd8b6280 X8: 0000000000000012 Jun 27 15:18:17.265011 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Jun 27 15:18:17.276918 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Jun 27 15:18:17.276981 (XEN) X15: 0000000000000001 X16: 1fffe000054f6e21 X17: 0000000000000000 Jun 27 15:18:17.288909 (XEN) X18: ffff8000b00b3c58 X19: 00000a00003625b8 X20: 000000000000005d Jun 27 15:18:17.288972 (XEN) X21: 00000a0000330e00 X22: 0000000020000000 X23: 000000000000005d Jun 27 15:18:17.300930 (XEN) X24: 000000000000005d X25: 0000000000000000 X26: 0000000000000000 Jun 27 15:18:17.300992 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd8a7e60 Jun 27 15:18:17.312906 (XEN) Jun 27 15:18:17.312960 (XEN) VTCR_EL2: 00000000800d3590 Jun 27 15:18:17.313004 (XEN) VTTBR_EL2: 00010107fd822000 Jun 27 15:18:17.324922 (XEN) Jun 27 15:18:17.324976 (XEN) SCTLR_EL2: 0000000030cd183d Jun 27 15:18:17.325020 (XEN) HCR_EL2: 00000000807c663f Jun 27 15:18:17.325064 (XEN) TTBR0_EL2: 000001071e31f000 Jun 27 15:18:17.325107 (XEN) Jun 27 15:18:17.325167 (XEN) ESR_EL2: 0000000007e00000 Jun 27 15:18:17.336954 (XEN) HPFAR_EL2: 0000009010803b00 Jun 27 15:18:17.337013 (XEN) FAR_EL2: ffff8000833b0100 Jun 27 15:18:17.337057 (XEN) Jun 27 15:18:17.337096 (XEN) Xen stack trace from sp=0000800ffd8a7e60: Jun 27 15:18:17.348917 (XEN) 0000800ffd8a7e70 00000a0000278f28 00000a0000329320 00000a00003625d8 Jun 27 15:18:17.348981 (XEN) 000000000000005d 0000000000000000 0000000000000000 000000000001020d Jun 27 15:18:17.360846 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.360908 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.372896 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.384891 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.384979 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.396885 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.396948 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.408889 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.408951 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.420904 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.420966 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.432887 (XEN) Xen call trace: Jun 27 15:18:17.432943 (XEN) [<00000a000026d1ac>] domain.c#idle_loop+0x128/0x190 (PC) Jun 27 15:18:17.444895 (XEN) [<00000a000026d190>] domain.c#idle_loop+0x10c/0x190 (LR) Jun 27 15:18:17.444982 (XEN) [<00000a0000278f28>] start_secondary+0x21c/0x220 Jun 27 15:18:17.456916 (XEN) [<00000a00003625d8>] 00000a00003625d8 Jun 27 15:18:17.456976 (XEN) Jun 27 15:18:17.457016 (XEN) *** Dumping CPU94 host state: *** Jun 27 15:18:17.457060 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Jun 27 15:18:17.468919 (XEN) CPU: 94 Jun 27 15:18:17.468974 (XEN) PC: 00000a000026d1ac domain.c#idle_loop+0x128/0x190 Jun 27 15:18:17.469024 (XEN) LR: 00000a000026d190 Jun 27 15:18:17.480915 (XEN) SP: 0000800ffd83fe60 Jun 27 15:18:17.480972 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Jun 27 15:18:17.481046 (XEN) X0: 0000000000000000 X1: 0000760ffd588000 X2: 0000800ffd8b0048 Jun 27 15:18:17.492923 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003625a8 Jun 27 15:18:17.492986 (XEN) X6: 00000a00003625b0 X7: 0000800ffd8b6740 X8: 0000000000000012 Jun 27 15:18:17.504918 (XEN) X9: 0000000000000000 X10: ffff800082099958 X11: 0000000000000135 Jun 27 15:18:17.516926 (XEN) X12: 000000000000039f X13: ffff800082041958 X14: 0000000000000000 Jun 27 15:18:17.517012 (XEN) X15: ffff80008000b720 X16: 000000000000001d X17: 0000000000000000 Jun 27 15:18:17.528911 (XEN) X18: 0000000000000006 X19: 00000a00003625b8 X20: 000000000000005e Jun 27 15:18:17.528974 (XEN) X21: 00000a0000330e80 X22: 0000000040000000 X23: 000000000000005e Jun 27 15:18:17.540919 (XEN) X24: 000000000000005e X25: 0000000000000000 X26: 0000000000000000 Jun 27 15:18:17.540982 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd83fe60 Jun 27 15:18:17.552921 (XEN) Jun 27 15:18:17.552974 (XEN) VTCR_EL2: 00000000800d3590 Jun 27 15:18:17.553018 (XEN) VTTBR_EL2: 0002010720547000 Jun 27 15:18:17.553061 (XEN) Jun 27 15:18:17.564923 (XEN) SCTLR_EL2: 0000000030cd183d Jun 27 15:18:17.565003 (XEN) HCR_EL2: 00000000807c663f Jun 27 15:18:17.565050 (XEN) TTBR0_EL2: 000001071e31f000 Jun 27 15:18:17.565093 (XEN) Jun 27 15:18:17.565131 (XEN) ESR_EL2: 000000005a000ea1 Jun 27 15:18:17.576915 (XEN) HPFAR_EL2: 0000000000030300 Jun 27 15:18:17.576995 (XEN) FAR_EL2: ffff800083010100 Jun 27 15:18:17.577041 (XEN) Jun 27 15:18:17.577080 (XEN) Xen stack trace from sp=0000800ffd83fe60: Jun 27 15:18:17.588949 (XEN) 0000800ffd83fe70 00000a0000278f28 00000a0000329320 00000a00003625d8 Jun 27 15:18:17.589014 (XEN) 000000000000005e 0000000000000000 0000000000000000 000000000001020e Jun 27 15:18:17.600915 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.600977 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.612925 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.613010 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.624930 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.636913 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.636975 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.648912 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.648997 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.660919 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.660982 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.672919 (XEN) Xen call trace: Jun 27 15:18:17.672975 (XEN) [<00000a000026d1ac>] domain.c#idle_loop+0x128/0x190 (PC) Jun 27 15:18:17.684912 (XEN) [<00000a000026d190>] domain.c#idle_loop+0x10c/0x190 (LR) Jun 27 15:18:17.684975 (XEN) [<00000a0000278f28>] start_secondary+0x21c/0x220 Jun 27 15:18:17.685025 (XEN) [<00000a00003625d8>] 00000a00003625d8 Jun 27 15:18:17.696928 (XEN) Jun 27 15:18:17.696981 (XEN) *** Dumping CPU95 host state: *** Jun 27 15:18:17.697050 (XEN) ----[ Xen-4.19-unstable arm64 debug=y Not tainted ]---- Jun 27 15:18:17.708918 (XEN) CPU: 95 Jun 27 15:18:17.708972 (XEN) PC: 00000a000026d1ac domain.c#idle_loop+0x128/0x190 Jun 27 15:18:17.709022 (XEN) LR: 00000a000026d190 Jun 27 15:18:17.709071 (XEN) SP: 0000800ffd82fe60 Jun 27 15:18:17.720918 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Jun 27 15:18:17.720982 (XEN) X0: 0000000000000000 X1: 0000760ffd50e000 X2: 0000800ffd836048 Jun 27 15:18:17.732919 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a00003625a8 Jun 27 15:18:17.732982 (XEN) X6: 00000a00003625b0 X7: 0000800ffd8b6c00 X8: 0000000000000012 Jun 27 15:18:17.744918 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Jun 27 15:18:17.745004 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Jun 27 15:18:17.756929 (XEN) X15: 0000000000000001 X16: 1fffe00006226fc1 X17: 0000000000000000 Jun 27 15:18:17.768915 (XEN) X18: ffff8000ab4cbc58 X19: 00000a00003625b8 X20: 000000000000005f Jun 27 15:18:17.768979 (XEN) X21: 00000a0000330f00 X22: 0000000080000000 X23: 000000000000005f Jun 27 15:18:17.780912 (XEN) X24: 000000000000005f X25: 0000000000000000 X26: 0000000000000000 Jun 27 15:18:17.780999 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd82fe60 Jun 27 15:18:17.792928 (XEN) Jun 27 15:18:17.792981 (XEN) VTCR_EL2: 00000000800d3590 Jun 27 15:18:17.793026 (XEN) VTTBR_EL2: 00010107fd822000 Jun 27 15:18:17.793069 (XEN) Jun 27 15:18:17.793107 (XEN) SCTLR_EL2: 0000000030cd183d Jun 27 15:18:17.804912 (XEN) HCR_EL2: 00000000807c663f Jun 27 15:18:17.804970 (XEN) TTBR0_EL2: 000001071e31f000 Jun 27 15:18:17.805014 (XEN) Jun 27 15:18:17.805053 (XEN) ESR_EL2: 0000000007e00000 Jun 27 15:18:17.816915 (XEN) HPFAR_EL2: 0000009010805100 Jun 27 15:18:17.816974 (XEN) FAR_EL2: ffff800083510100 Jun 27 15:18:17.817019 (XEN) Jun 27 15:18:17.817057 (XEN) Xen stack trace from sp=0000800ffd82fe60: Jun 27 15:18:17.817103 (XEN) 0000800ffd82fe70 00000a0000278f28 00000a0000329320 00000a00003625d8 Jun 27 15:18:17.828927 (XEN) 000000000000005f 0000000000000000 0000000000000000 000000000001020f Jun 27 15:18:17.840914 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.841012 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.852896 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.852959 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.864931 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.864994 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.876921 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.888923 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.888985 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.900918 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.900980 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jun 27 15:18:17.912918 (XEN) Xen call trace: Jun 27 15:18:17.912974 (XEN) [<00000a000026d1ac>] domain.c#idle_loop+0x128/0x190 (PC) Jun 27 15:18:17.913024 (XEN) [<00000a000026d190>] domain.c#idle_loop+0x10c/0x190 (LR) Jun 27 15:18:17.924941 (XEN) [<00000a0000278f28>] start_secondary+0x21c/0x220 Jun 27 15:18:17.925002 (XEN) [<00000a00003625d8>] 00000a00003625d8 Jun 27 15:18:17.936872 (XEN) Jun 27 15:18:17.936925 Jun 27 15:18:23.691647 (XEN) 'q' pressed -> dumping domain info (now = 1614064158140) Jun 27 15:18:23.708933 (XEN) General information for domain 0: Jun 27 15:18:23.708993 (XEN) refcnt=3 dying=0 pa Jun 27 15:18:23.711281 use_count=0 Jun 27 15:18:23.720823 (XEN) nr_pages=131072 xenheap_pages=2 dirty_cpus={} max_pages=131072 Jun 27 15:18:23.720883 (XEN) handle=00000000-0000-0000-0000-000000000000 vm_assist=00000020 Jun 27 15:18:23.732889 (XEN) p2m mappings for domain 0 (vmid 1): Jun 27 15:18:23.732948 (XEN) 1G mappings: 4984 (shattered 3) Jun 27 15:18:23.732994 (XEN) 2M mappings: 1444363 (shattered 187) Jun 27 15:18:23.744884 (XEN) 4K mappings: 95760 Jun 27 15:18:23.744940 (XEN) Rangesets belonging to domain 0: Jun 27 15:18:23.744986 (XEN) Interrupts { 32, 38, 48-51 } Jun 27 15:18:23.745030 (XEN) I/O Memory { 802000000-808000000, 810000000-820000000, 838000000-844000000, 846000000-848002000, 849000000-849002000, 84a000000-84a002000, 84b000000-84b002000, 868000000-880000000, 88001f000-880058000, 881010000-883000010, 902000000-908000000, 910000000-920000000, 938000000-944000000, 946000000-948002000, 949000000-949002000, 94a000000-94a002000, 94b000000-94b002000, 968000000-980000000 } Jun 27 15:18:23.780943 (XEN) NODE affinity for domain 0: [0] Jun 27 15:18:23.792893 (XEN) VCPU information and callbacks for domain 0: Jun 27 15:18:23.792955 (XEN) UNIT0 affinities: hard={0-95} soft={0-95} Jun 27 15:18:23.793002 (XEN) VCPU0: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:23.804923 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:23.804981 (XEN) GICH_LRs (vcpu 0) mask=0 Jun 27 15:18:23.805025 (XEN) VCPU_LR[0]=0 Jun 27 15:18:23.816916 (XEN) VCPU_LR[1]=0 Jun 27 15:18:23.816971 (XEN) VCPU_LR[2]=0 Jun 27 15:18:23.817013 (XEN) VCPU_LR[3]=0 Jun 27 15:18:23.817053 (XEN) VCPU_LR[4]=0 Jun 27 15:18:23.817094 (XEN) VCPU_LR[5]=0 Jun 27 15:18:23.817134 (XEN) VCPU_LR[6]=0 Jun 27 15:18:23.828904 (XEN) VCPU_LR[7]=0 Jun 27 15:18:23.828959 (XEN) VCPU_LR[8]=0 Jun 27 15:18:23.829001 (XEN) VCPU_LR[9]=0 Jun 27 15:18:23.829042 (XEN) VCPU_LR[10]=0 Jun 27 15:18:23.829082 (XEN) VCPU_LR[11]=0 Jun 27 15:18:23.840909 (XEN) VCPU_LR[12]=0 Jun 27 15:18:23.840967 (XEN) VCPU_LR[13]=0 Jun 27 15:18:23.841010 (XEN) VCPU_LR[14]=0 Jun 27 15:18:23.841051 (XEN) VCPU_LR[15]=0 Jun 27 15:18:23.841091 (XEN) No periodic timer Jun 27 15:18:23.841132 (XEN) UNIT1 affinities: hard={0-95} soft={0-95} Jun 27 15:18:23.852965 (XEN) VCPU1: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:23.853030 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:23.864924 (XEN) GICH_LRs (vcpu 1) mask=0 Jun 27 15:18:23.864983 (XEN) VCPU_LR[0]=0 Jun 27 15:18:23.865025 (XEN) VCPU_LR[1]=0 Jun 27 15:18:23.865066 (XEN) VCPU_LR[2]=0 Jun 27 15:18:23.865105 (XEN) VCPU_LR[3]=0 Jun 27 15:18:23.865145 (XEN) VCPU_LR[4]=0 Jun 27 15:18:23.876914 (XEN) VCPU_LR[5]=0 Jun 27 15:18:23.876970 (XEN) VCPU_LR[6]=0 Jun 27 15:18:23.877012 (XEN) VCPU_LR[7]=0 Jun 27 15:18:23.877052 (XEN) VCPU_LR[8]=0 Jun 27 15:18:23.877092 (XEN) VCPU_LR[9]=0 Jun 27 15:18:23.877132 (XEN) VCPU_LR[10]=0 Jun 27 15:18:23.888918 (XEN) VCPU_LR[11]=0 Jun 27 15:18:23.888974 (XEN) VCPU_LR[12]=0 Jun 27 15:18:23.889015 (XEN) VCPU_LR[13]=0 Jun 27 15:18:23.889056 (XEN) VCPU_LR[14]=0 Jun 27 15:18:23.889096 (XEN) VCPU_LR[15]=0 Jun 27 15:18:23.889136 (XEN) No periodic timer Jun 27 15:18:23.900922 (XEN) UNIT2 affinities: hard={0-95} soft={0-95} Jun 27 15:18:23.900983 (XEN) VCPU2: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:23.912918 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:23.912977 (XEN) GICH_LRs (vcpu 2) mask=0 Jun 27 15:18:23.913022 (XEN) VCPU_LR[0]=0 Jun 27 15:18:23.913063 (XEN) VCPU_LR[1]=0 Jun 27 15:18:23.913103 (XEN) VCPU_LR[2]=0 Jun 27 15:18:23.924902 (XEN) VCPU_LR[3]=0 Jun 27 15:18:23.924958 (XEN) VCPU_LR[4]=0 Jun 27 15:18:23.925000 (XEN) VCPU_LR[5]=0 Jun 27 15:18:23.925041 (XEN) VCPU_LR[6]=0 Jun 27 15:18:23.925081 (XEN) VCPU_LR[7]=0 Jun 27 15:18:23.936910 (XEN) VCPU_LR[8]=0 Jun 27 15:18:23.936966 (XEN) VCPU_LR[9]=0 Jun 27 15:18:23.937008 (XEN) VCPU_LR[10]=0 Jun 27 15:18:23.937050 (XEN) VCPU_LR[11]=0 Jun 27 15:18:23.937091 (XEN) VCPU_LR[12]=0 Jun 27 15:18:23.937131 (XEN) VCPU_LR[13]=0 Jun 27 15:18:23.948914 (XEN) VCPU_LR[14]=0 Jun 27 15:18:23.948971 (XEN) VCPU_LR[15]=0 Jun 27 15:18:23.949013 (XEN) No periodic timer Jun 27 15:18:23.949055 (XEN) UNIT3 affinities: hard={0-95} soft={0-95} Jun 27 15:18:23.949102 (XEN) VCPU3: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:23.960936 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:23.960994 (XEN) GICH_LRs (vcpu 3) mask=0 Jun 27 15:18:23.961038 (XEN) VCPU_LR[0]=0 Jun 27 15:18:23.972927 (XEN) VCPU_LR[1]=0 Jun 27 15:18:23.972983 (XEN) VCPU_LR[2]=0 Jun 27 15:18:23.973025 (XEN) VCPU_LR[3]=0 Jun 27 15:18:23.973066 (XEN) VCPU_LR[4]=0 Jun 27 15:18:23.973106 (XEN) VCPU_LR[5]=0 Jun 27 15:18:23.973146 (XEN) VCPU_LR[6]=0 Jun 27 15:18:23.984922 (XEN) VCPU_LR[7]=0 Jun 27 15:18:23.984978 (XEN) VCPU_LR[8]=0 Jun 27 15:18:23.985019 (XEN) VCPU_LR[9]=0 Jun 27 15:18:23.985059 (XEN) VCPU_LR[10]=0 Jun 27 15:18:23.985100 (XEN) VCPU_LR[11]=0 Jun 27 15:18:23.985141 (XEN) VCPU_LR[12]=0 Jun 27 15:18:23.996919 (XEN) VCPU_LR[13]=0 Jun 27 15:18:23.996975 (XEN) VCPU_LR[14]=0 Jun 27 15:18:23.997018 (XEN) VCPU_LR[15]=0 Jun 27 15:18:23.997059 (XEN) No periodic timer Jun 27 15:18:23.997100 (XEN) UNIT4 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.008922 (XEN) VCPU4: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.008987 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.020911 (XEN) GICH_LRs (vcpu 4) mask=0 Jun 27 15:18:24.020971 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.021014 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.021055 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.021095 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.021135 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.032922 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.032979 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.033021 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.033062 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.033102 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.033143 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.044919 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.044975 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.045017 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.045096 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.045139 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.045180 (XEN) No periodic timer Jun 27 15:18:24.056914 (XEN) UNIT5 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.056976 (XEN) VCPU5: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.068909 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.068969 (XEN) GICH_LRs (vcpu 5) mask=0 Jun 27 15:18:24.069013 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.069055 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.069096 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.080924 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.080980 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.081022 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.081063 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.081104 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.081144 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.092920 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.092976 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.093019 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.093060 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.093101 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.104820 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.104851 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.104875 (XEN) No periodic timer Jun 27 15:18:24.104898 (XEN) UNIT6 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.104946 (XEN) VCPU6: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.116920 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.116979 (XEN) GICH_LRs (vcpu 6) mask=0 Jun 27 15:18:24.117024 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.128919 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.128975 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.129016 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.129057 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.129097 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.129137 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.140913 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.140970 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.141012 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.141053 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.141094 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.141134 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.152918 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.152974 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.153016 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.153057 (XEN) No periodic timer Jun 27 15:18:24.153098 (XEN) UNIT7 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.164927 (XEN) VCPU7: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.164991 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.165036 (XEN) GICH_LRs (vcpu 7) mask=0 Jun 27 15:18:24.176908 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.176964 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.177006 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.177047 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.177087 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.188922 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.188977 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.189019 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.189060 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.189101 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.200904 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.200961 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.201003 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.201044 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.201084 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.201124 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.212918 (XEN) No periodic timer Jun 27 15:18:24.212976 (XEN) UNIT8 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.213024 (XEN) VCPU8: CPU34 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.224920 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.224979 (XEN) GICH_LRs (vcpu 8) mask=0 Jun 27 15:18:24.225023 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.225064 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.225104 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.236914 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.236970 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.237012 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.237052 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.237092 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.237132 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.248917 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.249009 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.249055 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.249096 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.249136 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.249176 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.260917 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.260974 (XEN) No periodic timer Jun 27 15:18:24.261017 (XEN) UNIT9 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.261064 (XEN) VCPU9: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.272927 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.272985 (XEN) GICH_LRs (vcpu 9) mask=0 Jun 27 15:18:24.273029 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.284908 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.284964 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.285006 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.285046 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.285086 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.285126 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.296912 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.296968 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.297010 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.297051 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.297092 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.297132 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.308916 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.308972 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.309014 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.309054 (XEN) No periodic timer Jun 27 15:18:24.309096 (XEN) UNIT10 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.320918 (XEN) VCPU10: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.320981 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.332930 (XEN) GICH_LRs (vcpu 10) mask=0 Jun 27 15:18:24.332988 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.333031 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.333072 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.333112 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.344919 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.344977 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.345019 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.345060 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.345100 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.345141 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.356915 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.356973 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.357016 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.357057 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.357097 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.357137 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.368921 (XEN) No periodic timer Jun 27 15:18:24.368978 (XEN) UNIT11 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.369026 (XEN) VCPU11: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.380918 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.380977 (XEN) GICH_LRs (vcpu 11) mask=0 Jun 27 15:18:24.381021 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.381062 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.381102 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.392920 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.392976 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.393018 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.393059 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.393099 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.393140 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.404924 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.404980 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.405023 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.405063 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.405104 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.405144 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.416920 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.416975 (XEN) No periodic timer Jun 27 15:18:24.417018 (XEN) UNIT12 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.417064 (XEN) VCPU12: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.428921 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.428979 (XEN) GICH_LRs (vcpu 12) mask=0 Jun 27 15:18:24.429024 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.440907 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.440963 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.441005 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.441046 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.441122 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.452912 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.452968 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.453010 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.453051 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.453092 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.453132 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.464932 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.464988 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.465030 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.465071 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.465111 (XEN) No periodic timer Jun 27 15:18:24.465152 (XEN) UNIT13 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.476932 (XEN) VCPU13: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.476996 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.488918 (XEN) GICH_LRs (vcpu 13) mask=0 Jun 27 15:18:24.488976 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.489019 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.489061 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.489102 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.500875 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.500931 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.500973 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.501013 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.501053 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.501093 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.512917 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.512974 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.513016 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.513057 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.513097 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.513138 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.524928 (XEN) No periodic timer Jun 27 15:18:24.524985 (XEN) UNIT14 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.525033 (XEN) VCPU14: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.536910 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.536969 (XEN) GICH_LRs (vcpu 14) mask=0 Jun 27 15:18:24.537013 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.537054 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.537095 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.548918 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.548973 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.549015 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.549056 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.549096 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.549136 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.560916 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.560972 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.561014 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.561054 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.561095 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.572842 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.572842 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.572842 (XEN) No periodic timer Jun 27 15:18:24.572842 (XEN) UNIT15 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.584934 (XEN) VCPU15: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.585003 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.585110 (XEN) GICH_LRs (vcpu 15) mask=0 Jun 27 15:18:24.596915 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.596971 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.597013 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.597054 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.597094 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.597134 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.608923 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.608978 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.609020 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.609061 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.609101 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.609141 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.620918 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.620974 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.621016 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.621057 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.621097 (XEN) No periodic timer Jun 27 15:18:24.621138 (XEN) UNIT16 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.632924 (XEN) VCPU16: CPU67 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.632988 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.644906 (XEN) GICH_LRs (vcpu 16) mask=0 Jun 27 15:18:24.645001 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.645047 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.645088 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.645128 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.656928 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.656984 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.657025 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.657066 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.657106 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.657146 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.668928 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.668984 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.669026 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.669067 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.669108 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.669149 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.680918 (XEN) No periodic timer Jun 27 15:18:24.680975 (XEN) UNIT17 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.681023 (XEN) VCPU17: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.692903 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.692961 (XEN) GICH_LRs (vcpu 17) mask=0 Jun 27 15:18:24.693005 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.704867 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.704867 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.704867 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.704867 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.704867 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.704867 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.716928 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.716991 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.717033 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.717074 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.717114 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.717154 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.728905 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.728962 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.729004 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.729045 (XEN) No periodic timer Jun 27 15:18:24.729086 (XEN) UNIT18 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.740918 (XEN) VCPU18: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.740982 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.741027 (XEN) GICH_LRs (vcpu 18) mask=0 Jun 27 15:18:24.752923 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.752978 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.753021 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.753062 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.753102 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.753142 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.764922 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.764977 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.765020 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.765061 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.765101 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.765141 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.776921 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.776977 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.777019 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.777060 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.777100 (XEN) No periodic timer Jun 27 15:18:24.788899 (XEN) UNIT19 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.788961 (XEN) VCPU19: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.789012 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.800917 (XEN) GICH_LRs (vcpu 19) mask=0 Jun 27 15:18:24.800975 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.801017 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.801057 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.801097 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.812899 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.812955 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.812996 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.813036 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.813076 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.824898 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.824954 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.824996 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.825036 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.825076 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.825117 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.836908 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.836964 (XEN) No periodic timer Jun 27 15:18:24.837007 (XEN) UNIT20 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.837089 (XEN) VCPU20: CPU36 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.848909 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.848968 (XEN) GICH_LRs (vcpu 20) mask=0 Jun 27 15:18:24.849013 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.860905 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.860961 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.861003 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.861043 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.861083 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.861123 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.872912 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.872969 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.873011 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.873052 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.873092 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.873132 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.884913 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.884969 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.885011 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.885052 (XEN) No periodic timer Jun 27 15:18:24.885093 (XEN) UNIT21 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.896913 (XEN) VCPU21: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.896977 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.897022 (XEN) GICH_LRs (vcpu 21) mask=0 Jun 27 15:18:24.908911 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.908967 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.909008 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.909049 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.909088 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.920905 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.920962 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.921005 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.921045 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.921085 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.921125 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.932903 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.932960 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.933002 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.933043 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.933083 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.933123 (XEN) No periodic timer Jun 27 15:18:24.944889 (XEN) UNIT22 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.944950 (XEN) VCPU22: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:24.956909 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:24.956967 (XEN) GICH_LRs (vcpu 22) mask=0 Jun 27 15:18:24.957012 (XEN) VCPU_LR[0]=0 Jun 27 15:18:24.957052 (XEN) VCPU_LR[1]=0 Jun 27 15:18:24.957092 (XEN) VCPU_LR[2]=0 Jun 27 15:18:24.968894 (XEN) VCPU_LR[3]=0 Jun 27 15:18:24.968950 (XEN) VCPU_LR[4]=0 Jun 27 15:18:24.968992 (XEN) VCPU_LR[5]=0 Jun 27 15:18:24.969033 (XEN) VCPU_LR[6]=0 Jun 27 15:18:24.969072 (XEN) VCPU_LR[7]=0 Jun 27 15:18:24.969112 (XEN) VCPU_LR[8]=0 Jun 27 15:18:24.980927 (XEN) VCPU_LR[9]=0 Jun 27 15:18:24.980983 (XEN) VCPU_LR[10]=0 Jun 27 15:18:24.981025 (XEN) VCPU_LR[11]=0 Jun 27 15:18:24.981066 (XEN) VCPU_LR[12]=0 Jun 27 15:18:24.981107 (XEN) VCPU_LR[13]=0 Jun 27 15:18:24.981147 (XEN) VCPU_LR[14]=0 Jun 27 15:18:24.992927 (XEN) VCPU_LR[15]=0 Jun 27 15:18:24.992983 (XEN) No periodic timer Jun 27 15:18:24.993025 (XEN) UNIT23 affinities: hard={0-95} soft={0-95} Jun 27 15:18:24.993072 (XEN) VCPU23: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.004932 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.004991 (XEN) GICH_LRs (vcpu 23) mask=0 Jun 27 15:18:25.005037 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.016921 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.016978 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.017020 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.017061 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.017103 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.017143 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.028904 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.028961 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.029004 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.029045 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.029086 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.029126 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.040914 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.040970 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.041050 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.041094 (XEN) No periodic timer Jun 27 15:18:25.041136 (XEN) UNIT24 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.052924 (XEN) VCPU24: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.052989 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.053035 (XEN) GICH_LRs (vcpu 24) mask=0 Jun 27 15:18:25.064918 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.064974 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.065016 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.065057 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.065098 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.076911 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.076968 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.077010 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.077051 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.077091 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.088898 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.088955 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.088998 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.089040 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.089081 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.089121 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.100915 (XEN) No periodic timer Jun 27 15:18:25.100971 (XEN) UNIT25 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.101019 (XEN) VCPU25: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.112920 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.112979 (XEN) GICH_LRs (vcpu 25) mask=0 Jun 27 15:18:25.113024 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.113064 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.113106 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.124920 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.124975 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.125017 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.125058 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.125099 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.125139 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.136917 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.136972 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.137015 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.137055 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.137096 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.137136 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.148901 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.148956 (XEN) No periodic timer Jun 27 15:18:25.148999 (XEN) UNIT26 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.149046 (XEN) VCPU26: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.160935 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.160993 (XEN) GICH_LRs (vcpu 26) mask=0 Jun 27 15:18:25.161037 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.172914 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.172969 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.173011 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.173053 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.173094 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.173134 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.184912 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.184967 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.185010 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.185051 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.185091 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.185132 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.196897 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.196953 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.196995 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.197036 (XEN) No periodic timer Jun 27 15:18:25.197077 (XEN) UNIT27 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.208898 (XEN) VCPU27: CPU9 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.208961 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.220908 (XEN) GICH_LRs (vcpu 27) mask=0 Jun 27 15:18:25.220967 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.221009 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.221050 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.221090 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.232905 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.232961 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.233004 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.233044 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.233084 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.233124 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.244948 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.245005 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.245048 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.245088 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.245128 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.245168 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.256912 (XEN) No periodic timer Jun 27 15:18:25.256969 (XEN) UNIT28 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.257017 (XEN) VCPU28: CPU70 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.268895 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.268955 (XEN) GICH_LRs (vcpu 28) mask=0 Jun 27 15:18:25.268999 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.269040 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.280914 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.280971 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.281013 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.281054 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.281094 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.281134 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.292913 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.292970 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.293012 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.293053 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.293093 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.293133 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.304925 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.304981 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.305023 (XEN) No periodic timer Jun 27 15:18:25.305065 (XEN) UNIT29 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.305111 (XEN) VCPU29: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.316920 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.316978 (XEN) GICH_LRs (vcpu 29) mask=0 Jun 27 15:18:25.317023 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.328903 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.328958 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.329000 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.329040 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.329080 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.340926 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.340982 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.341024 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.341065 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.341106 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.341146 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.352919 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.352975 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.353017 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.353058 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.353099 (XEN) No periodic timer Jun 27 15:18:25.353140 (XEN) UNIT30 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.364922 (XEN) VCPU30: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.364986 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.376920 (XEN) GICH_LRs (vcpu 30) mask=0 Jun 27 15:18:25.376977 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.377020 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.377060 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.377100 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.388901 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.388956 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.388999 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.389039 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.389079 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.389119 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.400891 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.400947 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.400989 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.401030 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.401071 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.401112 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.412917 (XEN) No periodic timer Jun 27 15:18:25.412973 (XEN) UNIT31 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.413021 (XEN) VCPU31: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.424920 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.424978 (XEN) GICH_LRs (vcpu 31) mask=0 Jun 27 15:18:25.425023 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.425064 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.436911 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.436967 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.437009 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.437088 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.437132 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.437172 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.448879 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.448936 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.448978 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.449019 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.449059 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.460915 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.460972 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.461015 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.461056 (XEN) No periodic timer Jun 27 15:18:25.461098 (XEN) UNIT32 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.472920 (XEN) VCPU32: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.472985 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.473030 (XEN) GICH_LRs (vcpu 32) mask=0 Jun 27 15:18:25.484916 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.484973 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.485015 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.485056 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.485096 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.485136 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.496925 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.496981 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.497023 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.497063 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.497104 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.497144 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.508888 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.508943 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.508985 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.509026 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.509066 (XEN) No periodic timer Jun 27 15:18:25.520908 (XEN) UNIT33 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.520970 (XEN) VCPU33: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.521021 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.532929 (XEN) GICH_LRs (vcpu 33) mask=0 Jun 27 15:18:25.532986 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.533029 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.533070 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.533109 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.544911 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.544967 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.545009 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.545049 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.545091 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.545131 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.556920 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.556975 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.557018 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.557059 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.557099 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.557139 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.568866 (XEN) No periodic timer Jun 27 15:18:25.568925 (XEN) UNIT34 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.568972 (XEN) VCPU34: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.580918 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.580977 (XEN) GICH_LRs (vcpu 34) mask=0 Jun 27 15:18:25.581021 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.592917 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.592973 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.593015 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.593055 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.593096 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.593136 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.604925 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.604981 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.605024 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.605065 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.605105 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.605146 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.616910 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.616967 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.617009 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.617050 (XEN) No periodic timer Jun 27 15:18:25.617092 (XEN) UNIT35 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.628868 (XEN) VCPU35: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.628917 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.628961 (XEN) GICH_LRs (vcpu 35) mask=0 Jun 27 15:18:25.640917 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.641011 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.641055 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.641096 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.641137 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.652927 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.652983 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.653025 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.653066 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.653106 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.653145 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.664915 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.664971 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.665014 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.665054 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.665095 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.665135 (XEN) No periodic timer Jun 27 15:18:25.676910 (XEN) UNIT36 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.676971 (XEN) VCPU36: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.677022 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.688865 (XEN) GICH_LRs (vcpu 36) mask=0 Jun 27 15:18:25.688897 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.688920 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.688974 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.689014 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.700917 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.700972 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.701014 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.701054 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.701095 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.712911 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.712967 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.713010 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.713050 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.713090 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.713130 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.724917 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.724972 (XEN) No periodic timer Jun 27 15:18:25.725016 (XEN) UNIT37 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.725062 (XEN) VCPU37: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.736922 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.736981 (XEN) GICH_LRs (vcpu 37) mask=0 Jun 27 15:18:25.737025 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.748832 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.748863 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.748886 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.748908 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.748930 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.748952 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.760915 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.760971 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.761013 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.761053 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.761094 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.761135 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.772917 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.772973 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.773015 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.773056 (XEN) No periodic timer Jun 27 15:18:25.773097 (XEN) UNIT38 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.784920 (XEN) VCPU38: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.784985 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.785030 (XEN) GICH_LRs (vcpu 38) mask=0 Jun 27 15:18:25.796911 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.796966 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.797008 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.797048 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.797088 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.808839 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.808870 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.808893 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.808914 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.808936 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.808958 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.820876 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.820931 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.820974 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.821015 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.821055 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.821095 (XEN) No periodic timer Jun 27 15:18:25.832873 (XEN) UNIT39 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.832934 (XEN) VCPU39: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.844800 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.844800 (XEN) GICH_LRs (vcpu 39) mask=0 Jun 27 15:18:25.844800 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.844800 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.844800 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.856883 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.856942 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.856984 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.857025 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.857065 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.857105 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.868835 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.868865 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.868888 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.868910 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.868932 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.880873 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.880929 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.880971 (XEN) No periodic timer Jun 27 15:18:25.881013 (XEN) UNIT40 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.881059 (XEN) VCPU40: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.892886 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.892944 (XEN) GICH_LRs (vcpu 40) mask=0 Jun 27 15:18:25.892988 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.904931 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.904986 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.905028 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.905069 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.905109 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.905149 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.916912 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.916967 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.917009 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.917050 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.917090 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.917130 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.928865 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.928896 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.928919 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.928941 (XEN) No periodic timer Jun 27 15:18:25.928964 (XEN) UNIT41 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.940912 (XEN) VCPU41: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:25.940976 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:25.952920 (XEN) GICH_LRs (vcpu 41) mask=0 Jun 27 15:18:25.952980 (XEN) VCPU_LR[0]=0 Jun 27 15:18:25.953023 (XEN) VCPU_LR[1]=0 Jun 27 15:18:25.953064 (XEN) VCPU_LR[2]=0 Jun 27 15:18:25.953104 (XEN) VCPU_LR[3]=0 Jun 27 15:18:25.953143 (XEN) VCPU_LR[4]=0 Jun 27 15:18:25.964775 (XEN) VCPU_LR[5]=0 Jun 27 15:18:25.964775 (XEN) VCPU_LR[6]=0 Jun 27 15:18:25.964775 (XEN) VCPU_LR[7]=0 Jun 27 15:18:25.964775 (XEN) VCPU_LR[8]=0 Jun 27 15:18:25.964775 (XEN) VCPU_LR[9]=0 Jun 27 15:18:25.976781 (XEN) VCPU_LR[10]=0 Jun 27 15:18:25.976781 (XEN) VCPU_LR[11]=0 Jun 27 15:18:25.976781 (XEN) VCPU_LR[12]=0 Jun 27 15:18:25.976781 (XEN) VCPU_LR[13]=0 Jun 27 15:18:25.976781 (XEN) VCPU_LR[14]=0 Jun 27 15:18:25.976781 (XEN) VCPU_LR[15]=0 Jun 27 15:18:25.988793 (XEN) No periodic timer Jun 27 15:18:25.988793 (XEN) UNIT42 affinities: hard={0-95} soft={0-95} Jun 27 15:18:25.988793 (XEN) VCPU42: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.000784 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.000784 (XEN) GICH_LRs (vcpu 42) mask=0 Jun 27 15:18:26.000784 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.000784 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.012782 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.012782 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.012782 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.012782 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.012782 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.012782 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.024853 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.024853 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.024853 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.024853 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.024853 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.024853 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.036982 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.037095 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.037141 (XEN) No periodic timer Jun 27 15:18:26.037184 (XEN) UNIT43 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.037230 (XEN) VCPU43: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.048879 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.048911 (XEN) GICH_LRs (vcpu 43) mask=0 Jun 27 15:18:26.048936 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.060920 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.060976 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.061018 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.061059 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.061101 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.061141 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.072922 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.072978 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.073020 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.073062 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.073104 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.084904 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.084963 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.085006 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.085047 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.085088 (XEN) No periodic timer Jun 27 15:18:26.096921 (XEN) UNIT44 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.096983 (XEN) VCPU44: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.097034 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.108893 (XEN) GICH_LRs (vcpu 44) mask=0 Jun 27 15:18:26.108925 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.108949 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.108971 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.108994 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.120927 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.120982 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.121024 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.121065 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.121105 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.121145 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.132919 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.132975 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.133017 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.133058 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.133098 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.133139 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.148928 (XEN) No periodic timer Jun 27 15:18:26.148986 (XEN) UNIT45 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.149035 (XEN) VCPU45: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.149085 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.156904 (XEN) GICH_LRs (vcpu 45) mask=0 Jun 27 15:18:26.156962 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.157006 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.168896 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.168927 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.168951 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.168974 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.168996 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.169018 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.180914 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.180972 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.181015 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.181057 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.181098 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.181139 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.192912 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.192968 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.193012 (XEN) No periodic timer Jun 27 15:18:26.193055 (XEN) UNIT46 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.193102 (XEN) VCPU46: CPU73 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.204924 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.204983 (XEN) GICH_LRs (vcpu 46) mask=0 Jun 27 15:18:26.216917 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.216974 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.217017 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.217058 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.217099 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.228906 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.228938 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.228962 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.228985 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.229008 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.229055 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.240918 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.240975 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.241017 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.241058 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.241099 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.241139 (XEN) No periodic timer Jun 27 15:18:26.252923 (XEN) UNIT47 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.252986 (XEN) VCPU47: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.253038 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.264928 (XEN) GICH_LRs (vcpu 47) mask=0 Jun 27 15:18:26.264988 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.265032 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.265074 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.265115 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.276915 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.276972 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.277015 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.277057 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.277098 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.277140 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.288920 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.288951 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.288975 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.288998 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.289021 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.300839 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.300839 (XEN) No periodic timer Jun 27 15:18:26.300839 (XEN) UNIT48 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.300839 (XEN) VCPU48: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.312923 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.312988 (XEN) GICH_LRs (vcpu 48) mask=0 Jun 27 15:18:26.313034 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.313075 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.324919 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.324976 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.325019 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.325061 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.325102 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.325143 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.336916 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.336973 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.337016 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.337058 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.337099 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.348925 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.348956 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.348980 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.349003 (XEN) No periodic timer Jun 27 15:18:26.349027 (XEN) UNIT49 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.364950 (XEN) VCPU49: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.365016 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.365062 (XEN) GICH_LRs (vcpu 49) mask=0 Jun 27 15:18:26.365107 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.376917 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.376974 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.377018 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.377059 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.377100 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.377141 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.388913 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.388971 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.389014 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.389055 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.389096 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.389137 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.400919 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.400976 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.401020 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.401062 (XEN) No periodic timer Jun 27 15:18:26.401104 (XEN) UNIT50 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.412913 (XEN) VCPU50: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.412978 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.413024 (XEN) GICH_LRs (vcpu 50) mask=0 Jun 27 15:18:26.424920 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.424977 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.425021 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.425062 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.425103 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.436920 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.437015 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.437061 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.437102 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.437142 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.437182 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.448913 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.448970 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.449013 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.449054 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.449094 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.449134 (XEN) No periodic timer Jun 27 15:18:26.460926 (XEN) UNIT51 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.460987 (XEN) VCPU51: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.461038 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.472911 (XEN) GICH_LRs (vcpu 51) mask=0 Jun 27 15:18:26.472969 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.473011 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.473052 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.484913 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.484969 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.485011 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.485052 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.485091 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.485131 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.496915 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.496971 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.497014 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.497055 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.497095 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.497135 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.508927 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.508982 (XEN) No periodic timer Jun 27 15:18:26.509025 (XEN) UNIT52 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.509072 (XEN) VCPU52: CPU73 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.520922 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.520980 (XEN) GICH_LRs (vcpu 52) mask=0 Jun 27 15:18:26.521024 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.532915 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.532971 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.533012 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.533053 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.533092 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.533133 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.544926 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.544982 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.545025 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.545067 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.545107 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.545148 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.556921 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.556977 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.557020 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.557061 (XEN) No periodic timer Jun 27 15:18:26.557102 (XEN) UNIT53 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.568918 (XEN) VCPU53: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.568982 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.569027 (XEN) GICH_LRs (vcpu 53) mask=0 Jun 27 15:18:26.580917 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.580973 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.581015 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.581056 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.581096 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.592908 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.592965 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.593008 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.593048 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.593089 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.604915 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.604972 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.605014 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.605055 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.605096 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.605136 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.616908 (XEN) No periodic timer Jun 27 15:18:26.616964 (XEN) UNIT54 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.617012 (XEN) VCPU54: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.628929 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.628987 (XEN) GICH_LRs (vcpu 54) mask=0 Jun 27 15:18:26.629032 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.629109 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.629152 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.640927 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.640982 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.641023 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.641064 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.641105 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.641145 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.652932 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.652987 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.653028 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.653069 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.653109 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.664920 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.664978 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.665020 (XEN) No periodic timer Jun 27 15:18:26.665062 (XEN) UNIT55 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.665108 (XEN) VCPU55: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.676927 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.676986 (XEN) GICH_LRs (vcpu 55) mask=0 Jun 27 15:18:26.677030 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.688918 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.688974 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.689016 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.689057 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.689096 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.689136 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.700917 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.700972 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.701013 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.701054 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.701094 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.701134 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.712923 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.712979 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.713021 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.713062 (XEN) No periodic timer Jun 27 15:18:26.713103 (XEN) UNIT56 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.724914 (XEN) VCPU56: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.724978 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.736920 (XEN) GICH_LRs (vcpu 56) mask=0 Jun 27 15:18:26.736978 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.737021 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.737062 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.737103 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.748926 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.748983 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.749026 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.749067 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.749107 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.749148 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.760920 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.760976 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.761018 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.761058 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.761098 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.761137 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.772922 (XEN) No periodic timer Jun 27 15:18:26.772979 (XEN) UNIT57 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.773027 (XEN) VCPU57: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.784926 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.784990 (XEN) GICH_LRs (vcpu 57) mask=0 Jun 27 15:18:26.785038 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.785061 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.796823 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.796854 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.796878 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.796900 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.796922 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.796944 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.808931 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.808987 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.809030 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.809072 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.809112 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.809152 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.820913 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.820970 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.821012 (XEN) No periodic timer Jun 27 15:18:26.821054 (XEN) UNIT58 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.821100 (XEN) VCPU58: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.832971 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.833030 (XEN) GICH_LRs (vcpu 58) mask=0 Jun 27 15:18:26.833075 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.844922 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.844977 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.845019 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.845060 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.845100 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.856916 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.856971 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.857014 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.857055 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.857096 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.857136 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.868923 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.868979 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.869021 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.869062 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.869102 (XEN) No periodic timer Jun 27 15:18:26.880914 (XEN) UNIT59 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.880976 (XEN) VCPU59: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.881027 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.892930 (XEN) GICH_LRs (vcpu 59) mask=0 Jun 27 15:18:26.892988 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.893031 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.893071 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.893110 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.904926 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.904981 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.905022 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.905062 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.905103 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.905144 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.916919 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.916974 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.917016 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.917057 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.917098 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.917138 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.928913 (XEN) No periodic timer Jun 27 15:18:26.928970 (XEN) UNIT60 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.929018 (XEN) VCPU60: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.940921 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.940979 (XEN) GICH_LRs (vcpu 60) mask=0 Jun 27 15:18:26.941024 (XEN) VCPU_LR[0]=0 Jun 27 15:18:26.941065 (XEN) VCPU_LR[1]=0 Jun 27 15:18:26.952924 (XEN) VCPU_LR[2]=0 Jun 27 15:18:26.952980 (XEN) VCPU_LR[3]=0 Jun 27 15:18:26.953022 (XEN) VCPU_LR[4]=0 Jun 27 15:18:26.953063 (XEN) VCPU_LR[5]=0 Jun 27 15:18:26.953103 (XEN) VCPU_LR[6]=0 Jun 27 15:18:26.953143 (XEN) VCPU_LR[7]=0 Jun 27 15:18:26.964920 (XEN) VCPU_LR[8]=0 Jun 27 15:18:26.964977 (XEN) VCPU_LR[9]=0 Jun 27 15:18:26.965019 (XEN) VCPU_LR[10]=0 Jun 27 15:18:26.965060 (XEN) VCPU_LR[11]=0 Jun 27 15:18:26.965101 (XEN) VCPU_LR[12]=0 Jun 27 15:18:26.965141 (XEN) VCPU_LR[13]=0 Jun 27 15:18:26.976908 (XEN) VCPU_LR[14]=0 Jun 27 15:18:26.976964 (XEN) VCPU_LR[15]=0 Jun 27 15:18:26.977006 (XEN) No periodic timer Jun 27 15:18:26.977047 (XEN) UNIT61 affinities: hard={0-95} soft={0-95} Jun 27 15:18:26.988921 (XEN) VCPU61: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:26.988986 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:26.989031 (XEN) GICH_LRs (vcpu 61) mask=0 Jun 27 15:18:27.000922 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.000978 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.001021 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.001062 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.001103 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.001143 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.012928 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.012983 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.013025 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.013066 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.013107 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.013148 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.024899 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.024955 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.024997 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.025074 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.025118 (XEN) No periodic timer Jun 27 15:18:27.036926 (XEN) UNIT62 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.036989 (XEN) VCPU62: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.037040 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.048912 (XEN) GICH_LRs (vcpu 62) mask=0 Jun 27 15:18:27.048970 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.049013 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.049054 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.049094 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.060924 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.060980 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.061022 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.061064 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.061104 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.061145 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.072914 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.072970 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.073013 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.073054 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.073095 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.073135 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.084924 (XEN) No periodic timer Jun 27 15:18:27.084980 (XEN) UNIT63 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.085029 (XEN) VCPU63: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.096927 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.096986 (XEN) GICH_LRs (vcpu 63) mask=0 Jun 27 15:18:27.097031 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.097072 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.108902 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.108958 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.109000 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.109041 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.109080 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.120858 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.120914 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.120956 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.120996 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.121036 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.121076 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.132905 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.132961 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.133004 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.133045 (XEN) No periodic timer Jun 27 15:18:27.133087 (XEN) UNIT64 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.144919 (XEN) VCPU64: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.144983 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.145028 (XEN) GICH_LRs (vcpu 64) mask=0 Jun 27 15:18:27.156927 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.156982 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.157024 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.157064 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.157105 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.168924 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.168980 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.169023 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.169063 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.169103 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.169143 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.180915 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.180972 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.181014 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.181054 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.181095 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.181135 (XEN) No periodic timer Jun 27 15:18:27.192912 (XEN) UNIT65 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.192974 (XEN) VCPU65: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.193024 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.204920 (XEN) GICH_LRs (vcpu 65) mask=0 Jun 27 15:18:27.204977 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.205020 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.205061 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.205101 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.216889 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.216944 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.216985 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.217026 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.217066 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.217106 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.228910 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.229001 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.229047 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.229088 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.229128 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.240915 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.240971 (XEN) No periodic timer Jun 27 15:18:27.241015 (XEN) UNIT66 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.241061 (XEN) VCPU66: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.252923 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.252981 (XEN) GICH_LRs (vcpu 66) mask=0 Jun 27 15:18:27.253025 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.264927 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.264983 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.265025 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.265066 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.265107 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.265147 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.276913 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.276969 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.277011 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.277051 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.277091 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.277131 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.288914 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.288969 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.289011 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.289051 (XEN) No periodic timer Jun 27 15:18:27.289092 (XEN) UNIT67 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.300909 (XEN) VCPU67: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.300972 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.301017 (XEN) GICH_LRs (vcpu 67) mask=0 Jun 27 15:18:27.312939 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.312995 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.313037 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.313078 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.313119 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.324917 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.324973 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.325016 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.325056 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.325097 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.325136 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.336910 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.336966 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.337009 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.337049 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.337090 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.337130 (XEN) No periodic timer Jun 27 15:18:27.348917 (XEN) UNIT68 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.348979 (XEN) VCPU68: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.349030 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.360909 (XEN) GICH_LRs (vcpu 68) mask=0 Jun 27 15:18:27.360967 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.361010 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.361051 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.372931 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.372986 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.373029 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.373070 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.373111 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.373151 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.384919 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.384975 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.385017 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.385057 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.385098 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.396909 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.396965 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.397007 (XEN) No periodic timer Jun 27 15:18:27.397049 (XEN) UNIT69 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.397095 (XEN) VCPU69: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.408936 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.408994 (XEN) GICH_LRs (vcpu 69) mask=0 Jun 27 15:18:27.409039 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.420917 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.420973 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.421015 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.421056 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.421096 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.421173 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.432917 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.432973 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.433015 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.433056 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.433096 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.433136 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.444914 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.444970 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.445011 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.445052 (XEN) No periodic timer Jun 27 15:18:27.445093 (XEN) UNIT70 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.456908 (XEN) VCPU70: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.456972 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.468920 (XEN) GICH_LRs (vcpu 70) mask=0 Jun 27 15:18:27.468979 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.469021 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.469062 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.469102 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.469143 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.480920 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.480976 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.481019 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.481060 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.481100 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.492914 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.492970 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.493013 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.493054 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.493094 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.493134 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.504917 (XEN) No periodic timer Jun 27 15:18:27.504973 (XEN) UNIT71 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.505021 (XEN) VCPU71: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.516915 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.516973 (XEN) GICH_LRs (vcpu 71) mask=0 Jun 27 15:18:27.517018 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.517059 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.528924 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.528980 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.529022 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.529062 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.529103 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.529142 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.540916 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.540972 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.541015 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.541055 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.541096 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.541137 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.552912 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.552969 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.553011 (XEN) No periodic timer Jun 27 15:18:27.553053 (XEN) UNIT72 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.553099 (XEN) VCPU72: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.564930 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.564988 (XEN) GICH_LRs (vcpu 72) mask=0 Jun 27 15:18:27.565033 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.576928 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.576983 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.577025 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.577066 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.577106 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.577145 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.588914 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.588969 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.589011 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.589051 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.589091 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.589131 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.600914 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.600969 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.601011 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.601051 (XEN) No periodic timer Jun 27 15:18:27.601092 (XEN) UNIT73 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.612912 (XEN) VCPU73: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.612976 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.624919 (XEN) GICH_LRs (vcpu 73) mask=0 Jun 27 15:18:27.624977 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.625019 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.625097 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.625141 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.636911 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.636967 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.637009 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.637049 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.637088 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.637128 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.648909 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.648964 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.649006 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.649048 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.649089 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.649129 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.660918 (XEN) No periodic timer Jun 27 15:18:27.660974 (XEN) UNIT74 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.661022 (XEN) VCPU74: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.672884 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.672942 (XEN) GICH_LRs (vcpu 74) mask=0 Jun 27 15:18:27.672986 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.673028 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.684884 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.684940 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.684982 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.685023 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.685064 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.685104 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.696872 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.696929 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.696970 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.697011 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.697051 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.697092 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.708866 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.708922 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.708965 (XEN) No periodic timer Jun 27 15:18:27.709007 (XEN) UNIT75 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.709053 (XEN) VCPU75: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.720891 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.720949 (XEN) GICH_LRs (vcpu 75) mask=0 Jun 27 15:18:27.732913 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.732970 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.733012 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.733053 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.733095 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.733135 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.744908 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.744965 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.745007 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.745048 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.745089 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.756910 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.756968 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.757011 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.757052 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.757092 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.757132 (XEN) No periodic timer Jun 27 15:18:27.768917 (XEN) UNIT76 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.768979 (XEN) VCPU76: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.769030 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.780921 (XEN) GICH_LRs (vcpu 76) mask=0 Jun 27 15:18:27.780978 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.781021 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.781062 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.781102 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.792925 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.792980 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.793022 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.793063 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.793102 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.793143 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.804918 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.804974 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.805016 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.805056 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.805097 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.805137 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.816917 (XEN) No periodic timer Jun 27 15:18:27.816973 (XEN) UNIT77 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.817021 (XEN) VCPU77: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.828939 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.828997 (XEN) GICH_LRs (vcpu 77) mask=0 Jun 27 15:18:27.829042 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.829082 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.840909 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.840965 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.841008 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.841048 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.841088 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.841128 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.852918 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.852973 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.853016 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.853057 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.853097 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.853137 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.864909 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.864965 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.865007 (XEN) No periodic timer Jun 27 15:18:27.865048 (XEN) UNIT78 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.876873 (XEN) VCPU78: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.876937 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.876982 (XEN) GICH_LRs (vcpu 78) mask=0 Jun 27 15:18:27.888933 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.888989 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.889030 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.889071 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.889111 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.900906 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.900963 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.901005 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.901046 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.901086 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.901126 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.912928 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.912984 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.913026 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.913067 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.913107 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.913146 (XEN) No periodic timer Jun 27 15:18:27.924919 (XEN) UNIT79 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.924980 (XEN) VCPU79: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.925031 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.936923 (XEN) GICH_LRs (vcpu 79) mask=0 Jun 27 15:18:27.936982 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.937024 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.937064 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.937105 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.948910 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.948965 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.949007 (XEN) VCPU_LR[6]=0 Jun 27 15:18:27.949048 (XEN) VCPU_LR[7]=0 Jun 27 15:18:27.949088 (XEN) VCPU_LR[8]=0 Jun 27 15:18:27.949128 (XEN) VCPU_LR[9]=0 Jun 27 15:18:27.960920 (XEN) VCPU_LR[10]=0 Jun 27 15:18:27.960975 (XEN) VCPU_LR[11]=0 Jun 27 15:18:27.961017 (XEN) VCPU_LR[12]=0 Jun 27 15:18:27.961058 (XEN) VCPU_LR[13]=0 Jun 27 15:18:27.961098 (XEN) VCPU_LR[14]=0 Jun 27 15:18:27.972909 (XEN) VCPU_LR[15]=0 Jun 27 15:18:27.972967 (XEN) No periodic timer Jun 27 15:18:27.973011 (XEN) UNIT80 affinities: hard={0-95} soft={0-95} Jun 27 15:18:27.973057 (XEN) VCPU80: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:27.984930 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:27.984988 (XEN) GICH_LRs (vcpu 80) mask=0 Jun 27 15:18:27.985033 (XEN) VCPU_LR[0]=0 Jun 27 15:18:27.985074 (XEN) VCPU_LR[1]=0 Jun 27 15:18:27.996918 (XEN) VCPU_LR[2]=0 Jun 27 15:18:27.996974 (XEN) VCPU_LR[3]=0 Jun 27 15:18:27.997016 (XEN) VCPU_LR[4]=0 Jun 27 15:18:27.997057 (XEN) VCPU_LR[5]=0 Jun 27 15:18:27.997097 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.008919 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.008975 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.009018 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.009059 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.009100 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.009142 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.020919 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.020975 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.021018 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.021095 (XEN) No periodic timer Jun 27 15:18:28.021140 (XEN) UNIT81 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.032934 (XEN) VCPU81: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.032998 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.033043 (XEN) GICH_LRs (vcpu 81) mask=0 Jun 27 15:18:28.044927 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.044983 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.045025 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.045067 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.045107 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.056917 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.056973 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.057016 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.057057 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.057097 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.057138 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.068922 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.068978 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.069021 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.069063 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.069103 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.069144 (XEN) No periodic timer Jun 27 15:18:28.080919 (XEN) UNIT82 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.080980 (XEN) VCPU82: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.092912 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.092974 (XEN) GICH_LRs (vcpu 82) mask=0 Jun 27 15:18:28.093019 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.093061 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.093101 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.104924 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.104980 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.105022 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.105063 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.105103 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.105143 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.116902 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.116958 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.117001 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.117041 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.117081 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.128913 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.128969 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.129011 (XEN) No periodic timer Jun 27 15:18:28.129053 (XEN) UNIT83 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.129099 (XEN) VCPU83: CPU89 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.140922 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.140981 (XEN) GICH_LRs (vcpu 83) mask=0 Jun 27 15:18:28.141025 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.152894 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.152949 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.152991 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.153032 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.153073 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.153113 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.164920 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.164975 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.165017 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.165057 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.165098 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.165138 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.176915 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.176971 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.177013 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.177053 (XEN) No periodic timer Jun 27 15:18:28.177095 (XEN) UNIT84 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.188922 (XEN) VCPU84: CPU6 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.188986 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.200913 (XEN) GICH_LRs (vcpu 84) mask=0 Jun 27 15:18:28.200972 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.201015 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.201055 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.201096 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.201136 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.212918 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.212973 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.213015 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.213056 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.213096 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.213136 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.224948 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.225005 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.225047 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.225087 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.225127 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.225167 (XEN) No periodic timer Jun 27 15:18:28.236919 (XEN) UNIT85 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.236981 (XEN) VCPU85: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.248905 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.248964 (XEN) GICH_LRs (vcpu 85) mask=0 Jun 27 15:18:28.249009 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.249050 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.260913 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.260969 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.261011 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.261053 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.261093 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.261133 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.272918 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.272974 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.273016 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.273057 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.273097 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.273137 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.284923 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.284980 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.285022 (XEN) No periodic timer Jun 27 15:18:28.285064 (XEN) UNIT86 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.285110 (XEN) VCPU86: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.296913 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.296971 (XEN) GICH_LRs (vcpu 86) mask=0 Jun 27 15:18:28.297016 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.308929 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.308984 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.309025 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.309065 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.309106 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.309146 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.320924 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.320980 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.321022 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.321063 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.321104 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.332925 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.332983 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.333025 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.333066 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.333107 (XEN) No periodic timer Jun 27 15:18:28.333149 (XEN) UNIT87 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.344924 (XEN) VCPU87: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.344989 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.356914 (XEN) GICH_LRs (vcpu 87) mask=0 Jun 27 15:18:28.356972 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.357015 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.357055 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.357095 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.357135 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.368924 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.368979 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.369021 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.369061 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.369101 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.369142 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.380910 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.380965 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.381007 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.381048 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.381089 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.392923 (XEN) No periodic timer Jun 27 15:18:28.392980 (XEN) UNIT88 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.393028 (XEN) VCPU88: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.404839 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.404898 (XEN) GICH_LRs (vcpu 88) mask=0 Jun 27 15:18:28.404943 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.404984 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.416915 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.416971 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.417014 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.417055 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.417096 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.417172 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.428926 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.428962 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.428990 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.429016 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.429080 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.429135 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.440746 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.440773 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.440795 (XEN) No periodic timer Jun 27 15:18:28.440818 (XEN) UNIT89 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.452937 (XEN) VCPU89: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.453004 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.453049 (XEN) GICH_LRs (vcpu 89) mask=0 Jun 27 15:18:28.464924 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.464981 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.465023 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.465064 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.465103 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.465143 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.476919 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.477004 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.477051 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.477093 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.477133 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.477175 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.488911 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.488967 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.489009 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.489050 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.489090 (XEN) No periodic timer Jun 27 15:18:28.489132 (XEN) UNIT90 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.500917 (XEN) VCPU90: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.500980 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.512917 (XEN) GICH_LRs (vcpu 90) mask=0 Jun 27 15:18:28.512975 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.513017 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.513058 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.513098 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.524913 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.524968 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.525011 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.525051 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.525092 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.525131 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.536889 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.536938 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.536979 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.537020 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.537061 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.548806 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.548833 (XEN) No periodic timer Jun 27 15:18:28.548856 (XEN) UNIT91 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.548882 (XEN) VCPU91: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.560810 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.560840 (XEN) GICH_LRs (vcpu 91) mask=0 Jun 27 15:18:28.560864 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.560886 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.572816 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.572843 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.572865 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.572888 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.572909 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.572931 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.584809 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.584835 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.584857 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.584880 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.584902 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.584924 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.596918 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.596973 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.597015 (XEN) No periodic timer Jun 27 15:18:28.597057 (XEN) UNIT92 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.608914 (XEN) VCPU92: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.608979 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.609024 (XEN) GICH_LRs (vcpu 92) mask=0 Jun 27 15:18:28.620912 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.620968 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.621050 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.621095 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.621136 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.621176 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.632911 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.632967 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.633010 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.633051 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.633092 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.644913 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.644969 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.645012 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.645053 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.645093 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.645133 (XEN) No periodic timer Jun 27 15:18:28.656917 (XEN) UNIT93 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.656978 (XEN) VCPU93: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.657029 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.668924 (XEN) GICH_LRs (vcpu 93) mask=0 Jun 27 15:18:28.668982 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.669024 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.669065 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.680911 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.680969 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.681012 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.681053 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.681094 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.681134 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.692915 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.692973 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.693016 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.693056 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.693097 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.693137 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.704911 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.704967 (XEN) No periodic timer Jun 27 15:18:28.705011 (XEN) UNIT94 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.705058 (XEN) VCPU94: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.716922 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.716979 (XEN) GICH_LRs (vcpu 94) mask=0 Jun 27 15:18:28.717024 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.717065 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.728923 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.728978 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.729021 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.729062 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.729102 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.729142 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.740923 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.740978 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.741021 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.741061 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.741102 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.741142 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.752912 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.752968 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.753010 (XEN) No periodic timer Jun 27 15:18:28.753053 (XEN) UNIT95 affinities: hard={0-95} soft={0-95} Jun 27 15:18:28.764924 (XEN) VCPU95: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jun 27 15:18:28.764989 (XEN) pause_count=0 pause_flags=1 Jun 27 15:18:28.776913 (XEN) GICH_LRs (vcpu 95) mask=0 Jun 27 15:18:28.776972 (XEN) VCPU_LR[0]=0 Jun 27 15:18:28.777015 (XEN) VCPU_LR[1]=0 Jun 27 15:18:28.777056 (XEN) VCPU_LR[2]=0 Jun 27 15:18:28.777096 (XEN) VCPU_LR[3]=0 Jun 27 15:18:28.777136 (XEN) VCPU_LR[4]=0 Jun 27 15:18:28.788919 (XEN) VCPU_LR[5]=0 Jun 27 15:18:28.788975 (XEN) VCPU_LR[6]=0 Jun 27 15:18:28.789017 (XEN) VCPU_LR[7]=0 Jun 27 15:18:28.789058 (XEN) VCPU_LR[8]=0 Jun 27 15:18:28.789098 (XEN) VCPU_LR[9]=0 Jun 27 15:18:28.789138 (XEN) VCPU_LR[10]=0 Jun 27 15:18:28.800912 (XEN) VCPU_LR[11]=0 Jun 27 15:18:28.800968 (XEN) VCPU_LR[12]=0 Jun 27 15:18:28.801010 (XEN) VCPU_LR[13]=0 Jun 27 15:18:28.801051 (XEN) VCPU_LR[14]=0 Jun 27 15:18:28.801092 (XEN) VCPU_LR[15]=0 Jun 27 15:18:28.801133 (XEN) No periodic timer Jun 27 15:18:28.812919 (XEN) Notifying guest 0:0 (virq 1, port 0) Jun 27 15:18:28.812978 (XEN) Notifying guest 0:1 (virq 1, port 0) Jun 27 15:18:28.813023 (XEN) Notifying guest 0:2 (virq 1, port 0) Jun 27 15:18:28.824920 (XEN) Notifying guest 0:3 (virq 1, port 0) Jun 27 15:18:28.824981 (XEN) Notifying guest 0:4 (virq 1, port 0) Jun 27 15:18:28.825025 (XEN) Notifying guest 0:5 (virq 1, port 0) Jun 27 15:18:28.836915 (XEN) Notifying guest 0:6 (virq 1, port 0) Jun 27 15:18:28.836975 (XEN) Notifying guest 0:7 (virq 1, port 0) Jun 27 15:18:28.837021 (XEN) Notifying guest 0:8 (virq 1, port 0) Jun 27 15:18:28.837065 (XEN) Notifying guest 0:9 (virq 1, port 0) Jun 27 15:18:28.848928 (XEN) Notifying guest 0:10 (virq 1, port 0) Jun 27 15:18:28.848986 (XEN) Notifying guest 0:11 (virq 1, port 0) Jun 27 15:18:28.849032 (XEN) Notifying guest 0:12 (virq 1, port 0) Jun 27 15:18:28.860950 (XEN) Notifying guest 0:13 (virq 1, port 0) Jun 27 15:18:28.861009 (XEN) Notifying guest 0:14 (virq 1, port 0) Jun 27 15:18:28.861054 (XEN) Notifying guest 0:15 (virq 1, port 0) Jun 27 15:18:28.872934 (XEN) Notifying guest 0:16 (virq 1, port 0) Jun 27 15:18:28.872992 (XEN) Notifying guest 0:17 (virq 1, port 0) Jun 27 15:18:28.873037 (XEN) Notifying guest 0:18 (virq 1, port 0) Jun 27 15:18:28.884909 (XEN) Notifying guest 0:19 (virq 1, port 0) Jun 27 15:18:28.884968 (XEN) Notifying guest 0:20 (virq 1, port 0) Jun 27 15:18:28.896923 (XEN) Notifying guest 0:21 (virq 1, port 0) Jun 27 15:18:28.896983 (XEN) Notifying guest 0:22 (virq 1, port 0) Jun 27 15:18:28.897029 (XEN) Notifying guest 0:23 (virq 1, port 0) Jun 27 15:18:28.908927 (XEN) Notifying guest 0:24 (virq 1, port 0) Jun 27 15:18:28.908987 (XEN) Notifying guest 0:25 (virq 1, port 0) Jun 27 15:18:28.909032 (XEN) Notifying guest 0:26 (virq 1, port 0) Jun 27 15:18:28.909076 (XEN) Notifying guest 0:27 (virq 1, port 0) Jun 27 15:18:28.920928 (XEN) Notifying guest 0:28 (virq 1, port 0) Jun 27 15:18:28.920987 (XEN) Notifying guest 0:29 (virq 1, port 0) Jun 27 15:18:28.921032 (XEN) Notifying guest 0:30 (virq 1, port 0) Jun 27 15:18:28.932929 (XEN) Notifying guest 0:31 (virq 1, port 0) Jun 27 15:18:28.932988 (XEN) Notifying guest 0:32 (virq 1, port 0) Jun 27 15:18:28.933032 (XEN) Notifying guest 0:33 (virq 1, port 0) Jun 27 15:18:28.944920 (XEN) Notifying guest 0:34 (virq 1, port 0) Jun 27 15:18:28.944979 (XEN) Notifying guest 0:35 (virq 1, port 0) Jun 27 15:18:28.945024 (XEN) Notifying guest 0:36 (virq 1, port 0) Jun 27 15:18:28.956919 (XEN) Notifying guest 0:37 (virq 1, port 0) Jun 27 15:18:28.956978 (XEN) Notifying guest 0:38 (virq 1, port 0) Jun 27 15:18:28.957022 (XEN) Notifying guest 0:39 (virq 1, port 0) Jun 27 15:18:28.968921 (XEN) Notifying guest 0:40 (virq 1, port 0) Jun 27 15:18:28.968980 (XEN) Notifying guest 0:41 (virq 1, port 0) Jun 27 15:18:28.969024 (XEN) Notifying guest 0:42 (virq 1, port 0) Jun 27 15:18:28.980911 (XEN) Notifying guest 0:43 (virq 1, port 0) Jun 27 15:18:28.980970 (XEN) Notifying guest 0:44 (virq 1, port 0) Jun 27 15:18:28.981015 (XEN) Notifying guest 0:45 (virq 1, port 0) Jun 27 15:18:28.992925 (XEN) Notifying guest 0:46 (virq 1, port 0) Jun 27 15:18:28.992984 (XEN) Notifying guest 0:47 (virq 1, port 0) Jun 27 15:18:28.993029 (XEN) Notifying guest 0:48 (virq 1, port 0) Jun 27 15:18:29.004919 (XEN) Notifying guest 0:49 (virq 1, port 0) Jun 27 15:18:29.004979 (XEN) Notifying guest 0:50 (virq 1, port 0) Jun 27 15:18:29.005025 (XEN) Notifying guest 0:51 (virq 1, port 0) Jun 27 15:18:29.016909 (XEN) Notifying guest 0:52 (virq 1, port 0) Jun 27 15:18:29.016969 (XEN) Notifying guest 0:53 (virq 1, port 0) Jun 27 15:18:29.017015 (XEN) Notifying guest 0:54 (virq 1, port 0) Jun 27 15:18:29.028900 (XEN) Notifying guest 0:55 (virq 1, port 0) Jun 27 15:18:29.028959 (XEN) Notifying guest 0:56 (virq 1, port 0) Jun 27 15:18:29.029005 (XEN) Notifying guest 0:57 (virq 1, port 0) Jun 27 15:18:29.040929 (XEN) Notifying guest 0:58 (virq 1, port 0) Jun 27 15:18:29.040989 (XEN) Notifying guest 0:59 (virq 1, port 0) Jun 27 15:18:29.041034 (XEN) Notifying guest 0:60 (virq 1, port 0) Jun 27 15:18:29.052921 (XEN) Notifying guest 0:61 (virq 1, port 0) Jun 27 15:18:29.052980 (XEN) Notifying guest 0:62 (virq 1, port 0) Jun 27 15:18:29.053064 (XEN) Notifying guest 0:63 (virq 1, port 0) Jun 27 15:18:29.064908 (XEN) Notifying guest 0:64 (virq 1, port 0) Jun 27 15:18:29.064968 (XEN) Notifying guest 0:65 (virq 1, port 0) Jun 27 15:18:29.065014 (XEN) Notifying guest 0:66 (virq 1, port 0) Jun 27 15:18:29.076921 (XEN) Notifying guest 0:67 (virq 1, port 0) Jun 27 15:18:29.076981 (XEN) Notifying guest 0:68 (virq 1, port 0) Jun 27 15:18:29.077027 (XEN) Notifying guest 0:69 (virq 1, port 0) Jun 27 15:18:29.088918 (XEN) Notifying guest 0:70 (virq 1, port 0) Jun 27 15:18:29.088978 (XEN) Notifying guest 0:71 (virq 1, port 0) Jun 27 15:18:29.089024 (XEN) Notifying guest 0:72 (virq 1, port 0) Jun 27 15:18:29.100923 (XEN) Notifying guest 0:73 (virq 1, port 0) Jun 27 15:18:29.100983 (XEN) Notifying guest 0:74 (virq 1, port 0) Jun 27 15:18:29.101028 (XEN) Notifying guest 0:75 (virq 1, port 0) Jun 27 15:18:29.112920 (XEN) Notifying guest 0:76 (virq 1, port 0) Jun 27 15:18:29.112980 (XEN) Notifying guest 0:77 (virq 1, port 0) Jun 27 15:18:29.113026 (XEN) Notifying guest 0:78 (virq 1, port 0) Jun 27 15:18:29.124920 (XEN) Notifying guest 0:79 (virq 1, port 0) Jun 27 15:18:29.124980 (XEN) Notifying guest 0:80 (virq 1, port 0) Jun 27 15:18:29.125026 (XEN) Notifying guest 0:81 (virq 1, port 0) Jun 27 15:18:29.136903 (XEN) Notifying guest 0:82 (virq 1, port 0) Jun 27 15:18:29.136963 (XEN) Notifying guest 0:83 (virq 1, port 0) Jun 27 15:18:29.137010 (XEN) Notifying guest 0:84 (virq 1, port 0) Jun 27 15:18:29.148914 (XEN) Notifying guest 0:85 (virq 1, port 0) Jun 27 15:18:29.148973 (XEN) Notifying guest 0:86 (virq 1, port 0) Jun 27 15:18:29.149018 (XEN) Notifying guest 0:87 (virq 1, port 0) Jun 27 15:18:29.160929 (XEN) Notifying guest 0:88 (virq 1, port 0) Jun 27 15:18:29.160987 (XEN) Notifying guest 0:89 (virq 1, port 0) Jun 27 15:18:29.161033 (XEN) Notifying guest 0:90 (virq 1, port 0) Jun 27 15:18:29.172916 (XEN) Notifying guest 0:91 (virq 1, port 0) Jun 27 15:18:29.172976 (XEN) Notifying guest 0:92 (virq 1, port 0) Jun 27 15:18:29.173021 (XEN) Notifying guest 0:93 (virq 1, port 0) Jun 27 15:18:29.184900 (XEN) Notifying guest 0:94 (virq 1, port 0) Jun 27 15:18:29.184960 (XEN) Notifying guest 0:95 (virq 1, port 0) Jun 27 15:18:29.185005 Jun 27 15:18:35.687736 (XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input) Jun 27 15:18:35.712940 Jun 27 15:18:35.714319