Jun 29 03:17:15.501091 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:15.501269 (XEN) GICH_LRs (vcpu 49) mask=0
Jun 29 03:17:15.501296 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:15.501373 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:15.501400 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:15.501422 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:15.501444 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:15.501466 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:15.501506 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:15.508975 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:15.508975 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:15.508975 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:15.508976 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:15.509038 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:15.509080 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:15.520851 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:15.520907 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:15.520949 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:15.521013 (XEN) No periodic timer
Jun 29 03:17:15.521057 (XEN)   UNIT50 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:15.532869 (XEN)     VCPU50: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:15.532934 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:15.544852 (XEN) GICH_LRs (vcpu 50) mask=0
Jun 29 03:17:15.544934 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:15.544978 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:15.545019 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:15.545059 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:15.545099 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:15.556894 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:15.556950 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:15.556993 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:15.557034 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:15.557074 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:15.557137 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:15.568838 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:15.568899 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:15.568942 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:15.568983 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:15.569047 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:15.569089 (XEN) No periodic timer
Jun 29 03:17:15.580801 (XEN)   UNIT51 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:15.580855 (XEN)     VCPU51: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:15.592722 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:15.592760 (XEN) GICH_LRs (vcpu 51) mask=0
Jun 29 03:17:15.592784 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:15.592807 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:15.604733 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:15.604759 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:15.604792 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:15.604814 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:15.604837 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:15.604859 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:15.616736 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:15.616762 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:15.616794 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:15.616817 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:15.616839 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:15.616861 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:15.628734 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:15.628769 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:15.628792 (XEN) No periodic timer
Jun 29 03:17:15.628815 (XEN)   UNIT52 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:15.628840 (XEN)     VCPU52: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:15.643226 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:15.643278 (XEN) GICH_LRs (vcpu 52) mask=0
Jun 29 03:17:15.643303 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:15.655235 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:15.655265 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:15.655288 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:15.655323 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:15.655346 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:15.655368 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:15.667230 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:15.667261 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:15.667296 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:15.667319 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:15.667342 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:15.679157 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:15.679157 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:15.679157 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:15.679157 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:15.679157 (XEN) No periodic timer
Jun 29 03:17:15.679157 (XEN)   UNIT53 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:15.691150 (XEN)     VCPU53: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:15.691150 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:15.703152 (XEN) GICH_LRs (vcpu 53) mask=0
Jun 29 03:17:15.703152 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:15.703152 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:15.703152 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:15.703152 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:15.703152 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:15.715134 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:15.715134 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:15.715134 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:15.715134 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:15.715134 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:15.727147 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:15.727147 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:15.727147 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:15.727147 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:15.727147 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:15.727147 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:15.739148 (XEN) No periodic timer
Jun 29 03:17:15.739148 (XEN)   UNIT54 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:15.739148 (XEN)     VCPU54: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:15.751157 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:15.751157 (XEN) GICH_LRs (vcpu 54) mask=0
Jun 29 03:17:15.751157 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:15.751157 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:15.763151 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:15.763151 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:15.763151 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:15.763151 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:15.763151 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:15.763151 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:15.775152 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:15.775152 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:15.775152 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:15.775152 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:15.775152 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:15.775152 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:15.787161 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:15.787161 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:15.787161 (XEN) No periodic timer
Jun 29 03:17:15.787161 (XEN)   UNIT55 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:15.787161 (XEN)     VCPU55: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:15.799156 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:15.799156 (XEN) GICH_LRs (vcpu 55) mask=0
Jun 29 03:17:15.811151 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:15.811151 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:15.811151 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:15.811151 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:15.811151 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:15.811151 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:15.823149 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:15.823149 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:15.823149 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:15.823149 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:15.823149 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:15.823149 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:15.835163 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:15.835163 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:15.835163 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:15.835163 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:15.835163 (XEN) No periodic timer
Jun 29 03:17:15.835163 (XEN)   UNIT56 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:15.847141 (XEN)     VCPU56: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:15.847141 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:15.859150 (XEN) GICH_LRs (vcpu 56) mask=0
Jun 29 03:17:15.859150 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:15.859150 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:15.859150 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:15.859150 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:15.871157 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:15.871157 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:15.871157 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:15.871157 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:15.871157 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:15.871157 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:15.883158 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:15.883158 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:15.883158 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:15.883158 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:15.883158 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:15.883158 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:15.895150 (XEN) No periodic timer
Jun 29 03:17:15.895150 (XEN)   UNIT57 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:15.895150 (XEN)     VCPU57: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:15.907158 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:15.907158 (XEN) GICH_LRs (vcpu 57) mask=0
Jun 29 03:17:15.907158 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:15.907158 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:15.919156 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:15.919156 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:15.919156 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:15.919156 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:15.919156 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:15.919156 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:15.931152 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:15.931152 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:15.931152 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:15.931152 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:15.931152 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:15.931152 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:15.943156 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:15.943156 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:15.943156 (XEN) No periodic timer
Jun 29 03:17:15.943156 (XEN)   UNIT58 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:15.955162 (XEN)     VCPU58: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:15.955162 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:15.955162 (XEN) GICH_LRs (vcpu 58) mask=0
Jun 29 03:17:15.967161 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:15.967161 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:15.967161 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:15.967161 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:15.967161 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:15.967161 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:15.979146 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:15.979146 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:15.979146 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:15.979146 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:15.979146 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:15.991164 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:15.991164 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:15.991164 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:15.991164 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:15.991164 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:15.991164 (XEN) No periodic timer
Jun 29 03:17:16.003156 (XEN)   UNIT59 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.003156 (XEN)     VCPU59: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.003156 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.015155 (XEN) GICH_LRs (vcpu 59) mask=0
Jun 29 03:17:16.015155 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.015155 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.015155 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.015155 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.027156 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.027156 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.027156 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.027156 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.027156 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.027156 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.039156 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.039156 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.039156 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.039156 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.039156 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.051155 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.051155 (XEN) No periodic timer
Jun 29 03:17:16.051155 (XEN)   UNIT60 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.051155 (XEN)     VCPU60: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.063152 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.063152 (XEN) GICH_LRs (vcpu 60) mask=0
Jun 29 03:17:16.063152 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.063152 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.075154 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.075154 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.075154 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.075154 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.075154 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.075154 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.087146 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.087146 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.087146 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.087146 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.087146 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.087146 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.099143 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.099143 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.099143 (XEN) No periodic timer
Jun 29 03:17:16.099143 (XEN)   UNIT61 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.111155 (XEN)     VCPU61: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.111155 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.111155 (XEN) GICH_LRs (vcpu 61) mask=0
Jun 29 03:17:16.123156 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.123156 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.123156 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.123156 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.123156 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.135155 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.135155 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.135155 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.135155 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.135155 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.135155 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.147153 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.147153 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.147153 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.147153 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.147153 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.147153 (XEN) No periodic timer
Jun 29 03:17:16.159163 (XEN)   UNIT62 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.159163 (XEN)     VCPU62: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.171154 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.171154 (XEN) GICH_LRs (vcpu 62) mask=0
Jun 29 03:17:16.171154 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.171154 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.171154 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.183152 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.183152 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.183152 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.183152 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.183152 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.183152 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.195160 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.195160 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.195160 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.195160 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.195160 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.195160 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.207157 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.207157 (XEN) No periodic timer
Jun 29 03:17:16.207157 (XEN)   UNIT63 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.207157 (XEN)     VCPU63: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.219155 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.219155 (XEN) GICH_LRs (vcpu 63) mask=0
Jun 29 03:17:16.219155 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.219155 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.231145 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.231145 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.231145 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.231145 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.231145 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.243153 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.243153 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.243153 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.243153 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.243153 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.243153 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.255150 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.255150 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.255150 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.255150 (XEN) No periodic timer
Jun 29 03:17:16.255150 (XEN)   UNIT64 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.267163 (XEN)     VCPU64: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.267163 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.279155 (XEN) GICH_LRs (vcpu 64) mask=0
Jun 29 03:17:16.279155 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.279155 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.279155 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.279155 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.279155 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.291155 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.291155 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.291155 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.291155 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.291155 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.291155 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.303164 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.303164 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.303164 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.303164 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.303164 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.303164 (XEN) No periodic timer
Jun 29 03:17:16.315162 (XEN)   UNIT65 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.315162 (XEN)     VCPU65: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.327155 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.327155 (XEN) GICH_LRs (vcpu 65) mask=0
Jun 29 03:17:16.327155 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.327155 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.327155 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.339154 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.339154 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.339154 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.339154 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.339154 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.339154 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.351147 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.351147 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.351147 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.351147 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.351147 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.363155 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.363155 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.363155 (XEN) No periodic timer
Jun 29 03:17:16.363155 (XEN)   UNIT66 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.363155 (XEN)     VCPU66: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.375159 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.375159 (XEN) GICH_LRs (vcpu 66) mask=0
Jun 29 03:17:16.387149 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.387149 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.387149 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.387149 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.387149 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.387149 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.399156 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.399156 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.399156 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.399156 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.399156 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.399156 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.411176 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.411176 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.411176 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.411176 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.411176 (XEN) No periodic timer
Jun 29 03:17:16.411176 (XEN)   UNIT67 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.423152 (XEN)     VCPU67: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.423152 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.435147 (XEN) GICH_LRs (vcpu 67) mask=0
Jun 29 03:17:16.435147 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.435147 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.435147 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.435147 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.435147 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.447153 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.447153 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.447153 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.447153 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.447153 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.447153 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.459158 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.459158 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.459158 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.459158 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.459158 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.471163 (XEN) No periodic timer
Jun 29 03:17:16.471163 (XEN)   UNIT68 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.471163 (XEN)     VCPU68: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.483144 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.483144 (XEN) GICH_LRs (vcpu 68) mask=0
Jun 29 03:17:16.483144 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.483144 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.495159 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.495159 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.495159 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.495159 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.495159 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.495159 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.507164 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.507164 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.507164 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.507164 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.507164 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.507164 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.519152 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.519152 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.519152 (XEN) No periodic timer
Jun 29 03:17:16.519152 (XEN)   UNIT69 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.531161 (XEN)     VCPU69: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.531161 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.531161 (XEN) GICH_LRs (vcpu 69) mask=0
Jun 29 03:17:16.543158 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.543158 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.543158 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.543158 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.543158 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.543158 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.555153 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.555153 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.555153 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.555153 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.555153 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.555153 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.567155 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.567155 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.567155 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.567155 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.567155 (XEN) No periodic timer
Jun 29 03:17:16.567155 (XEN)   UNIT70 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.579161 (XEN)     VCPU70: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.579161 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.591154 (XEN) GICH_LRs (vcpu 70) mask=0
Jun 29 03:17:16.591154 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.591154 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.591154 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.591154 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.603150 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.603150 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.603150 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.603150 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.603150 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.603150 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.615154 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.615154 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.615154 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.615154 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.615154 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.627155 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.627155 (XEN) No periodic timer
Jun 29 03:17:16.627155 (XEN)   UNIT71 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.627155 (XEN)     VCPU71: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.639159 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.639159 (XEN) GICH_LRs (vcpu 71) mask=0
Jun 29 03:17:16.639159 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.639159 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.651154 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.651154 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.651154 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.651154 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.651154 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.651154 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.663154 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.663154 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.663154 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.663154 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.663154 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.663154 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.675152 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.675152 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.675152 (XEN) No periodic timer
Jun 29 03:17:16.675152 (XEN)   UNIT72 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.687222 (XEN)     VCPU72: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.687222 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.687222 (XEN) GICH_LRs (vcpu 72) mask=0
Jun 29 03:17:16.699420 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.699420 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.699420 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.699420 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.699420 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.699420 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.711159 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.711159 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.711159 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.711159 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.711159 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.711159 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.723163 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.723163 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.723163 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.723163 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.723163 (XEN) No periodic timer
Jun 29 03:17:16.723163 (XEN)   UNIT73 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.735145 (XEN)     VCPU73: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.747163 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.747163 (XEN) GICH_LRs (vcpu 73) mask=0
Jun 29 03:17:16.747163 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.747163 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.747163 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.759162 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.759162 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.759162 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.759162 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.759162 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.759162 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.771159 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.771159 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.771159 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.771159 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.771159 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.771159 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.783156 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.783156 (XEN) No periodic timer
Jun 29 03:17:16.783156 (XEN)   UNIT74 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.783156 (XEN)     VCPU74: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.795159 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.795159 (XEN) GICH_LRs (vcpu 74) mask=0
Jun 29 03:17:16.795159 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.795159 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.807159 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.807159 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.807159 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.807159 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.807159 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.807159 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.819156 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.819156 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.819156 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.819156 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.819156 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.831155 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.831155 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.831155 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.831155 (XEN) No periodic timer
Jun 29 03:17:16.831155 (XEN)   UNIT75 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.843151 (XEN)     VCPU75: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.843151 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.843151 (XEN) GICH_LRs (vcpu 75) mask=0
Jun 29 03:17:16.855155 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.855155 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.855155 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.855155 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.855155 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.855155 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.867147 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.867147 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.867147 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.867147 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.867147 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.879160 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.879160 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.879160 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.879160 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.879160 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.879160 (XEN) No periodic timer
Jun 29 03:17:16.891148 (XEN)   UNIT76 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.891148 (XEN)     VCPU76: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.907178 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.907178 (XEN) GICH_LRs (vcpu 76) mask=0
Jun 29 03:17:16.907178 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.907178 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.907178 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.907178 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.907178 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.919157 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.919157 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.919157 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.919157 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.919157 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.919157 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.931155 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.931155 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.931155 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.931155 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.931155 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.931155 (XEN) No periodic timer
Jun 29 03:17:16.943154 (XEN)   UNIT77 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.943154 (XEN)     VCPU77: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:16.955161 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:16.955161 (XEN) GICH_LRs (vcpu 77) mask=0
Jun 29 03:17:16.955161 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:16.955161 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:16.955161 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:16.967159 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:16.967159 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:16.967159 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:16.967159 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:16.967159 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:16.967159 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:16.979155 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:16.979155 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:16.979155 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:16.979155 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:16.979155 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:16.979155 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:16.991150 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:16.991150 (XEN) No periodic timer
Jun 29 03:17:16.991150 (XEN)   UNIT78 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:16.991150 (XEN)     VCPU78: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.003157 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.003157 (XEN) GICH_LRs (vcpu 78) mask=0
Jun 29 03:17:17.003157 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.015152 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.015152 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.015152 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.015152 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.015152 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.015152 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.027167 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.027167 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.027167 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.027167 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.027167 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.027167 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.039157 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.039157 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.039157 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.039157 (XEN) No periodic timer
Jun 29 03:17:17.039157 (XEN)   UNIT79 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.051158 (XEN)     VCPU79: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.051158 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.063158 (XEN) GICH_LRs (vcpu 79) mask=0
Jun 29 03:17:17.063158 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.063158 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.063158 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.063158 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.063158 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.075155 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.075155 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.075155 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.075155 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.075155 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.075155 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.087161 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.087161 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.087161 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.087161 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.087161 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.087161 (XEN) No periodic timer
Jun 29 03:17:17.099160 (XEN)   UNIT80 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.099160 (XEN)     VCPU80: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.110213 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.110251 (XEN) GICH_LRs (vcpu 80) mask=0
Jun 29 03:17:17.110276 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.110299 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.110322 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.123149 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.123149 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.123149 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.123149 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.123149 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.135166 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.135166 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.135166 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.135166 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.135166 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.135166 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.147154 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.147154 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.147154 (XEN) No periodic timer
Jun 29 03:17:17.147154 (XEN)   UNIT81 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.147154 (XEN)     VCPU81: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.159156 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.159156 (XEN) GICH_LRs (vcpu 81) mask=0
Jun 29 03:17:17.159156 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.171157 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.171157 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.171157 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.171157 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.171157 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.171157 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.183158 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.183158 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.183158 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.183158 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.183158 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.195160 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.195160 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.195160 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.195160 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.195160 (XEN) No periodic timer
Jun 29 03:17:17.195160 (XEN)   UNIT82 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.207157 (XEN)     VCPU82: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.207157 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.219159 (XEN) GICH_LRs (vcpu 82) mask=0
Jun 29 03:17:17.219159 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.219159 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.219159 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.219159 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.219159 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.231153 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.231153 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.231153 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.231153 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.231153 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.231153 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.243150 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.243150 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.243150 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.243150 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.243150 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.255152 (XEN) No periodic timer
Jun 29 03:17:17.255152 (XEN)   UNIT83 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.255152 (XEN)     VCPU83: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.267156 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.267156 (XEN) GICH_LRs (vcpu 83) mask=0
Jun 29 03:17:17.267156 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.267156 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.279157 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.279157 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.279157 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.279157 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.279157 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.279157 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.291156 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.291156 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.291156 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.291156 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.291156 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.291156 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.303158 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.303158 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.303158 (XEN) No periodic timer
Jun 29 03:17:17.303158 (XEN)   UNIT84 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.303158 (XEN)     VCPU84: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.315150 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.315150 (XEN) GICH_LRs (vcpu 84) mask=0
Jun 29 03:17:17.327156 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.327156 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.327156 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.327156 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.327156 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.327156 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.339161 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.339161 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.339161 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.339161 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.339161 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.339161 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.351152 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.351152 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.351152 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.351152 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.351152 (XEN) No periodic timer
Jun 29 03:17:17.351152 (XEN)   UNIT85 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.363137 (XEN)     VCPU85: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.363137 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.375148 (XEN) GICH_LRs (vcpu 85) mask=0
Jun 29 03:17:17.375148 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.375148 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.375148 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.375148 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.387213 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.387249 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.387272 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.387295 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.387318 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.387341 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.399162 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.399162 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.399162 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.399162 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.399162 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.399162 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.411158 (XEN) No periodic timer
Jun 29 03:17:17.411158 (XEN)   UNIT86 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.411158 (XEN)     VCPU86: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.423153 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.423153 (XEN) GICH_LRs (vcpu 86) mask=0
Jun 29 03:17:17.423153 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.423153 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.435213 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.435248 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.435271 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.435294 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.435316 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.435338 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.447162 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.447162 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.447162 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.447162 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.447162 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.447162 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.459154 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.459154 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.459154 (XEN) No periodic timer
Jun 29 03:17:17.459154 (XEN)   UNIT87 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.471158 (XEN)     VCPU87: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.471158 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.471158 (XEN) GICH_LRs (vcpu 87) mask=0
Jun 29 03:17:17.483157 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.483157 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.483157 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.483157 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.483157 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.483157 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.495142 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.495142 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.495142 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.495142 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.495142 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.507159 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.507159 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.507159 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.507159 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.507159 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.507159 (XEN) No periodic timer
Jun 29 03:17:17.519152 (XEN)   UNIT88 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.519152 (XEN)     VCPU88: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.519152 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.531155 (XEN) GICH_LRs (vcpu 88) mask=0
Jun 29 03:17:17.531155 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.531155 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.531155 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.531155 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.543156 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.543156 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.543156 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.543156 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.543156 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.543156 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.555162 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.555342 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.555389 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.555389 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.555456 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.567151 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.567151 (XEN) No periodic timer
Jun 29 03:17:17.567151 (XEN)   UNIT89 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.567151 (XEN)     VCPU89: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.579163 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.579163 (XEN) GICH_LRs (vcpu 89) mask=0
Jun 29 03:17:17.579163 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.579163 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.591162 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.591162 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.591162 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.591162 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.591162 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.591162 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.603154 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.603154 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.603154 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.603154 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.603154 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.603154 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.615153 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.615153 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.615153 (XEN) No periodic timer
Jun 29 03:17:17.615153 (XEN)   UNIT90 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.627148 (XEN)     VCPU90: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.627148 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.627148 (XEN) GICH_LRs (vcpu 90) mask=0
Jun 29 03:17:17.639163 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.639163 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.639163 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.639163 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.639163 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.651167 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.651167 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.651167 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.651167 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.651167 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.651167 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.663156 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.663156 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.663156 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.663156 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.663156 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.663156 (XEN) No periodic timer
Jun 29 03:17:17.675152 (XEN)   UNIT91 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.675152 (XEN)     VCPU91: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.687149 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.687149 (XEN) GICH_LRs (vcpu 91) mask=0
Jun 29 03:17:17.687149 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.687149 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.687149 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.699159 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.699159 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.699159 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.699159 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.699159 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.699159 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.711164 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.711164 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.711164 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.711164 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.711164 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.711164 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.723157 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.723157 (XEN) No periodic timer
Jun 29 03:17:17.723157 (XEN)   UNIT92 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.723157 (XEN)     VCPU92: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.735160 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.735160 (XEN) GICH_LRs (vcpu 92) mask=0
Jun 29 03:17:17.735160 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.735160 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.747159 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.747159 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.747159 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.747159 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.747159 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.759155 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.759155 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.759155 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.759155 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.759155 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.759155 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.771158 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.771158 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.771158 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.771158 (XEN) No periodic timer
Jun 29 03:17:17.771158 (XEN)   UNIT93 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.783161 (XEN)     VCPU93: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.783161 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.795154 (XEN) GICH_LRs (vcpu 93) mask=0
Jun 29 03:17:17.795154 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.795154 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.795154 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.795154 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.795154 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.807156 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.807156 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.807156 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.807156 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.807156 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.807156 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.819161 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.819161 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.819161 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.819161 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.819161 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.819161 (XEN) No periodic timer
Jun 29 03:17:17.831154 (XEN)   UNIT94 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.831154 (XEN)     VCPU94: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.843153 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.843153 (XEN) GICH_LRs (vcpu 94) mask=0
Jun 29 03:17:17.843153 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.843153 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.843153 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.855239 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.855275 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.855298 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.855321 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.855343 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.855365 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.867238 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.867269 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.867292 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.867314 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.867347 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.867372 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.879239 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.879270 (XEN) No periodic timer
Jun 29 03:17:17.879294 (XEN)   UNIT95 affinities: hard={0-95} soft={0-95}
Jun 29 03:17:17.879319 (XEN)     VCPU95: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Jun 29 03:17:17.891245 (XEN)     pause_count=0 pause_flags=1
Jun 29 03:17:17.891276 (XEN) GICH_LRs (vcpu 95) mask=0
Jun 29 03:17:17.903239 (XEN)    VCPU_LR[0]=0
Jun 29 03:17:17.903271 (XEN)    VCPU_LR[1]=0
Jun 29 03:17:17.903295 (XEN)    VCPU_LR[2]=0
Jun 29 03:17:17.903317 (XEN)    VCPU_LR[3]=0
Jun 29 03:17:17.903340 (XEN)    VCPU_LR[4]=0
Jun 29 03:17:17.903362 (XEN)    VCPU_LR[5]=0
Jun 29 03:17:17.915233 (XEN)    VCPU_LR[6]=0
Jun 29 03:17:17.915265 (XEN)    VCPU_LR[7]=0
Jun 29 03:17:17.915289 (XEN)    VCPU_LR[8]=0
Jun 29 03:17:17.915311 (XEN)    VCPU_LR[9]=0
Jun 29 03:17:17.915334 (XEN)    VCPU_LR[10]=0
Jun 29 03:17:17.915356 (XEN)    VCPU_LR[11]=0
Jun 29 03:17:17.927251 (XEN)    VCPU_LR[12]=0
Jun 29 03:17:17.927282 (XEN)    VCPU_LR[13]=0
Jun 29 03:17:17.927305 (XEN)    VCPU_LR[14]=0
Jun 29 03:17:17.927327 (XEN)    VCPU_LR[15]=0
Jun 29 03:17:17.927349 (XEN) No periodic timer
Jun 29 03:17:17.927371 (XEN) Notifying guest 0:0 (virq 1, port 0)
Jun 29 03:17:17.939256 (XEN) Notifying guest 0:1 (virq 1, port 0)
Jun 29 03:17:17.939288 (XEN) Notifying guest 0:2 (virq 1, port 0)
Jun 29 03:17:17.939313 (XEN) Notifying guest 0:3 (virq 1, port 0)
Jun 29 03:17:17.951251 (XEN) Notifying guest 0:4 (virq 1, port 0)
Jun 29 03:17:17.951283 (XEN) Notifying guest 0:5 (virq 1, port 0)
Jun 29 03:17:17.951308 (XEN) Notifying guest 0:6 (virq 1, port 0)
Jun 29 03:17:17.963251 (XEN) Notifying guest 0:7 (virq 1, port 0)
Jun 29 03:17:17.963284 (XEN) Notifying guest 0:8 (virq 1, port 0)
Jun 29 03:17:17.963309 (XEN) Notifying guest 0:9 (virq 1, port 0)
Jun 29 03:17:17.975245 (XEN) Notifying guest 0:10 (virq 1, port 0)
Jun 29 03:17:17.975278 (XEN) Notifying guest 0:11 (virq 1, port 0)
Jun 29 03:17:17.975304 (XEN) Notifying guest 0:12 (virq 1, port 0)
Jun 29 03:17:17.987253 (XEN) Notifying guest 0:13 (virq 1, port 0)
Jun 29 03:17:17.987286 (XEN) Notifying guest 0:14 (virq 1, port 0)
Jun 29 03:17:17.987312 (XEN) Notifying guest 0:15 (virq 1, port 0)
Jun 29 03:17:17.999245 (XEN) Notifying guest 0:16 (virq 1, port 0)
Jun 29 03:17:17.999278 (XEN) Notifying guest 0:17 (virq 1, port 0)
Jun 29 03:17:17.999303 (XEN) Notifying guest 0:18 (virq 1, port 0)
Jun 29 03:17:18.011239 (XEN) Notifying guest 0:19 (virq 1, port 0)
Jun 29 03:17:18.011273 (XEN) Notifying guest 0:20 (virq 1, port 0)
Jun 29 03:17:18.011299 (XEN) Notifying guest 0:21 (virq 1, port 0)
Jun 29 03:17:18.023255 (XEN) Notifying guest 0:22 (virq 1, port 0)
Jun 29 03:17:18.023288 (XEN) Notifying guest 0:23 (virq 1, port 0)
Jun 29 03:17:18.023313 (XEN) Notifying guest 0:24 (virq 1, port 0)
Jun 29 03:17:18.035248 (XEN) Notifying guest 0:25 (virq 1, port 0)
Jun 29 03:17:18.035281 (XEN) Notifying guest 0:26 (virq 1, port 0)
Jun 29 03:17:18.035306 (XEN) Notifying guest 0:27 (virq 1, port 0)
Jun 29 03:17:18.047251 (XEN) Notifying guest 0:28 (virq 1, port 0)
Jun 29 03:17:18.047284 (XEN) Notifying guest 0:29 (virq 1, port 0)
Jun 29 03:17:18.047310 (XEN) Notifying guest 0:30 (virq 1, port 0)
Jun 29 03:17:18.059244 (XEN) Notifying guest 0:31 (virq 1, port 0)
Jun 29 03:17:18.059277 (XEN) Notifying guest 0:32 (virq 1, port 0)
Jun 29 03:17:18.059302 (XEN) Notifying guest 0:33 (virq 1, port 0)
Jun 29 03:17:18.071257 (XEN) Notifying guest 0:34 (virq 1, port 0)
Jun 29 03:17:18.071290 (XEN) Notifying guest 0:35 (virq 1, port 0)
Jun 29 03:17:18.071316 (XEN) Notifying guest 0:36 (virq 1, port 0)
Jun 29 03:17:18.083245 (XEN) Notifying guest 0:37 (virq 1, port 0)
Jun 29 03:17:18.083278 (XEN) Notifying guest 0:38 (virq 1, port 0)
Jun 29 03:17:18.083304 (XEN) Notifying guest 0:39 (virq 1, port 0)
Jun 29 03:17:18.083328 (XEN) Notifying guest 0:40 (virq 1, port 0)
Jun 29 03:17:18.095250 (XEN) Notifying guest 0:41 (virq 1, port 0)
Jun 29 03:17:18.095292 (XEN) Notifying guest 0:42 (virq 1, port 0)
Jun 29 03:17:18.095319 (XEN) Notifying guest 0:43 (virq 1, port 0)
Jun 29 03:17:18.107254 (XEN) Notifying guest 0:44 (virq 1, port 0)
Jun 29 03:17:18.107286 (XEN) Notifying guest 0:45 (virq 1, port 0)
Jun 29 03:17:18.107311 (XEN) Notifying guest 0:46 (virq 1, port 0)
Jun 29 03:17:18.119259 (XEN) Notifying guest 0:47 (virq 1, port 0)
Jun 29 03:17:18.119308 (XEN) Notifying guest 0:48 (virq 1, port 0)
Jun 29 03:17:18.119350 (XEN) Notifying guest 0:49 (virq 1, port 0)
Jun 29 03:17:18.131242 (XEN) Notifying guest 0:50 (virq 1, port 0)
Jun 29 03:17:18.131274 (XEN) Notifying guest 0:51 (virq 1, port 0)
Jun 29 03:17:18.143232 (XEN) Notifying guest 0:52 (virq 1, port 0)
Jun 29 03:17:18.143265 (XEN) Notifying guest 0:53 (virq 1, port 0)
Jun 29 03:17:18.143290 (XEN) Notifying guest 0:54 (virq 1, port 0)
Jun 29 03:17:18.155252 (XEN) Notifying guest 0:55 (virq 1, port 0)
Jun 29 03:17:18.155285 (XEN) Notifying guest 0:56 (virq 1, port 0)
Jun 29 03:17:18.155310 (XEN) Notifying guest 0:57 (virq 1, port 0)
Jun 29 03:17:18.155334 (XEN) Notifying guest 0:58 (virq 1, port 0)
Jun 29 03:17:18.167243 (XEN) Notifying guest 0:59 (virq 1, port 0)
Jun 29 03:17:18.167276 (XEN) Notifying guest 0:60 (virq 1, port 0)
Jun 29 03:17:18.167301 (XEN) Notifying guest 0:61 (virq 1, port 0)
Jun 29 03:17:18.179226 (XEN) Notifying guest 0:62 (virq 1, port 0)
Jun 29 03:17:18.179258 (XEN) Notifying guest 0:63 (virq 1, port 0)
Jun 29 03:17:18.179283 (XEN) Notifying guest 0:64 (virq 1, port 0)
Jun 29 03:17:18.191208 (XEN) Notifying guest 0:65 (virq 1, port 0)
Jun 29 03:17:18.191240 (XEN) Notifying guest 0:66 (virq 1, port 0)
Jun 29 03:17:18.191265 (XEN) Notifying guest 0:67 (virq 1, port 0)
Jun 29 03:17:18.203218 (XEN) Notifying guest 0:68 (virq 1, port 0)
Jun 29 03:17:18.203250 (XEN) Notifying guest 0:69 (virq 1, port 0)
Jun 29 03:17:18.203275 (XEN) Notifying guest 0:70 (virq 1, port 0)
Jun 29 03:17:18.215239 (XEN) Notifying guest 0:71 (virq 1, port 0)
Jun 29 03:17:18.215272 (XEN) Notifying guest 0:72 (virq 1, port 0)
Jun 29 03:17:18.215297 (XEN) Notifying guest 0:73 (virq 1, port 0)
Jun 29 03:17:18.227246 (XEN) Notifying guest 0:74 (virq 1, port 0)
Jun 29 03:17:18.227279 (XEN) Notifying guest 0:75 (virq 1, port 0)
Jun 29 03:17:18.227303 (XEN) Notifying guest 0:76 (virq 1, port 0)
Jun 29 03:17:18.239252 (XEN) Notifying guest 0:77 (virq 1, port 0)
Jun 29 03:17:18.239285 (XEN) Notifying guest 0:78 (virq 1, port 0)
Jun 29 03:17:18.239310 (XEN) Notifying guest 0:79 (virq 1, port 0)
Jun 29 03:17:18.251239 (XEN) Notifying guest 0:80 (virq 1, port 0)
Jun 29 03:17:18.251271 (XEN) Notifying guest 0:81 (virq 1, port 0)
Jun 29 03:17:18.251296 (XEN) Notifying guest 0:82 (virq 1, port 0)
Jun 29 03:17:18.263233 (XEN) Notifying guest 0:83 (virq 1, port 0)
Jun 29 03:17:18.263265 (XEN) Notifying guest 0:84 (virq 1, port 0)
Jun 29 03:17:18.263291 (XEN) Notifying guest 0:85 (virq 1, port 0)
Jun 29 03:17:18.275246 (XEN) Notifying guest 0:86 (virq 1, port 0)
Jun 29 03:17:18.275279 (XEN) Notifying guest 0:87 (virq 1, port 0)
Jun 29 03:17:18.275304 (XEN) Notifying guest 0:88 (virq 1, port 0)
Jun 29 03:17:18.287242 (XEN) Notifying guest 0:89 (virq 1, port 0)
Jun 29 03:17:18.287275 (XEN) Notifying guest 0:90 (virq 1, port 0)
Jun 29 03:17:18.287300 (XEN) Notifying guest 0:91 (virq 1, port 0)
Jun 29 03:17:18.299239 (XEN) Notifying guest 0:92 (virq 1, port 0)
Jun 29 03:17:18.299271 (XEN) Notifying guest 0:93 (virq 1, port 0)
Jun 29 03:17:18.299296 (XEN) Notifying guest 0:94 (virq 1, port 0)
Jun 29 03:17:18.311211 (XEN) Notifying guest 0:95 (virq 1, port 0)
Jun 29 03:17:18.311243 Jun 29 03:17:24.734368 <client 0x195a5f0 connected - now 1 clients>
(XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input)
Jun 29 03:17:24.755246 Jun 29 03:17:24.756690 <client 0x195a5f0 disconnected - now 0 clients>