Jul 1 06:11:18.115016 (XEN) FAR_EL2: ffff80000b510100 Jul 1 06:11:18.124714 (XEN) Jul 1 06:11:18.124714 (XEN) Xen stack trace from sp=0000800ffd857e60: Jul 1 06:11:18.124719 (XEN) 0000800ffd857e70 00000a0000283014 00000a0000341420 00000a00003785a8 Jul 1 06:11:18.124746 (XEN) 000000000000005f 0000000000000000 0000000000000000 000000000001020f Jul 1 06:11:18.136681 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jul 1 06:11:18.148676 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jul 1 06:11:18.148712 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jul 1 06:11:18.160643 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jul 1 06:11:18.160643 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jul 1 06:11:18.172662 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jul 1 06:11:18.172662 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jul 1 06:11:18.184664 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jul 1 06:11:18.196663 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jul 1 06:11:18.196663 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jul 1 06:11:18.208663 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Jul 1 06:11:18.208663 (XEN) Xen call trace: Jul 1 06:11:18.208663 (XEN) [<00000a0000277078>] arch/arm/domain.c#idle_loop+0x12c/0x194 (PC) Jul 1 06:11:18.220664 (XEN) [<00000a000027705c>] arch/arm/domain.c#idle_loop+0x110/0x194 (LR) Jul 1 06:11:18.232653 (XEN) [<00000a0000283014>] start_secondary+0x218/0x21c Jul 1 06:11:18.232653 (XEN) [<00000a00003785a8>] 00000a00003785a8 Jul 1 06:11:18.232653 (XEN) Jul 1 06:11:18.232653 Jul 1 06:11:23.841454 (XEN) 'q' pressed -> dumping domain info (now = 1281368675170) Jul 1 06:11:23.864955 (XEN) General information for domain 0: Jul 1 06:11:23.864978 (XEN) refcnt=3 dying=0 p Jul 1 06:11:23.867202 ause_count=0 Jul 1 06:11:23.880768 (XEN) nr_pages=131072 xenheap_pages=2 dirty_cpus={} max_pages=131072 Jul 1 06:11:23.880768 (XEN) handle=00000000-0000-0000-0000-000000000000 vm_assist=00000020 Jul 1 06:11:23.880768 (XEN) p2m mappings for domain 0 (vmid 1): Jul 1 06:11:23.892770 (XEN) 1G mappings: 4984 (shattered 3) Jul 1 06:11:23.892770 (XEN) 2M mappings: 1444449 (shattered 101) Jul 1 06:11:23.892770 (XEN) 4K mappings: 51728 Jul 1 06:11:23.892770 (XEN) Rangesets belonging to domain 0: Jul 1 06:11:23.900793 (XEN) Interrupts { 32, 38, 48-51 } Jul 1 06:11:23.900793 (XEN) I/O Memory { 802000000-808000000, 810000000-820000000, 838000000-844000000, 846000000-848002000, 849000000-849002000, 84a000000-84a002000, 84b000000-84b002000, 868000000-880000000, 88001f000-880058000, 881010000-883000010, 902000000-908000000, 910000000-920000000, 938000000-944000000, 946000000-948002000, 949000000-949002000, 94a000000-94a002000, 94b000000-94b002000, 968000000-980000000 } Jul 1 06:11:23.936782 (XEN) NODE affinity for domain 0: [0] Jul 1 06:11:23.948782 (XEN) VCPU information and callbacks for domain 0: Jul 1 06:11:23.948782 (XEN) UNIT0 affinities: hard={0-95} soft={0-95} Jul 1 06:11:23.948782 (XEN) VCPU0: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:23.960785 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:23.960785 (XEN) GICH_LRs (vcpu 0) mask=0 Jul 1 06:11:23.960785 (XEN) VCPU_LR[0]=0 Jul 1 06:11:23.972785 (XEN) VCPU_LR[1]=0 Jul 1 06:11:23.972785 (XEN) VCPU_LR[2]=0 Jul 1 06:11:23.972785 (XEN) VCPU_LR[3]=0 Jul 1 06:11:23.972785 (XEN) VCPU_LR[4]=0 Jul 1 06:11:23.972785 (XEN) VCPU_LR[5]=0 Jul 1 06:11:23.972785 (XEN) VCPU_LR[6]=0 Jul 1 06:11:23.984781 (XEN) VCPU_LR[7]=0 Jul 1 06:11:23.984781 (XEN) VCPU_LR[8]=0 Jul 1 06:11:23.984781 (XEN) VCPU_LR[9]=0 Jul 1 06:11:23.984781 (XEN) VCPU_LR[10]=0 Jul 1 06:11:23.984781 (XEN) VCPU_LR[11]=0 Jul 1 06:11:23.996781 (XEN) VCPU_LR[12]=0 Jul 1 06:11:23.996781 (XEN) VCPU_LR[13]=0 Jul 1 06:11:23.996781 (XEN) VCPU_LR[14]=0 Jul 1 06:11:23.996781 (XEN) VCPU_LR[15]=0 Jul 1 06:11:23.996781 (XEN) No periodic timer Jul 1 06:11:23.996781 (XEN) UNIT1 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.008774 (XEN) VCPU1: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.008774 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.020783 (XEN) GICH_LRs (vcpu 1) mask=0 Jul 1 06:11:24.020783 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.020783 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.020783 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.020783 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.020783 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.032789 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.032789 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.032789 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.032789 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.032789 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.032789 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.044779 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.044779 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.044779 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.044779 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.044779 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.056778 (XEN) No periodic timer Jul 1 06:11:24.056778 (XEN) UNIT2 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.056778 (XEN) VCPU2: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.068780 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.068780 (XEN) GICH_LRs (vcpu 2) mask=0 Jul 1 06:11:24.068780 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.068780 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.080785 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.080785 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.080785 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.080785 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.080785 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.080785 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.092786 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.092786 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.092786 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.092786 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.092786 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.092786 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.104786 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.104786 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.104786 (XEN) No periodic timer Jul 1 06:11:24.104786 (XEN) UNIT3 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.104786 (XEN) VCPU3: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.116786 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.116786 (XEN) GICH_LRs (vcpu 3) mask=0 Jul 1 06:11:24.116786 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.128785 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.128785 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.128785 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.128785 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.128785 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.128785 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.140786 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.140786 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.140786 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.140786 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.140786 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.140786 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.152784 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.152784 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.152784 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.152784 (XEN) No periodic timer Jul 1 06:11:24.152784 (XEN) UNIT4 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.164783 (XEN) VCPU4: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.164783 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.176760 (XEN) GICH_LRs (vcpu 4) mask=0 Jul 1 06:11:24.176760 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.176760 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.176760 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.176760 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.192796 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.192796 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.192796 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.192796 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.192796 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.192796 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.192796 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.192796 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.200753 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.200753 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.200753 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.200753 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.212774 (XEN) No periodic timer Jul 1 06:11:24.212774 (XEN) UNIT5 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.212774 (XEN) VCPU5: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.224770 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.224770 (XEN) GICH_LRs (vcpu 5) mask=0 Jul 1 06:11:24.224770 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.224770 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.224770 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.236778 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.236778 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.236778 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.236778 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.236778 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.236778 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.248781 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.248781 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.248781 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.248781 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.248781 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.260782 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.260782 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.260782 (XEN) No periodic timer Jul 1 06:11:24.260782 (XEN) UNIT6 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.260782 (XEN) VCPU6: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.272783 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.272783 (XEN) GICH_LRs (vcpu 6) mask=0 Jul 1 06:11:24.272783 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.284783 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.284783 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.284783 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.284783 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.284783 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.284783 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.296782 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.296782 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.296782 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.296782 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.296782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.296782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.308768 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.308768 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.308768 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.308768 (XEN) No periodic timer Jul 1 06:11:24.308768 (XEN) UNIT7 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.320783 (XEN) VCPU7: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.320783 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.332784 (XEN) GICH_LRs (vcpu 7) mask=0 Jul 1 06:11:24.332784 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.332784 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.332784 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.332784 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.344785 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.344785 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.344785 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.344785 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.344785 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.344785 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.356781 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.356781 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.356781 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.356781 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.356781 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.356781 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.368780 (XEN) No periodic timer Jul 1 06:11:24.368780 (XEN) UNIT8 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.368780 (XEN) VCPU8: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.380784 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.380784 (XEN) GICH_LRs (vcpu 8) mask=0 Jul 1 06:11:24.380784 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.380784 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.380784 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.392776 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.392776 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.392776 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.392776 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.392776 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.392776 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.404781 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.404781 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.404781 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.404781 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.404781 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.404781 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.416781 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.416781 (XEN) No periodic timer Jul 1 06:11:24.416781 (XEN) UNIT9 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.416781 (XEN) VCPU9: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.428772 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.428772 (XEN) GICH_LRs (vcpu 9) mask=0 Jul 1 06:11:24.440782 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.440782 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.440782 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.440782 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.440782 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.440782 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.452784 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.452784 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.452784 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.452784 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.452784 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.452784 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.464784 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.464784 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.464784 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.464784 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.464784 (XEN) No periodic timer Jul 1 06:11:24.464784 (XEN) UNIT10 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.476780 (XEN) VCPU10: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.476780 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.488770 (XEN) GICH_LRs (vcpu 10) mask=0 Jul 1 06:11:24.488770 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.488770 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.488770 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.488770 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.500823 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.500823 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.500823 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.500823 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.500823 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.500823 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.512781 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.512781 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.512781 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.512781 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.512781 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.512781 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.524783 (XEN) No periodic timer Jul 1 06:11:24.524783 (XEN) UNIT11 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.524783 (XEN) VCPU11: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.536782 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.536782 (XEN) GICH_LRs (vcpu 11) mask=0 Jul 1 06:11:24.536782 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.536782 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.536782 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.548783 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.548783 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.548783 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.548783 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.548783 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.548783 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.560762 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.560762 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.560762 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.560762 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.560762 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.572778 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.572778 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.572778 (XEN) No periodic timer Jul 1 06:11:24.572778 (XEN) UNIT12 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.584780 (XEN) VCPU12: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.584780 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.584780 (XEN) GICH_LRs (vcpu 12) mask=0 Jul 1 06:11:24.596782 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.596782 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.596782 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.596782 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.596782 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.596782 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.608784 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.608784 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.608784 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.608784 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.608784 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.608784 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.620782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.620782 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.620782 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.620782 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.620782 (XEN) No periodic timer Jul 1 06:11:24.620782 (XEN) UNIT13 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.632783 (XEN) VCPU13: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.632783 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.644783 (XEN) GICH_LRs (vcpu 13) mask=0 Jul 1 06:11:24.644783 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.644783 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.644783 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.644783 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.656783 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.656783 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.656783 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.656783 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.656783 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.656783 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.668781 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.668781 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.668781 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.668781 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.668781 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.668781 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.680771 (XEN) No periodic timer Jul 1 06:11:24.680771 (XEN) UNIT14 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.680771 (XEN) VCPU14: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.692776 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.692776 (XEN) GICH_LRs (vcpu 14) mask=0 Jul 1 06:11:24.692776 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.692776 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.704781 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.704781 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.704781 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.704781 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.704781 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.704781 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.716777 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.716777 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.716777 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.716777 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.716777 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.728774 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.728774 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.728774 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.728774 (XEN) No periodic timer Jul 1 06:11:24.728774 (XEN) UNIT15 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.740771 (XEN) VCPU15: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.740771 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.740771 (XEN) GICH_LRs (vcpu 15) mask=0 Jul 1 06:11:24.752784 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.752784 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.752784 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.752784 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.752784 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.752784 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.764784 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.764784 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.764784 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.764784 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.764784 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.764784 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.776780 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.776780 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.776780 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.776780 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.776780 (XEN) No periodic timer Jul 1 06:11:24.788770 (XEN) UNIT16 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.788770 (XEN) VCPU16: CPU67 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.788770 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.800780 (XEN) GICH_LRs (vcpu 16) mask=0 Jul 1 06:11:24.800780 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.800780 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.800780 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.800780 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.812916 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.812916 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.812916 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.812916 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.812916 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.824807 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.824807 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.824807 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.824807 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.824807 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.824807 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.836780 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.836780 (XEN) No periodic timer Jul 1 06:11:24.836780 (XEN) UNIT17 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.836780 (XEN) VCPU17: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.848780 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.848780 (XEN) GICH_LRs (vcpu 17) mask=0 Jul 1 06:11:24.848780 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.860784 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.860784 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.860784 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.860784 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.860784 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.860784 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.872782 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.872782 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.872782 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.872782 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.872782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.872782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.884782 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.884782 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.884782 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.884782 (XEN) No periodic timer Jul 1 06:11:24.884782 (XEN) UNIT18 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.896780 (XEN) VCPU18: CPU7 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.896780 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.896780 (XEN) GICH_LRs (vcpu 18) mask=0 Jul 1 06:11:24.908782 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.908782 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.908782 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.908782 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.908782 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.908782 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.920782 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.920782 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.920782 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.920782 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.920782 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.920782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.932782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.932782 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.932782 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.932782 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.932782 (XEN) No periodic timer Jul 1 06:11:24.944773 (XEN) UNIT19 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.944773 (XEN) VCPU19: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:24.956782 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:24.956782 (XEN) GICH_LRs (vcpu 19) mask=0 Jul 1 06:11:24.956782 (XEN) VCPU_LR[0]=0 Jul 1 06:11:24.956782 (XEN) VCPU_LR[1]=0 Jul 1 06:11:24.956782 (XEN) VCPU_LR[2]=0 Jul 1 06:11:24.968781 (XEN) VCPU_LR[3]=0 Jul 1 06:11:24.968781 (XEN) VCPU_LR[4]=0 Jul 1 06:11:24.968781 (XEN) VCPU_LR[5]=0 Jul 1 06:11:24.968781 (XEN) VCPU_LR[6]=0 Jul 1 06:11:24.968781 (XEN) VCPU_LR[7]=0 Jul 1 06:11:24.968781 (XEN) VCPU_LR[8]=0 Jul 1 06:11:24.980782 (XEN) VCPU_LR[9]=0 Jul 1 06:11:24.980782 (XEN) VCPU_LR[10]=0 Jul 1 06:11:24.980782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:24.980782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:24.980782 (XEN) VCPU_LR[13]=0 Jul 1 06:11:24.980782 (XEN) VCPU_LR[14]=0 Jul 1 06:11:24.992770 (XEN) VCPU_LR[15]=0 Jul 1 06:11:24.992770 (XEN) No periodic timer Jul 1 06:11:24.992770 (XEN) UNIT20 affinities: hard={0-95} soft={0-95} Jul 1 06:11:24.992770 (XEN) VCPU20: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.004772 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.004772 (XEN) GICH_LRs (vcpu 20) mask=0 Jul 1 06:11:25.004772 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.016780 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.016780 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.016780 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.016780 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.016780 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.016780 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.028780 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.028780 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.028780 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.028780 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.028780 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.028780 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.040782 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.040782 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.040782 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.040782 (XEN) No periodic timer Jul 1 06:11:25.040782 (XEN) UNIT21 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.052779 (XEN) VCPU21: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.052779 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.052779 (XEN) GICH_LRs (vcpu 21) mask=0 Jul 1 06:11:25.064764 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.064764 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.064764 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.064764 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.064764 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.076780 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.076780 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.076780 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.076780 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.076780 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.076780 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.088769 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.088769 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.088769 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.088769 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.088769 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.100781 (XEN) No periodic timer Jul 1 06:11:25.100781 (XEN) UNIT22 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.100781 (XEN) VCPU22: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.112784 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.112784 (XEN) GICH_LRs (vcpu 22) mask=0 Jul 1 06:11:25.112784 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.112784 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.112784 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.124781 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.124781 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.124781 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.124781 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.124781 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.124781 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.136779 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.136779 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.136779 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.136779 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.136779 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.136779 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.148780 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.148780 (XEN) No periodic timer Jul 1 06:11:25.148780 (XEN) UNIT23 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.148780 (XEN) VCPU23: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.160783 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.160783 (XEN) GICH_LRs (vcpu 23) mask=0 Jul 1 06:11:25.160783 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.172783 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.172783 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.172783 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.172783 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.172783 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.172783 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.184782 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.184782 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.184782 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.184782 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.184782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.184782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.196767 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.196767 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.196767 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.196767 (XEN) No periodic timer Jul 1 06:11:25.196767 (XEN) UNIT24 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.208770 (XEN) VCPU24: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.208770 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.220780 (XEN) GICH_LRs (vcpu 24) mask=0 Jul 1 06:11:25.220780 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.220780 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.220780 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.220780 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.232775 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.232775 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.232775 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.232775 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.232775 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.232775 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.244773 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.244773 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.244773 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.244773 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.244773 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.244773 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.256841 (XEN) No periodic timer Jul 1 06:11:25.256841 (XEN) UNIT25 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.256841 (XEN) VCPU25: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.268779 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.268779 (XEN) GICH_LRs (vcpu 25) mask=0 Jul 1 06:11:25.268779 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.268779 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.268779 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.280781 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.280781 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.280781 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.280781 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.280781 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.280781 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.292782 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.292782 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.292782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.292782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.292782 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.304779 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.304779 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.304779 (XEN) No periodic timer Jul 1 06:11:25.304779 (XEN) UNIT26 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.304779 (XEN) VCPU26: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.316764 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.316764 (XEN) GICH_LRs (vcpu 26) mask=0 Jul 1 06:11:25.328780 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.328780 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.328780 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.328780 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.328780 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.328780 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.340782 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.340782 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.340782 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.340782 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.340782 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.340782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.352782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.352782 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.352782 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.352782 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.352782 (XEN) No periodic timer Jul 1 06:11:25.352782 (XEN) UNIT27 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.364784 (XEN) VCPU27: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.364784 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.376779 (XEN) GICH_LRs (vcpu 27) mask=0 Jul 1 06:11:25.376779 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.376779 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.376779 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.376779 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.388780 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.388780 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.388780 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.388780 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.388780 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.388780 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.400782 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.400782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.400782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.400782 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.400782 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.400782 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.412783 (XEN) No periodic timer Jul 1 06:11:25.412783 (XEN) UNIT28 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.412783 (XEN) VCPU28: CPU70 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.424781 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.424781 (XEN) GICH_LRs (vcpu 28) mask=0 Jul 1 06:11:25.424781 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.424781 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.436780 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.436780 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.436780 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.436780 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.436780 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.436780 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.448770 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.448770 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.448770 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.448770 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.448770 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.460781 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.460781 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.460781 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.460781 (XEN) No periodic timer Jul 1 06:11:25.460781 (XEN) UNIT29 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.472785 (XEN) VCPU29: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.472785 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.472785 (XEN) GICH_LRs (vcpu 29) mask=0 Jul 1 06:11:25.484779 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.484779 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.484779 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.484779 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.484779 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.484779 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.496772 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.496772 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.496772 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.496772 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.496772 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.496772 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.508771 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.508771 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.508771 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.508771 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.508771 (XEN) No periodic timer Jul 1 06:11:25.520776 (XEN) UNIT30 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.520776 (XEN) VCPU30: CPU9 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.520776 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.532781 (XEN) GICH_LRs (vcpu 30) mask=0 Jul 1 06:11:25.532781 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.532781 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.532781 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.532781 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.544782 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.544782 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.544782 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.544782 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.544782 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.544782 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.556777 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.556777 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.556777 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.556777 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.556777 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.556777 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.568772 (XEN) No periodic timer Jul 1 06:11:25.568772 (XEN) UNIT31 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.568772 (XEN) VCPU31: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.580927 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.580993 (XEN) GICH_LRs (vcpu 31) mask=0 Jul 1 06:11:25.581203 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.592774 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.592774 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.592774 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.592774 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.592774 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.592774 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.604782 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.604782 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.604782 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.604782 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.604782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.604782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.616781 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.616781 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.616781 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.616781 (XEN) No periodic timer Jul 1 06:11:25.616781 (XEN) UNIT32 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.628781 (XEN) VCPU32: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.628781 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.628781 (XEN) GICH_LRs (vcpu 32) mask=0 Jul 1 06:11:25.640782 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.640782 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.640782 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.640782 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.640782 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.652784 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.652784 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.652784 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.652784 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.652784 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.652784 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.664782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.664782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.664782 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.664782 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.664782 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.664782 (XEN) No periodic timer Jul 1 06:11:25.676782 (XEN) UNIT33 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.676782 (XEN) VCPU33: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.676782 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.688771 (XEN) GICH_LRs (vcpu 33) mask=0 Jul 1 06:11:25.688771 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.688771 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.688771 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.688771 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.700770 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.700770 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.700770 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.700770 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.700770 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.712990 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.713063 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.713106 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.713148 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.713189 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.713231 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.724905 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.724961 (XEN) No periodic timer Jul 1 06:11:25.725004 (XEN) UNIT34 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.725051 (XEN) VCPU34: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.736925 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.736984 (XEN) GICH_LRs (vcpu 34) mask=0 Jul 1 06:11:25.737029 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.748924 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.748981 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.749025 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.749067 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.749107 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.749148 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.760916 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.760973 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.761016 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.761057 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.761099 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.761140 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.772921 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.772978 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.773058 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.773103 (XEN) No periodic timer Jul 1 06:11:25.773146 (XEN) UNIT35 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.784915 (XEN) VCPU35: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.784980 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.785026 (XEN) GICH_LRs (vcpu 35) mask=0 Jul 1 06:11:25.796917 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.796974 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.797017 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.797058 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.797099 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.808909 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.808965 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.809009 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.809050 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.809092 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.809133 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.820923 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.820980 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.821024 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.821066 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.821107 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.821149 (XEN) No periodic timer Jul 1 06:11:25.832905 (XEN) UNIT36 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.832967 (XEN) VCPU36: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.844883 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.844942 (XEN) GICH_LRs (vcpu 36) mask=0 Jul 1 06:11:25.844987 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.845029 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.845070 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.856910 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.856966 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.857009 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.857051 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.857092 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.857133 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.868916 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.868971 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.869014 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.869057 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.869099 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.880917 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.880975 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.881019 (XEN) No periodic timer Jul 1 06:11:25.881061 (XEN) UNIT37 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.881109 (XEN) VCPU37: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.892929 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.892987 (XEN) GICH_LRs (vcpu 37) mask=0 Jul 1 06:11:25.893033 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.904913 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.904969 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.905012 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.905054 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.905096 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.905137 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.916893 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.916949 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.916992 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.917034 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.917076 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.917118 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.928916 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.928972 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.929014 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.929055 (XEN) No periodic timer Jul 1 06:11:25.929097 (XEN) UNIT38 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.940892 (XEN) VCPU38: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:25.940957 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:25.952864 (XEN) GICH_LRs (vcpu 38) mask=0 Jul 1 06:11:25.952925 (XEN) VCPU_LR[0]=0 Jul 1 06:11:25.952968 (XEN) VCPU_LR[1]=0 Jul 1 06:11:25.953010 (XEN) VCPU_LR[2]=0 Jul 1 06:11:25.953051 (XEN) VCPU_LR[3]=0 Jul 1 06:11:25.964914 (XEN) VCPU_LR[4]=0 Jul 1 06:11:25.964971 (XEN) VCPU_LR[5]=0 Jul 1 06:11:25.965014 (XEN) VCPU_LR[6]=0 Jul 1 06:11:25.965056 (XEN) VCPU_LR[7]=0 Jul 1 06:11:25.965097 (XEN) VCPU_LR[8]=0 Jul 1 06:11:25.965139 (XEN) VCPU_LR[9]=0 Jul 1 06:11:25.976906 (XEN) VCPU_LR[10]=0 Jul 1 06:11:25.976982 (XEN) VCPU_LR[11]=0 Jul 1 06:11:25.977028 (XEN) VCPU_LR[12]=0 Jul 1 06:11:25.977070 (XEN) VCPU_LR[13]=0 Jul 1 06:11:25.977111 (XEN) VCPU_LR[14]=0 Jul 1 06:11:25.977151 (XEN) VCPU_LR[15]=0 Jul 1 06:11:25.988905 (XEN) No periodic timer Jul 1 06:11:25.988962 (XEN) UNIT39 affinities: hard={0-95} soft={0-95} Jul 1 06:11:25.989011 (XEN) VCPU39: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.000924 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.000983 (XEN) GICH_LRs (vcpu 39) mask=0 Jul 1 06:11:26.001028 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.001070 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.012903 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.012960 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.013002 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.013044 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.013085 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.013125 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.024915 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.024972 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.025015 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.025057 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.025098 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.025138 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.036912 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.036969 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.037012 (XEN) No periodic timer Jul 1 06:11:26.037055 (XEN) UNIT40 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.037102 (XEN) VCPU40: CPU72 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.048920 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.048979 (XEN) GICH_LRs (vcpu 40) mask=0 Jul 1 06:11:26.049024 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.060914 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.060971 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.061014 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.061055 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.061097 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.061138 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.072927 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.072983 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.073026 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.073068 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.073109 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.073150 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.084908 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.084965 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.085007 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.085050 (XEN) No periodic timer Jul 1 06:11:26.096901 (XEN) UNIT41 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.096964 (XEN) VCPU41: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.097016 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.108911 (XEN) GICH_LRs (vcpu 41) mask=0 Jul 1 06:11:26.108969 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.109012 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.109054 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.109095 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.120915 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.120971 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.121014 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.121056 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.121096 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.121137 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.132918 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.132974 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.133018 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.133060 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.133101 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.133142 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.144915 (XEN) No periodic timer Jul 1 06:11:26.144972 (XEN) UNIT42 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.145021 (XEN) VCPU42: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.156915 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.156973 (XEN) GICH_LRs (vcpu 42) mask=0 Jul 1 06:11:26.157018 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.157060 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.168909 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.168966 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.169010 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.169052 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.169114 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.169159 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.180913 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.180969 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.181013 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.181055 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.181096 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.181137 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.192922 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.192979 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.193023 (XEN) No periodic timer Jul 1 06:11:26.193066 (XEN) UNIT43 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.193114 (XEN) VCPU43: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.204920 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.204978 (XEN) GICH_LRs (vcpu 43) mask=0 Jul 1 06:11:26.216914 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.216970 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.217013 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.217055 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.217096 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.217137 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.228916 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.228972 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.229015 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.229056 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.229097 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.229138 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.240909 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.240964 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.241007 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.241048 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.241089 (XEN) No periodic timer Jul 1 06:11:26.252920 (XEN) UNIT44 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.252982 (XEN) VCPU44: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.253033 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.264915 (XEN) GICH_LRs (vcpu 44) mask=0 Jul 1 06:11:26.264973 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.265016 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.265058 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.265100 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.276914 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.276970 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.277012 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.277053 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.277095 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.277136 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.288914 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.288969 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.289012 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.289053 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.289095 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.289136 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.300913 (XEN) No periodic timer Jul 1 06:11:26.300970 (XEN) UNIT45 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.301019 (XEN) VCPU45: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.312911 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.312969 (XEN) GICH_LRs (vcpu 45) mask=0 Jul 1 06:11:26.313014 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.313056 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.324923 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.324979 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.325021 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.325062 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.325104 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.325144 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.336902 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.336958 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.337001 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.337042 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.337084 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.348906 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.348962 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.349005 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.349046 (XEN) No periodic timer Jul 1 06:11:26.349089 (XEN) UNIT46 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.360908 (XEN) VCPU46: CPU73 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.360974 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.361019 (XEN) GICH_LRs (vcpu 46) mask=0 Jul 1 06:11:26.372919 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.372976 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.373040 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.373085 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.373126 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.384914 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.384971 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.385014 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.385056 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.385096 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.385137 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.396908 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.396965 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.397008 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.397049 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.397091 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.397132 (XEN) No periodic timer Jul 1 06:11:26.408913 (XEN) UNIT47 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.408975 (XEN) VCPU47: CPU89 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.409027 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.420915 (XEN) GICH_LRs (vcpu 47) mask=0 Jul 1 06:11:26.420973 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.421017 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.421058 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.421098 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.432920 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.432976 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.433019 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.433060 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.433102 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.433143 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.444914 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.444969 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.445012 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.445052 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.445093 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.456909 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.456940 (XEN) No periodic timer Jul 1 06:11:26.456964 (XEN) UNIT48 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.456990 (XEN) VCPU48: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.468907 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.468966 (XEN) GICH_LRs (vcpu 48) mask=0 Jul 1 06:11:26.469010 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.480908 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.480964 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.481007 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.481049 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.481090 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.481130 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.492901 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.492957 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.492999 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.493040 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.493081 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.493122 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.504926 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.504982 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.505025 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.505066 (XEN) No periodic timer Jul 1 06:11:26.505107 (XEN) UNIT49 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.516875 (XEN) VCPU49: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.516939 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.516984 (XEN) GICH_LRs (vcpu 49) mask=0 Jul 1 06:11:26.528920 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.528975 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.529017 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.529058 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.529099 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.540911 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.540966 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.541009 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.541049 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.541090 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.541129 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.552915 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.552971 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.553015 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.553056 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.553097 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.553138 (XEN) No periodic timer Jul 1 06:11:26.564909 (XEN) UNIT50 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.564970 (XEN) VCPU50: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.576934 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.576995 (XEN) GICH_LRs (vcpu 50) mask=0 Jul 1 06:11:26.577040 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.577082 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.577123 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.588913 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.588969 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.589012 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.589054 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.589095 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.600903 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.600961 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.601004 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.601046 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.601087 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.601128 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.612907 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.612964 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.613007 (XEN) No periodic timer Jul 1 06:11:26.613050 (XEN) UNIT51 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.613097 (XEN) VCPU51: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.624927 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.624985 (XEN) GICH_LRs (vcpu 51) mask=0 Jul 1 06:11:26.625030 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.636916 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.636972 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.637015 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.637057 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.637098 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.637140 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.648913 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.648969 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.649012 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.649053 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.649094 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.649135 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.660913 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.660969 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.661012 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.661054 (XEN) No periodic timer Jul 1 06:11:26.661097 (XEN) UNIT52 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.672912 (XEN) VCPU52: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.672977 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.684913 (XEN) GICH_LRs (vcpu 52) mask=0 Jul 1 06:11:26.684972 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.685015 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.685057 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.685099 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.685140 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.696920 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.696976 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.697018 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.697060 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.697102 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.697142 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.708908 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.708964 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.709007 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.709049 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.709091 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.709133 (XEN) No periodic timer Jul 1 06:11:26.720908 (XEN) UNIT53 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.720970 (XEN) VCPU53: CPU89 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.732919 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.732978 (XEN) GICH_LRs (vcpu 53) mask=0 Jul 1 06:11:26.733024 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.733066 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.744903 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.744960 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.745003 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.745045 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.745085 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.745126 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.756919 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.756975 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.757018 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.757060 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.757101 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.757143 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.768911 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.768968 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.769036 (XEN) No periodic timer Jul 1 06:11:26.769082 (XEN) UNIT54 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.769129 (XEN) VCPU54: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.780924 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.780982 (XEN) GICH_LRs (vcpu 54) mask=0 Jul 1 06:11:26.792912 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.792969 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.793013 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.793055 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.793097 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.793138 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.804907 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.804965 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.805009 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.805051 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.805093 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.805134 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.816957 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.817013 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.817057 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.817100 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.817143 (XEN) No periodic timer Jul 1 06:11:26.817185 (XEN) UNIT55 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.828915 (XEN) VCPU55: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.828979 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.840891 (XEN) GICH_LRs (vcpu 55) mask=0 Jul 1 06:11:26.840949 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.840992 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.841034 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.841075 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.852907 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.852963 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.853006 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.853047 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.853088 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.853129 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.864908 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.864964 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.865008 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.865050 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.865091 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.865133 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.876924 (XEN) No periodic timer Jul 1 06:11:26.876981 (XEN) UNIT56 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.877030 (XEN) VCPU56: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.888910 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.888970 (XEN) GICH_LRs (vcpu 56) mask=0 Jul 1 06:11:26.889016 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.889058 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.900913 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.900969 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.901011 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.901052 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.901094 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.901136 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.912915 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.912971 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.913014 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.913056 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.913098 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.913139 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.924914 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.924970 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.925013 (XEN) No periodic timer Jul 1 06:11:26.925056 (XEN) UNIT57 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.936911 (XEN) VCPU57: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.936977 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.937023 (XEN) GICH_LRs (vcpu 57) mask=0 Jul 1 06:11:26.948910 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.948967 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.949010 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.949052 (XEN) VCPU_LR[3]=0 Jul 1 06:11:26.949093 (XEN) VCPU_LR[4]=0 Jul 1 06:11:26.949135 (XEN) VCPU_LR[5]=0 Jul 1 06:11:26.960913 (XEN) VCPU_LR[6]=0 Jul 1 06:11:26.960969 (XEN) VCPU_LR[7]=0 Jul 1 06:11:26.961013 (XEN) VCPU_LR[8]=0 Jul 1 06:11:26.961054 (XEN) VCPU_LR[9]=0 Jul 1 06:11:26.961095 (XEN) VCPU_LR[10]=0 Jul 1 06:11:26.961155 (XEN) VCPU_LR[11]=0 Jul 1 06:11:26.972905 (XEN) VCPU_LR[12]=0 Jul 1 06:11:26.972962 (XEN) VCPU_LR[13]=0 Jul 1 06:11:26.973005 (XEN) VCPU_LR[14]=0 Jul 1 06:11:26.973047 (XEN) VCPU_LR[15]=0 Jul 1 06:11:26.973089 (XEN) No periodic timer Jul 1 06:11:26.984905 (XEN) UNIT58 affinities: hard={0-95} soft={0-95} Jul 1 06:11:26.984967 (XEN) VCPU58: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:26.985020 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:26.996888 (XEN) GICH_LRs (vcpu 58) mask=0 Jul 1 06:11:26.996946 (XEN) VCPU_LR[0]=0 Jul 1 06:11:26.996989 (XEN) VCPU_LR[1]=0 Jul 1 06:11:26.997031 (XEN) VCPU_LR[2]=0 Jul 1 06:11:26.997073 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.008914 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.008970 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.009013 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.009055 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.009096 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.009137 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.020929 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.020985 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.021027 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.021069 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.021110 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.032914 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.032971 (XEN) No periodic timer Jul 1 06:11:27.033014 (XEN) UNIT59 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.033062 (XEN) VCPU59: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.044918 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.044976 (XEN) GICH_LRs (vcpu 59) mask=0 Jul 1 06:11:27.045022 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.045064 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.056906 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.056962 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.057005 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.057047 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.057088 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.057129 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.068921 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.068977 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.069025 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.069067 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.069108 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.069148 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.080916 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.080972 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.081016 (XEN) No periodic timer Jul 1 06:11:27.081059 (XEN) UNIT60 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.092919 (XEN) VCPU60: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.092984 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.093030 (XEN) GICH_LRs (vcpu 60) mask=0 Jul 1 06:11:27.104900 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.104957 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.105001 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.105042 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.105084 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.116911 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.116967 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.117011 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.117053 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.117094 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.117136 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.128915 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.128972 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.129015 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.129057 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.129100 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.129141 (XEN) No periodic timer Jul 1 06:11:27.140916 (XEN) UNIT61 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.140978 (XEN) VCPU61: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.141030 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.152920 (XEN) GICH_LRs (vcpu 61) mask=0 Jul 1 06:11:27.152979 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.153022 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.153063 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.164912 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.164968 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.165012 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.165054 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.165116 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.165160 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.176909 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.176966 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.177009 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.177052 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.177093 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.177134 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.188908 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.188965 (XEN) No periodic timer Jul 1 06:11:27.189010 (XEN) UNIT62 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.189057 (XEN) VCPU62: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.200926 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.200985 (XEN) GICH_LRs (vcpu 62) mask=0 Jul 1 06:11:27.201031 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.201073 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.212910 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.212966 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.213008 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.213050 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.213091 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.213132 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.224910 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.224966 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.225009 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.225051 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.225093 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.236919 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.236976 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.237019 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.237061 (XEN) No periodic timer Jul 1 06:11:27.237102 (XEN) UNIT63 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.248918 (XEN) VCPU63: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.248983 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.260915 (XEN) GICH_LRs (vcpu 63) mask=0 Jul 1 06:11:27.260974 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.261018 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.261059 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.261101 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.261142 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.272912 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.272968 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.273011 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.273053 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.273095 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.273136 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.284913 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.284969 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.285012 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.285053 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.285095 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.285135 (XEN) No periodic timer Jul 1 06:11:27.296914 (XEN) UNIT64 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.296975 (XEN) VCPU64: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.308907 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.308967 (XEN) GICH_LRs (vcpu 64) mask=0 Jul 1 06:11:27.309013 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.309055 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.309096 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.320922 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.320978 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.321022 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.321063 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.321104 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.321145 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.332911 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.332968 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.333010 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.333052 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.333093 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.333134 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.344920 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.344976 (XEN) No periodic timer Jul 1 06:11:27.345020 (XEN) UNIT65 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.345068 (XEN) VCPU65: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.356941 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.357007 (XEN) GICH_LRs (vcpu 65) mask=0 Jul 1 06:11:27.357053 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.368914 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.369002 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.369049 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.369090 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.369131 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.369172 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.380927 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.380985 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.381029 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.381070 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.381112 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.392920 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.392977 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.393020 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.393062 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.393103 (XEN) No periodic timer Jul 1 06:11:27.393146 (XEN) UNIT66 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.404925 (XEN) VCPU66: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.404990 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.416918 (XEN) GICH_LRs (vcpu 66) mask=0 Jul 1 06:11:27.416977 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.417021 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.417062 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.417103 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.417144 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.428914 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.428970 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.429013 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.429054 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.429095 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.429136 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.440934 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.440994 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.441037 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.441078 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.441120 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.441162 (XEN) No periodic timer Jul 1 06:11:27.452918 (XEN) UNIT67 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.452979 (XEN) VCPU67: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.464917 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.464977 (XEN) GICH_LRs (vcpu 67) mask=0 Jul 1 06:11:27.465022 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.465065 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.465106 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.476903 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.476959 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.477002 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.477043 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.477084 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.488903 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.488960 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.489003 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.489044 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.489085 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.489125 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.500922 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.500978 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.501020 (XEN) No periodic timer Jul 1 06:11:27.501062 (XEN) UNIT68 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.501109 (XEN) VCPU68: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.512934 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.512993 (XEN) GICH_LRs (vcpu 68) mask=0 Jul 1 06:11:27.524910 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.524967 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.525010 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.525052 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.525095 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.525136 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.536911 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.536968 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.537011 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.537053 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.537093 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.537134 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.548911 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.548968 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.549011 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.549053 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.549094 (XEN) No periodic timer Jul 1 06:11:27.549137 (XEN) UNIT69 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.560916 (XEN) VCPU69: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.561018 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.572921 (XEN) GICH_LRs (vcpu 69) mask=0 Jul 1 06:11:27.572980 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.573023 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.573064 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.573105 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.573145 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.584915 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.584970 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.585012 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.585054 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.585096 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.585137 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.596924 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.596980 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.597023 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.597064 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.597106 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.608892 (XEN) No periodic timer Jul 1 06:11:27.608949 (XEN) UNIT70 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.608998 (XEN) VCPU70: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.620910 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.620969 (XEN) GICH_LRs (vcpu 70) mask=0 Jul 1 06:11:27.621015 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.621056 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.632916 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.632972 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.633015 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.633057 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.633098 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.633139 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.644916 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.644973 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.645017 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.645058 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.645100 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.645142 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.656913 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.656969 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.657012 (XEN) No periodic timer Jul 1 06:11:27.657054 (XEN) UNIT71 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.668911 (XEN) VCPU71: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.668976 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.669023 (XEN) GICH_LRs (vcpu 71) mask=0 Jul 1 06:11:27.680912 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.680969 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.681013 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.681055 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.681096 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.681137 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.692892 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.692948 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.692991 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.693033 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.693074 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.693116 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.704915 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.704971 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.705014 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.705056 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.705098 (XEN) No periodic timer Jul 1 06:11:27.705140 (XEN) UNIT72 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.716924 (XEN) VCPU72: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.716988 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.728918 (XEN) GICH_LRs (vcpu 72) mask=0 Jul 1 06:11:27.728978 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.729021 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.729062 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.729102 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.740894 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.740951 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.740995 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.741037 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.741078 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.752915 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.752973 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.753017 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.753058 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.753100 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.753141 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.764915 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.764991 (XEN) No periodic timer Jul 1 06:11:27.765037 (XEN) UNIT73 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.765085 (XEN) VCPU73: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.776916 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.776974 (XEN) GICH_LRs (vcpu 73) mask=0 Jul 1 06:11:27.777020 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.777063 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.788912 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.788967 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.789009 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.789051 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.789091 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.789132 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.800917 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.800973 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.801016 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.801058 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.801100 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.801141 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.812908 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.812964 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.813007 (XEN) No periodic timer Jul 1 06:11:27.813050 (XEN) UNIT74 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.824921 (XEN) VCPU74: CPU36 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.824986 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.825033 (XEN) GICH_LRs (vcpu 74) mask=0 Jul 1 06:11:27.836898 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.836954 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.836997 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.837039 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.837080 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.837121 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.848913 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.848970 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.849012 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.849054 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.849095 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.849135 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.860899 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.860955 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.860999 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.861040 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.861081 (XEN) No periodic timer Jul 1 06:11:27.872909 (XEN) UNIT75 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.872971 (XEN) VCPU75: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.884906 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.884966 (XEN) GICH_LRs (vcpu 75) mask=0 Jul 1 06:11:27.885012 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.885054 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.885096 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.896909 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.896965 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.897008 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.897050 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.897092 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.897133 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.908910 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.908967 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.909011 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.909052 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.909093 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.909135 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.920914 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.920970 (XEN) No periodic timer Jul 1 06:11:27.921014 (XEN) UNIT76 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.921061 (XEN) VCPU76: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.932920 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.932978 (XEN) GICH_LRs (vcpu 76) mask=0 Jul 1 06:11:27.933024 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.944909 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.944966 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.945009 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.945050 (XEN) VCPU_LR[4]=0 Jul 1 06:11:27.945091 (XEN) VCPU_LR[5]=0 Jul 1 06:11:27.945132 (XEN) VCPU_LR[6]=0 Jul 1 06:11:27.956909 (XEN) VCPU_LR[7]=0 Jul 1 06:11:27.956967 (XEN) VCPU_LR[8]=0 Jul 1 06:11:27.957010 (XEN) VCPU_LR[9]=0 Jul 1 06:11:27.957051 (XEN) VCPU_LR[10]=0 Jul 1 06:11:27.957092 (XEN) VCPU_LR[11]=0 Jul 1 06:11:27.957152 (XEN) VCPU_LR[12]=0 Jul 1 06:11:27.968908 (XEN) VCPU_LR[13]=0 Jul 1 06:11:27.968965 (XEN) VCPU_LR[14]=0 Jul 1 06:11:27.969008 (XEN) VCPU_LR[15]=0 Jul 1 06:11:27.969050 (XEN) No periodic timer Jul 1 06:11:27.969093 (XEN) UNIT77 affinities: hard={0-95} soft={0-95} Jul 1 06:11:27.980914 (XEN) VCPU77: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:27.980978 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:27.981023 (XEN) GICH_LRs (vcpu 77) mask=0 Jul 1 06:11:27.992897 (XEN) VCPU_LR[0]=0 Jul 1 06:11:27.992953 (XEN) VCPU_LR[1]=0 Jul 1 06:11:27.992997 (XEN) VCPU_LR[2]=0 Jul 1 06:11:27.993038 (XEN) VCPU_LR[3]=0 Jul 1 06:11:27.993079 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.004915 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.004971 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.005013 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.005054 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.005095 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.005136 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.016925 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.016981 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.017024 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.017066 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.017107 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.017148 (XEN) No periodic timer Jul 1 06:11:28.028913 (XEN) UNIT78 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.028975 (XEN) VCPU78: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.040912 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.040971 (XEN) GICH_LRs (vcpu 78) mask=0 Jul 1 06:11:28.041017 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.041059 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.041100 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.052914 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.052970 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.053013 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.053054 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.053095 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.053137 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.064906 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.064963 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.065006 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.065048 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.065089 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.065130 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.076919 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.076976 (XEN) No periodic timer Jul 1 06:11:28.077019 (XEN) UNIT79 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.077067 (XEN) VCPU79: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.088913 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.088971 (XEN) GICH_LRs (vcpu 79) mask=0 Jul 1 06:11:28.089016 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.100925 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.100981 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.101024 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.101066 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.101107 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.101148 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.112897 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.112953 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.112997 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.113038 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.113079 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.124909 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.124965 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.125008 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.125050 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.125092 (XEN) No periodic timer Jul 1 06:11:28.125134 (XEN) UNIT80 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.136918 (XEN) VCPU80: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.136983 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.148914 (XEN) GICH_LRs (vcpu 80) mask=0 Jul 1 06:11:28.148973 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.149016 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.149057 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.149097 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.149138 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.160918 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.160974 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.161038 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.161083 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.161124 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.161165 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.172907 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.172964 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.173007 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.173049 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.173090 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.184911 (XEN) No periodic timer Jul 1 06:11:28.184969 (XEN) UNIT81 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.185018 (XEN) VCPU81: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.196921 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.196980 (XEN) GICH_LRs (vcpu 81) mask=0 Jul 1 06:11:28.197026 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.197068 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.197109 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.208913 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.208969 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.209012 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.209054 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.209095 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.209136 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.220922 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.220978 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.221020 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.221061 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.221102 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.221143 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.232925 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.232981 (XEN) No periodic timer Jul 1 06:11:28.233024 (XEN) UNIT82 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.233071 (XEN) VCPU82: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.244900 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.244960 (XEN) GICH_LRs (vcpu 82) mask=0 Jul 1 06:11:28.256917 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.256974 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.257017 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.257059 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.257100 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.257141 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.268913 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.268970 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.269013 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.269055 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.269096 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.269137 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.280910 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.280966 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.281010 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.281051 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.281092 (XEN) No periodic timer Jul 1 06:11:28.281134 (XEN) UNIT83 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.292918 (XEN) VCPU83: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.292982 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.304913 (XEN) GICH_LRs (vcpu 83) mask=0 Jul 1 06:11:28.304972 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.305015 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.305056 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.305097 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.316817 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.316817 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.316817 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.316817 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.316817 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.316817 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.328926 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.328989 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.329033 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.329075 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.329117 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.329158 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.340914 (XEN) No periodic timer Jul 1 06:11:28.340971 (XEN) UNIT84 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.341020 (XEN) VCPU84: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.352913 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.352972 (XEN) GICH_LRs (vcpu 84) mask=0 Jul 1 06:11:28.353017 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.353059 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.353100 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.364925 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.364982 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.365025 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.365066 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.365106 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.365146 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.376912 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.376968 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.377010 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.377052 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.377093 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.388915 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.388971 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.389014 (XEN) No periodic timer Jul 1 06:11:28.389056 (XEN) UNIT85 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.400910 (XEN) VCPU85: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.400975 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.401021 (XEN) GICH_LRs (vcpu 85) mask=0 Jul 1 06:11:28.412917 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.412974 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.413017 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.413059 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.413101 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.413143 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.424915 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.424971 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.425014 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.425055 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.425096 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.425137 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.436877 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.436933 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.436977 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.437018 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.437059 (XEN) No periodic timer Jul 1 06:11:28.437101 (XEN) UNIT86 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.448920 (XEN) VCPU86: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.448985 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.460916 (XEN) GICH_LRs (vcpu 86) mask=0 Jul 1 06:11:28.460974 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.461017 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.461059 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.461100 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.472910 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.472967 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.473011 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.473053 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.473095 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.473136 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.484917 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.484974 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.485017 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.485059 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.485100 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.485140 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.496891 (XEN) No periodic timer Jul 1 06:11:28.496947 (XEN) UNIT87 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.496996 (XEN) VCPU87: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.508918 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.508976 (XEN) GICH_LRs (vcpu 87) mask=0 Jul 1 06:11:28.509022 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.509064 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.520920 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.520976 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.521019 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.521061 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.521101 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.521142 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.532917 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.532973 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.533016 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.533057 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.533098 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.533139 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.544917 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.544974 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.545017 (XEN) No periodic timer Jul 1 06:11:28.545059 (XEN) UNIT88 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.556911 (XEN) VCPU88: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.556976 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.557052 (XEN) GICH_LRs (vcpu 88) mask=0 Jul 1 06:11:28.568907 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.568964 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.569007 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.569048 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.569123 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.569170 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.580924 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.580980 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.581023 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.581065 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.581107 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.581149 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.592914 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.592971 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.593014 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.593055 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.593097 (XEN) No periodic timer Jul 1 06:11:28.593140 (XEN) UNIT89 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.604922 (XEN) VCPU89: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.604986 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.616912 (XEN) GICH_LRs (vcpu 89) mask=0 Jul 1 06:11:28.616970 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.617013 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.617054 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.617095 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.628898 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.628954 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.628998 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.629039 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.629080 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.640930 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.641001 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.641047 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.641089 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.641130 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.641171 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.652914 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.652971 (XEN) No periodic timer Jul 1 06:11:28.653015 (XEN) UNIT90 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.653063 (XEN) VCPU90: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.664919 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.664978 (XEN) GICH_LRs (vcpu 90) mask=0 Jul 1 06:11:28.665023 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.676893 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.676893 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.676893 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.676893 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.676893 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.676893 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.688916 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.688978 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.689021 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.689063 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.689104 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.689145 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.700925 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.700982 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.701024 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.701066 (XEN) No periodic timer Jul 1 06:11:28.701108 (XEN) UNIT91 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.712912 (XEN) VCPU91: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.712977 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.713023 (XEN) GICH_LRs (vcpu 91) mask=0 Jul 1 06:11:28.724918 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.724918 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.724918 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.724918 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.724918 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.724918 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.736783 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.736783 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.736783 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.736783 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.736783 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.736783 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.748896 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.748957 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.748997 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.748997 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.748997 (XEN) No periodic timer Jul 1 06:11:28.760783 (XEN) UNIT92 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.760783 (XEN) VCPU92: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.772786 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.772786 (XEN) GICH_LRs (vcpu 92) mask=0 Jul 1 06:11:28.772786 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.772786 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.772786 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.784783 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.784783 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.784783 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.784783 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.784783 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.784783 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.796782 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.796782 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.796782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.796782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.796782 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.796782 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.808778 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.808778 (XEN) No periodic timer Jul 1 06:11:28.808778 (XEN) UNIT93 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.808778 (XEN) VCPU93: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.820917 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.820981 (XEN) GICH_LRs (vcpu 93) mask=0 Jul 1 06:11:28.821027 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.832786 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.832786 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.832786 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.832786 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.832786 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.832786 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.844782 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.844782 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.844782 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.844782 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.844782 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.844782 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.856782 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.856782 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.856782 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.856782 (XEN) No periodic timer Jul 1 06:11:28.856782 (XEN) UNIT94 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.868782 (XEN) VCPU94: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.868782 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.868782 (XEN) GICH_LRs (vcpu 94) mask=0 Jul 1 06:11:28.880774 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.880774 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.880774 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.880774 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.880774 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.892783 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.892783 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.892783 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.892783 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.892783 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.892783 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.904786 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.904786 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.904786 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.904786 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.904786 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.916784 (XEN) No periodic timer Jul 1 06:11:28.916784 (XEN) UNIT95 affinities: hard={0-95} soft={0-95} Jul 1 06:11:28.916784 (XEN) VCPU95: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Jul 1 06:11:28.928783 (XEN) pause_count=0 pause_flags=1 Jul 1 06:11:28.928783 (XEN) GICH_LRs (vcpu 95) mask=0 Jul 1 06:11:28.928783 (XEN) VCPU_LR[0]=0 Jul 1 06:11:28.928783 (XEN) VCPU_LR[1]=0 Jul 1 06:11:28.928783 (XEN) VCPU_LR[2]=0 Jul 1 06:11:28.940783 (XEN) VCPU_LR[3]=0 Jul 1 06:11:28.940783 (XEN) VCPU_LR[4]=0 Jul 1 06:11:28.940783 (XEN) VCPU_LR[5]=0 Jul 1 06:11:28.940783 (XEN) VCPU_LR[6]=0 Jul 1 06:11:28.940783 (XEN) VCPU_LR[7]=0 Jul 1 06:11:28.940783 (XEN) VCPU_LR[8]=0 Jul 1 06:11:28.952783 (XEN) VCPU_LR[9]=0 Jul 1 06:11:28.952783 (XEN) VCPU_LR[10]=0 Jul 1 06:11:28.952783 (XEN) VCPU_LR[11]=0 Jul 1 06:11:28.952783 (XEN) VCPU_LR[12]=0 Jul 1 06:11:28.952783 (XEN) VCPU_LR[13]=0 Jul 1 06:11:28.952783 (XEN) VCPU_LR[14]=0 Jul 1 06:11:28.964785 (XEN) VCPU_LR[15]=0 Jul 1 06:11:28.964785 (XEN) No periodic timer Jul 1 06:11:28.964785 (XEN) Notifying guest 0:0 (virq 1, port 0) Jul 1 06:11:28.964785 (XEN) Notifying guest 0:1 (virq 1, port 0) Jul 1 06:11:28.976785 (XEN) Notifying guest 0:2 (virq 1, port 0) Jul 1 06:11:28.976785 (XEN) Notifying guest 0:3 (virq 1, port 0) Jul 1 06:11:28.976785 (XEN) Notifying guest 0:4 (virq 1, port 0) Jul 1 06:11:28.988780 (XEN) Notifying guest 0:5 (virq 1, port 0) Jul 1 06:11:28.988780 (XEN) Notifying guest 0:6 (virq 1, port 0) Jul 1 06:11:28.988780 (XEN) Notifying guest 0:7 (virq 1, port 0) Jul 1 06:11:29.000773 (XEN) Notifying guest 0:8 (virq 1, port 0) Jul 1 06:11:29.000773 (XEN) Notifying guest 0:9 (virq 1, port 0) Jul 1 06:11:29.000773 (XEN) Notifying guest 0:10 (virq 1, port 0) Jul 1 06:11:29.012771 (XEN) Notifying guest 0:11 (virq 1, port 0) Jul 1 06:11:29.012771 (XEN) Notifying guest 0:12 (virq 1, port 0) Jul 1 06:11:29.012771 (XEN) Notifying guest 0:13 (virq 1, port 0) Jul 1 06:11:29.024785 (XEN) Notifying guest 0:14 (virq 1, port 0) Jul 1 06:11:29.024785 (XEN) Notifying guest 0:15 (virq 1, port 0) Jul 1 06:11:29.024785 (XEN) Notifying guest 0:16 (virq 1, port 0) Jul 1 06:11:29.036783 (XEN) Notifying guest 0:17 (virq 1, port 0) Jul 1 06:11:29.036783 (XEN) Notifying guest 0:18 (virq 1, port 0) Jul 1 06:11:29.036783 (XEN) Notifying guest 0:19 (virq 1, port 0) Jul 1 06:11:29.048781 (XEN) Notifying guest 0:20 (virq 1, port 0) Jul 1 06:11:29.048781 (XEN) Notifying guest 0:21 (virq 1, port 0) Jul 1 06:11:29.048781 (XEN) Notifying guest 0:22 (virq 1, port 0) Jul 1 06:11:29.060785 (XEN) Notifying guest 0:23 (virq 1, port 0) Jul 1 06:11:29.060785 (XEN) Notifying guest 0:24 (virq 1, port 0) Jul 1 06:11:29.060785 (XEN) Notifying guest 0:25 (virq 1, port 0) Jul 1 06:11:29.072787 (XEN) Notifying guest 0:26 (virq 1, port 0) Jul 1 06:11:29.072787 (XEN) Notifying guest 0:27 (virq 1, port 0) Jul 1 06:11:29.072787 (XEN) Notifying guest 0:28 (virq 1, port 0) Jul 1 06:11:29.084785 (XEN) Notifying guest 0:29 (virq 1, port 0) Jul 1 06:11:29.084785 (XEN) Notifying guest 0:30 (virq 1, port 0) Jul 1 06:11:29.084785 (XEN) Notifying guest 0:31 (virq 1, port 0) Jul 1 06:11:29.084785 (XEN) Notifying guest 0:32 (virq 1, port 0) Jul 1 06:11:29.096782 (XEN) Notifying guest 0:33 (virq 1, port 0) Jul 1 06:11:29.096782 (XEN) Notifying guest 0:34 (virq 1, port 0) Jul 1 06:11:29.096782 (XEN) Notifying guest 0:35 (virq 1, port 0) Jul 1 06:11:29.108783 (XEN) Notifying guest 0:36 (virq 1, port 0) Jul 1 06:11:29.108783 (XEN) Notifying guest 0:37 (virq 1, port 0) Jul 1 06:11:29.108783 (XEN) Notifying guest 0:38 (virq 1, port 0) Jul 1 06:11:29.120784 (XEN) Notifying guest 0:39 (virq 1, port 0) Jul 1 06:11:29.120784 (XEN) Notifying guest 0:40 (virq 1, port 0) Jul 1 06:11:29.120784 (XEN) Notifying guest 0:41 (virq 1, port 0) Jul 1 06:11:29.132775 (XEN) Notifying guest 0:42 (virq 1, port 0) Jul 1 06:11:29.132775 (XEN) Notifying guest 0:43 (virq 1, port 0) Jul 1 06:11:29.144786 (XEN) Notifying guest 0:44 (virq 1, port 0) Jul 1 06:11:29.144786 (XEN) Notifying guest 0:45 (virq 1, port 0) Jul 1 06:11:29.144786 (XEN) Notifying guest 0:46 (virq 1, port 0) Jul 1 06:11:29.156782 (XEN) Notifying guest 0:47 (virq 1, port 0) Jul 1 06:11:29.156782 (XEN) Notifying guest 0:48 (virq 1, port 0) Jul 1 06:11:29.156782 (XEN) Notifying guest 0:49 (virq 1, port 0) Jul 1 06:11:29.156782 (XEN) Notifying guest 0:50 (virq 1, port 0) Jul 1 06:11:29.168780 (XEN) Notifying guest 0:51 (virq 1, port 0) Jul 1 06:11:29.168780 (XEN) Notifying guest 0:52 (virq 1, port 0) Jul 1 06:11:29.168780 (XEN) Notifying guest 0:53 (virq 1, port 0) Jul 1 06:11:29.180815 (XEN) Notifying guest 0:54 (virq 1, port 0) Jul 1 06:11:29.180887 (XEN) Notifying guest 0:55 (virq 1, port 0) Jul 1 06:11:29.180887 (XEN) Notifying guest 0:56 (virq 1, port 0) Jul 1 06:11:29.192974 (XEN) Notifying guest 0:57 (virq 1, port 0) Jul 1 06:11:29.193040 (XEN) Notifying guest 0:58 (virq 1, port 0) Jul 1 06:11:29.193086 (XEN) Notifying guest 0:59 (virq 1, port 0) Jul 1 06:11:29.204935 (XEN) Notifying guest 0:60 (virq 1, port 0) Jul 1 06:11:29.204995 (XEN) Notifying guest 0:61 (virq 1, port 0) Jul 1 06:11:29.205041 (XEN) Notifying guest 0:62 (virq 1, port 0) Jul 1 06:11:29.216826 (XEN) Notifying guest 0:63 (virq 1, port 0) Jul 1 06:11:29.216826 (XEN) Notifying guest 0:64 (virq 1, port 0) Jul 1 06:11:29.216826 (XEN) Notifying guest 0:65 (virq 1, port 0) Jul 1 06:11:29.228935 (XEN) Notifying guest 0:66 (virq 1, port 0) Jul 1 06:11:29.228998 (XEN) Notifying guest 0:67 (virq 1, port 0) Jul 1 06:11:29.229045 (XEN) Notifying guest 0:68 (virq 1, port 0) Jul 1 06:11:29.240919 (XEN) Notifying guest 0:69 (virq 1, port 0) Jul 1 06:11:29.240980 (XEN) Notifying guest 0:70 (virq 1, port 0) Jul 1 06:11:29.241026 (XEN) Notifying guest 0:71 (virq 1, port 0) Jul 1 06:11:29.252924 (XEN) Notifying guest 0:72 (virq 1, port 0) Jul 1 06:11:29.252983 (XEN) Notifying guest 0:73 (virq 1, port 0) Jul 1 06:11:29.253031 (XEN) Notifying guest 0:74 (virq 1, port 0) Jul 1 06:11:29.264903 (XEN) Notifying guest 0:75 (virq 1, port 0) Jul 1 06:11:29.264964 (XEN) Notifying guest 0:76 (virq 1, port 0) Jul 1 06:11:29.265010 (XEN) Notifying guest 0:77 (virq 1, port 0) Jul 1 06:11:29.276930 (XEN) Notifying guest 0:78 (virq 1, port 0) Jul 1 06:11:29.276990 (XEN) Notifying guest 0:79 (virq 1, port 0) Jul 1 06:11:29.277037 (XEN) Notifying guest 0:80 (virq 1, port 0) Jul 1 06:11:29.288920 (XEN) Notifying guest 0:81 (virq 1, port 0) Jul 1 06:11:29.288980 (XEN) Notifying guest 0:82 (virq 1, port 0) Jul 1 06:11:29.289026 (XEN) Notifying guest 0:83 (virq 1, port 0) Jul 1 06:11:29.300924 (XEN) Notifying guest 0:84 (virq 1, port 0) Jul 1 06:11:29.300984 (XEN) Notifying guest 0:85 (virq 1, port 0) Jul 1 06:11:29.301031 (XEN) Notifying guest 0:86 (virq 1, port 0) Jul 1 06:11:29.312920 (XEN) Notifying guest 0:87 (virq 1, port 0) Jul 1 06:11:29.312980 (XEN) Notifying guest 0:88 (virq 1, port 0) Jul 1 06:11:29.313025 (XEN) Notifying guest 0:89 (virq 1, port 0) Jul 1 06:11:29.324929 (XEN) Notifying guest 0:90 (virq 1, port 0) Jul 1 06:11:29.324989 (XEN) Notifying guest 0:91 (virq 1, port 0) Jul 1 06:11:29.325035 (XEN) Notifying guest 0:92 (virq 1, port 0) Jul 1 06:11:29.336920 (XEN) Notifying guest 0:93 (virq 1, port 0) Jul 1 06:11:29.336979 (XEN) Notifying guest 0:94 (virq 1, port 0) Jul 1 06:11:29.337026 (XEN) Notifying guest 0:95 (virq 1, port 0) Jul 1 06:11:29.348862 Jul 1 06:11:35.838390 (XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input) Jul 1 06:11:35.864928 Jul 1 06:11:35.866317