Sep 10 07:54:32.375410 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:32.375410 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:32.384849 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:32.384911 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:32.384982 (XEN) Sep 10 07:54:32.385023 (XEN) *** Dumping CPU83 host state: *** Sep 10 07:54:32.397485 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:32.397485 (XEN) CPU: 83 Sep 10 07:54:32.397485 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:32.409460 (XEN) LR: 00000a0000278470 Sep 10 07:54:32.409460 (XEN) SP: 0000800ffde67e60 Sep 10 07:54:32.409460 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:32.421464 (XEN) X0: 0000000000000000 X1: 0000760ffdb2a000 X2: 0000800ffde72078 Sep 10 07:54:32.421464 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:32.433118 (XEN) X6: 00000a000038a5c8 X7: 0000800ffde75280 X8: 0000000000000012 Sep 10 07:54:32.444852 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Sep 10 07:54:32.444917 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Sep 10 07:54:32.456858 (XEN) X15: ffff000025f0220c X16: ffff8000092a0fb8 X17: 0000000000000000 Sep 10 07:54:32.456923 (XEN) X18: ffff80000cfebc58 X19: 00000a000038a5d0 X20: 0000000000000053 Sep 10 07:54:32.468867 (XEN) X21: 00000a000034fe00 X22: 0000000000080000 X23: 0000000000000053 Sep 10 07:54:32.468930 (XEN) X24: 0000000000000053 X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:32.480859 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde67e60 Sep 10 07:54:32.480945 (XEN) Sep 10 07:54:32.480987 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:32.492861 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:32.492919 (XEN) Sep 10 07:54:32.492960 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:32.493027 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:32.504854 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:32.504913 (XEN) Sep 10 07:54:32.504954 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:32.504999 (XEN) HPFAR_EL2: 0000008010802300 Sep 10 07:54:32.505066 (XEN) FAR_EL2: ffff80000aa30100 Sep 10 07:54:32.516862 (XEN) Sep 10 07:54:32.516916 (XEN) Xen stack trace from sp=0000800ffde67e60: Sep 10 07:54:32.516964 (XEN) 0000800ffde67e70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:32.528864 (XEN) 0000000000000053 0000000000000000 0000000000000000 0000000000010203 Sep 10 07:54:32.528948 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.540855 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.540918 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.552859 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.552922 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.564872 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.576856 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.576918 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.588857 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.588920 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.600861 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.600924 (XEN) Xen call trace: Sep 10 07:54:32.612853 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:32.612919 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:32.627490 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:32.627583 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:32.627631 (XEN) Sep 10 07:54:32.639511 (XEN) *** Dumping CPU84 host state: *** Sep 10 07:54:32.639571 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:32.639622 (XEN) CPU: 84 Sep 10 07:54:32.639685 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:32.650676 (XEN) LR: 00000a0000278470 Sep 10 07:54:32.650735 (XEN) SP: 0000800ffd9f7e60 Sep 10 07:54:32.650779 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:32.663419 (XEN) X0: 0000000000000000 X1: 0000760ffdb28000 X2: 0000800ffde70078 Sep 10 07:54:32.663419 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:32.675411 (XEN) X6: 00000a000038a5c8 X7: 0000800ffde75740 X8: 0000000000000012 Sep 10 07:54:32.687407 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Sep 10 07:54:32.687407 (XEN) X12: 0000000000000001 X13: 000000000000027c X14: 000000000000027c Sep 10 07:54:32.699412 (XEN) X15: 0000aaaaef3c9ca0 X16: 0000000000000000 X17: 0000000000000000 Sep 10 07:54:32.699412 (XEN) X18: 0000000000000000 X19: 00000a000038a5d0 X20: 0000000000000054 Sep 10 07:54:32.711411 (XEN) X21: 00000a000034fe80 X22: 0000000000100000 X23: 0000000000000054 Sep 10 07:54:32.711411 (XEN) X24: 0000000000000054 X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:32.723411 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd9f7e60 Sep 10 07:54:32.735415 (XEN) Sep 10 07:54:32.735415 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:32.735415 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:32.735415 (XEN) Sep 10 07:54:32.735415 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:32.735415 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:32.747407 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:32.747407 (XEN) Sep 10 07:54:32.747407 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:32.747407 (XEN) HPFAR_EL2: 0000008010802f00 Sep 10 07:54:32.747407 (XEN) FAR_EL2: ffff80000aaf0100 Sep 10 07:54:32.759413 (XEN) Sep 10 07:54:32.759413 (XEN) Xen stack trace from sp=0000800ffd9f7e60: Sep 10 07:54:32.759413 (XEN) 0000800ffd9f7e70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:32.771406 (XEN) 0000000000000054 0000000000000000 0000000000000000 0000000000010204 Sep 10 07:54:32.771406 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.783418 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.783418 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.795413 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.807411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.807411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.819387 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.819387 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.831401 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.831401 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.843412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:32.855407 (XEN) Xen call trace: Sep 10 07:54:32.855407 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:32.855407 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:32.867410 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:32.867410 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:32.879406 (XEN) Sep 10 07:54:32.879406 (XEN) *** Dumping CPU85 host state: *** Sep 10 07:54:32.879406 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:32.879406 (XEN) CPU: 85 Sep 10 07:54:32.891417 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:32.891417 (XEN) LR: 00000a0000278470 Sep 10 07:54:32.891417 (XEN) SP: 0000800ffd9efe60 Sep 10 07:54:32.891417 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:32.903525 (XEN) X0: 0000000000000000 X1: 0000760ffd6b4000 X2: 0000800ffd9fc078 Sep 10 07:54:32.915419 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:32.915419 (XEN) X6: 00000a000038a5c8 X7: 0000800ffde75c00 X8: 0000000000000012 Sep 10 07:54:32.927420 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Sep 10 07:54:32.927420 (XEN) X12: 0000000000000001 X13: 00000000000001ad X14: 00000000000001ad Sep 10 07:54:32.939419 (XEN) X15: 0000aaaafa6a6e30 X16: 0000000000000000 X17: 0000000000000000 Sep 10 07:54:32.939419 (XEN) X18: 0000000000000000 X19: 00000a000038a5d0 X20: 0000000000000055 Sep 10 07:54:32.951415 (XEN) X21: 00000a000034ff00 X22: 0000000000200000 X23: 0000000000000055 Sep 10 07:54:32.951415 (XEN) X24: 0000000000000055 X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:32.963415 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd9efe60 Sep 10 07:54:32.975420 (XEN) Sep 10 07:54:32.975420 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:32.975420 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:32.975420 (XEN) Sep 10 07:54:32.975420 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:32.975420 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:32.987417 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:32.987417 (XEN) Sep 10 07:54:32.987417 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:32.987417 (XEN) HPFAR_EL2: 0000008010803b00 Sep 10 07:54:32.999415 (XEN) FAR_EL2: ffff80000abb0100 Sep 10 07:54:32.999415 (XEN) Sep 10 07:54:32.999415 (XEN) Xen stack trace from sp=0000800ffd9efe60: Sep 10 07:54:32.999415 (XEN) 0000800ffd9efe70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:33.011405 (XEN) 0000000000000055 0000000000000000 0000000000000000 0000000000010205 Sep 10 07:54:33.011405 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.023412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.023412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.035408 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.047406 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.047406 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.059388 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.059388 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.071413 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.071413 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.083410 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.095405 (XEN) Xen call trace: Sep 10 07:54:33.095405 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:33.095405 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:33.107369 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:33.107369 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:33.119412 (XEN) Sep 10 07:54:33.119412 (XEN) *** Dumping CPU86 host state: *** Sep 10 07:54:33.119412 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:33.119412 (XEN) CPU: 86 Sep 10 07:54:33.131410 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:33.131410 (XEN) LR: 00000a0000278470 Sep 10 07:54:33.131410 (XEN) SP: 0000800ffd9e7e60 Sep 10 07:54:33.143403 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:33.143403 (XEN) X0: 0000000000000000 X1: 0000760ffd6b2000 X2: 0000800ffd9fa078 Sep 10 07:54:33.155409 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:33.155409 (XEN) X6: 00000a000038a5c8 X7: 0000800ffd9f8150 X8: 0000000000000012 Sep 10 07:54:33.167408 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Sep 10 07:54:33.167408 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Sep 10 07:54:33.179410 (XEN) X15: ffff0000301a800c X16: ffff8000092a0fb8 X17: 0000000000000000 Sep 10 07:54:33.179410 (XEN) X18: ffff80000d283c58 X19: 00000a000038a5d0 X20: 0000000000000056 Sep 10 07:54:33.191405 (XEN) X21: 00000a000034ff80 X22: 0000000000400000 X23: 0000000000000056 Sep 10 07:54:33.203410 (XEN) X24: 0000000000000056 X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:33.203410 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd9e7e60 Sep 10 07:54:33.215418 (XEN) Sep 10 07:54:33.215418 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:33.215418 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:33.215418 (XEN) Sep 10 07:54:33.215418 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:33.227411 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:33.227411 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:33.227411 (XEN) Sep 10 07:54:33.227411 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:33.227411 (XEN) HPFAR_EL2: 0000008010804700 Sep 10 07:54:33.239410 (XEN) FAR_EL2: ffff80000ac70100 Sep 10 07:54:33.239410 (XEN) Sep 10 07:54:33.239410 (XEN) Xen stack trace from sp=0000800ffd9e7e60: Sep 10 07:54:33.239410 (XEN) 0000800ffd9e7e70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:33.251407 (XEN) 0000000000000056 0000000000000000 0000000000000000 0000000000010206 Sep 10 07:54:33.251407 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.263408 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.275410 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.275410 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.287412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.287412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.299409 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.299409 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.311408 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.323410 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.323410 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.335411 (XEN) Xen call trace: Sep 10 07:54:33.335411 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:33.335411 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:33.347410 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:33.347410 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:33.359409 (XEN) Sep 10 07:54:33.359409 (XEN) *** Dumping CPU87 host state: *** Sep 10 07:54:33.359409 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:33.371407 (XEN) CPU: 87 Sep 10 07:54:33.371407 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:33.371407 (XEN) LR: 00000a0000278470 Sep 10 07:54:33.371407 (XEN) SP: 0000800ffd997e60 Sep 10 07:54:33.383411 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:33.383411 (XEN) X0: 0000000000000000 X1: 0000760ffd656000 X2: 0000800ffd99e078 Sep 10 07:54:33.395417 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:33.395417 (XEN) X6: 00000a000038a5c8 X7: 0000800ffd9f8590 X8: 0000000000000012 Sep 10 07:54:33.407420 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Sep 10 07:54:33.407420 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Sep 10 07:54:33.419414 (XEN) X15: 00000000284efb00 X16: 0000000000000001 X17: 0000000000000230 Sep 10 07:54:33.419414 (XEN) X18: ffff80000daf3ac8 X19: 00000a000038a5d0 X20: 0000000000000057 Sep 10 07:54:33.431408 (XEN) X21: 00000a0000350000 X22: 0000000000800000 X23: 0000000000000057 Sep 10 07:54:33.443415 (XEN) X24: 0000000000000057 X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:33.443415 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd997e60 Sep 10 07:54:33.455417 (XEN) Sep 10 07:54:33.455417 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:33.455417 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:33.455417 (XEN) Sep 10 07:54:33.455417 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:33.467410 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:33.467410 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:33.467410 (XEN) Sep 10 07:54:33.467410 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:33.467410 (XEN) HPFAR_EL2: 0000008010805300 Sep 10 07:54:33.479421 (XEN) FAR_EL2: ffff80000ad30100 Sep 10 07:54:33.479421 (XEN) Sep 10 07:54:33.479421 (XEN) Xen stack trace from sp=0000800ffd997e60: Sep 10 07:54:33.479421 (XEN) 0000800ffd997e70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:33.491416 (XEN) 0000000000000057 0000000000000000 0000000000000000 0000000000010207 Sep 10 07:54:33.503414 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.503414 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.515417 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.515417 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.527416 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.527416 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.539416 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.539416 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.551417 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.563413 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.563413 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.575417 (XEN) Xen call trace: Sep 10 07:54:33.575417 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:33.575417 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:33.587412 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:33.587412 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:33.599415 (XEN) Sep 10 07:54:33.599415 (XEN) *** Dumping CPU88 host state: *** Sep 10 07:54:33.599415 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:33.611411 (XEN) CPU: 88 Sep 10 07:54:33.611411 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:33.611411 (XEN) LR: 00000a0000278470 Sep 10 07:54:33.611411 (XEN) SP: 0000800ffd98fe60 Sep 10 07:54:33.623421 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:33.623421 (XEN) X0: 0000000000000000 X1: 0000760ffd652000 X2: 0000800ffd99a078 Sep 10 07:54:33.635414 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:33.635414 (XEN) X6: 00000a000038a5c8 X7: 0000800ffd9f8a50 X8: 0000000000000012 Sep 10 07:54:33.647418 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Sep 10 07:54:33.647418 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Sep 10 07:54:33.659417 (XEN) X15: ffff00003133420c X16: 0000000000000001 X17: 0000000000000216 Sep 10 07:54:33.671411 (XEN) X18: ffff80000daebc58 X19: 00000a000038a5d0 X20: 0000000000000058 Sep 10 07:54:33.671411 (XEN) X21: 00000a0000350080 X22: 0000000001000000 X23: 0000000000000058 Sep 10 07:54:33.683405 (XEN) X24: 0000000000000058 X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:33.683405 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd98fe60 Sep 10 07:54:33.695411 (XEN) Sep 10 07:54:33.695411 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:33.695411 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:33.695411 (XEN) Sep 10 07:54:33.695411 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:33.707409 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:33.707409 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:33.707409 (XEN) Sep 10 07:54:33.707409 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:33.719410 (XEN) HPFAR_EL2: 0000008010805f00 Sep 10 07:54:33.719410 (XEN) FAR_EL2: ffff80000adf0100 Sep 10 07:54:33.719410 (XEN) Sep 10 07:54:33.719410 (XEN) Xen stack trace from sp=0000800ffd98fe60: Sep 10 07:54:33.719410 (XEN) 0000800ffd98fe70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:33.731408 (XEN) 0000000000000058 0000000000000000 0000000000000000 0000000000010208 Sep 10 07:54:33.743409 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.743409 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.755406 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.755406 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.767408 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.767408 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.779408 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.791411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.791411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.803411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.803411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.815423 (XEN) Xen call trace: Sep 10 07:54:33.815423 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:33.827406 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:33.827406 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:33.827406 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:33.839409 (XEN) Sep 10 07:54:33.839409 (XEN) *** Dumping CPU89 host state: *** Sep 10 07:54:33.839409 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:33.851414 (XEN) CPU: 89 Sep 10 07:54:33.851414 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:33.851414 (XEN) LR: 00000a0000278470 Sep 10 07:54:33.863411 (XEN) SP: 0000800ffd91fe60 Sep 10 07:54:33.863411 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:33.863411 (XEN) X0: 0000000000000000 X1: 0000760ffd650000 X2: 0000800ffd998078 Sep 10 07:54:33.875406 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:33.875406 (XEN) X6: 00000a000038a5c8 X7: 0000800ffd986010 X8: 0000000000000012 Sep 10 07:54:33.887406 (XEN) X9: 0000000000000080 X10: 0000016e26f2221e X11: 0000000000000000 Sep 10 07:54:33.899414 (XEN) X12: 0000000000000000 X13: 0000000000000314 X14: 0000000000000340 Sep 10 07:54:33.899414 (XEN) X15: 00003d0900000000 X16: 0000000000000001 X17: 0000000000000000 Sep 10 07:54:33.911409 (XEN) X18: ffff80000c6e3d48 X19: 00000a000038a5d0 X20: 0000000000000059 Sep 10 07:54:33.911591 (XEN) X21: 00000a0000350100 X22: 0000000002000000 X23: 0000000000000059 Sep 10 07:54:33.938195 (XEN) X24: 0000000000000059 X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:33.938273 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd91fe60 Sep 10 07:54:33.938341 (XEN) Sep 10 07:54:33.938341 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:33.938341 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:33.938341 (XEN) Sep 10 07:54:33.938341 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:33.947407 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:33.947407 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:33.947407 (XEN) Sep 10 07:54:33.947407 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:33.959410 (XEN) HPFAR_EL2: 0000009010800b00 Sep 10 07:54:33.959410 (XEN) FAR_EL2: ffff80000b0b0100 Sep 10 07:54:33.959410 (XEN) Sep 10 07:54:33.959410 (XEN) Xen stack trace from sp=0000800ffd91fe60: Sep 10 07:54:33.971409 (XEN) 0000800ffd91fe70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:33.971409 (XEN) 0000000000000059 0000000000000000 0000000000000000 0000000000010209 Sep 10 07:54:33.983410 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.983410 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.995411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:33.995411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.007411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.007411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.019423 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.031412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.031412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.043418 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.043418 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.055415 (XEN) Xen call trace: Sep 10 07:54:34.055415 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:34.067416 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:34.067416 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:34.079425 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:34.079425 (XEN) Sep 10 07:54:34.079425 (XEN) *** Dumping CPU90 host state: *** Sep 10 07:54:34.079425 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:34.091413 (XEN) CPU: 90 Sep 10 07:54:34.091413 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:34.091413 (XEN) LR: 00000a0000278470 Sep 10 07:54:34.103414 (XEN) SP: 0000800ffd917e60 Sep 10 07:54:34.103414 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:34.103414 (XEN) X0: 0000000000000000 X1: 0000760ffd63c000 X2: 0000800ffd984078 Sep 10 07:54:34.115411 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:34.115411 (XEN) X6: 00000a000038a5c8 X7: 0000800ffd986410 X8: 0000000000000012 Sep 10 07:54:34.127413 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Sep 10 07:54:34.139410 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Sep 10 07:54:34.139410 (XEN) X15: ffff00002c4f170c X16: ffff8000092a0fb8 X17: 0000000000000000 Sep 10 07:54:34.151410 (XEN) X18: ffff800031cb3c58 X19: 00000a000038a5d0 X20: 000000000000005a Sep 10 07:54:34.151410 (XEN) X21: 00000a0000350180 X22: 0000000004000000 X23: 000000000000005a Sep 10 07:54:34.163516 (XEN) X24: 000000000000005a X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:34.163585 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd917e60 Sep 10 07:54:34.175419 (XEN) Sep 10 07:54:34.175419 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:34.175419 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:34.187410 (XEN) Sep 10 07:54:34.187410 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:34.187410 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:34.187410 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:34.187410 (XEN) Sep 10 07:54:34.187410 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:34.199415 (XEN) HPFAR_EL2: 0000009010801700 Sep 10 07:54:34.199415 (XEN) FAR_EL2: ffff80000b170100 Sep 10 07:54:34.199415 (XEN) Sep 10 07:54:34.199415 (XEN) Xen stack trace from sp=0000800ffd917e60: Sep 10 07:54:34.211414 (XEN) 0000800ffd917e70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:34.211414 (XEN) 000000000000005a 0000000000000000 0000000000000000 000000000001020a Sep 10 07:54:34.223412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.223412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.235414 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.235414 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.247417 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.259416 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.259416 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.271415 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.271415 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.283413 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.283413 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.295414 (XEN) Xen call trace: Sep 10 07:54:34.295414 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:34.307420 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:34.307420 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:34.319415 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:34.319415 (XEN) Sep 10 07:54:34.319415 (XEN) *** Dumping CPU91 host state: *** Sep 10 07:54:34.319415 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:34.331408 (XEN) CPU: 91 Sep 10 07:54:34.331408 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:34.331408 (XEN) LR: 00000a0000278470 Sep 10 07:54:34.343414 (XEN) SP: 0000800ffd90fe60 Sep 10 07:54:34.343414 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:34.343414 (XEN) X0: 0000000000000000 X1: 0000760ffd638000 X2: 0000800ffd980078 Sep 10 07:54:34.355411 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:34.367410 (XEN) X6: 00000a000038a5c8 X7: 0000800ffd9868d0 X8: 0000000000000012 Sep 10 07:54:34.367410 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Sep 10 07:54:34.379344 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Sep 10 07:54:34.379344 (XEN) X15: ffff00003170690c X16: 0000000000000001 X17: 0000000000000000 Sep 10 07:54:34.391407 (XEN) X18: ffff80000dac3c58 X19: 00000a000038a5d0 X20: 000000000000005b Sep 10 07:54:34.391407 (XEN) X21: 00000a0000350200 X22: 0000000008000000 X23: 000000000000005b Sep 10 07:54:34.403409 (XEN) X24: 000000000000005b X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:34.403409 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd90fe60 Sep 10 07:54:34.415412 (XEN) Sep 10 07:54:34.415412 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:34.415412 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:34.427409 (XEN) Sep 10 07:54:34.427409 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:34.427409 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:34.427409 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:34.427409 (XEN) Sep 10 07:54:34.427409 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:34.439411 (XEN) HPFAR_EL2: 0000009010802300 Sep 10 07:54:34.439411 (XEN) FAR_EL2: ffff80000b230100 Sep 10 07:54:34.439411 (XEN) Sep 10 07:54:34.439411 (XEN) Xen stack trace from sp=0000800ffd90fe60: Sep 10 07:54:34.451408 (XEN) 0000800ffd90fe70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:34.451408 (XEN) 000000000000005b 0000000000000000 0000000000000000 000000000001020b Sep 10 07:54:34.463411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.463411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.475408 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.475408 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.487407 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.499412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.499412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.511408 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.511408 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.523516 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.523584 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.535411 (XEN) Xen call trace: Sep 10 07:54:34.535411 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:34.547412 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:34.547412 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:34.559401 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:34.559401 (XEN) Sep 10 07:54:34.559401 (XEN) *** Dumping CPU92 host state: *** Sep 10 07:54:34.559401 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:34.571406 (XEN) CPU: 92 Sep 10 07:54:34.571406 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:34.583412 (XEN) LR: 00000a0000278470 Sep 10 07:54:34.583412 (XEN) SP: 0000800ffd89fe60 Sep 10 07:54:34.583412 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:34.595414 (XEN) X0: 0000000000000000 X1: 0000760ffd5be000 X2: 0000800ffd906078 Sep 10 07:54:34.595414 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:34.607412 (XEN) X6: 00000a000038a5c8 X7: 0000800ffd986d90 X8: 0000000000000012 Sep 10 07:54:34.607412 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Sep 10 07:54:34.619414 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Sep 10 07:54:34.619414 (XEN) X15: ffff0000217f3b0c X16: ffff8000092a0fb8 X17: 0000000000000000 Sep 10 07:54:34.631407 (XEN) X18: ffff800031683c58 X19: 00000a000038a5d0 X20: 000000000000005c Sep 10 07:54:34.631407 (XEN) X21: 00000a0000350280 X22: 0000000010000000 X23: 000000000000005c Sep 10 07:54:34.643412 (XEN) X24: 000000000000005c X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:34.655410 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd89fe60 Sep 10 07:54:34.655410 (XEN) Sep 10 07:54:34.655410 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:34.655410 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:34.667407 (XEN) Sep 10 07:54:34.667407 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:34.667407 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:34.667407 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:34.667407 (XEN) Sep 10 07:54:34.679418 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:34.679418 (XEN) HPFAR_EL2: 0000009010802f00 Sep 10 07:54:34.679418 (XEN) FAR_EL2: ffff80000b2f0100 Sep 10 07:54:34.679418 (XEN) Sep 10 07:54:34.679418 (XEN) Xen stack trace from sp=0000800ffd89fe60: Sep 10 07:54:34.691409 (XEN) 0000800ffd89fe70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:34.691409 (XEN) 000000000000005c 0000000000000000 0000000000000000 000000000001020c Sep 10 07:54:34.703412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.703412 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.715410 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.727411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.727411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.739430 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.739430 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.751409 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.751409 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.763411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.775406 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.775406 (XEN) Xen call trace: Sep 10 07:54:34.775406 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:34.787412 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:34.787412 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:34.799421 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:34.799421 (XEN) Sep 10 07:54:34.799421 (XEN) *** Dumping CPU93 host state: *** Sep 10 07:54:34.799421 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:34.811410 (XEN) CPU: 93 Sep 10 07:54:34.811410 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:34.823408 (XEN) LR: 00000a0000278470 Sep 10 07:54:34.823408 (XEN) SP: 0000800ffd897e60 Sep 10 07:54:34.823408 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:34.835328 (XEN) X0: 0000000000000000 X1: 0000760ffd5ba000 X2: 0000800ffd902078 Sep 10 07:54:34.835328 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:34.847451 (XEN) X6: 00000a000038a5c8 X7: 0000800ffd904280 X8: 0000000000000012 Sep 10 07:54:34.847451 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Sep 10 07:54:34.859370 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Sep 10 07:54:34.859370 (XEN) X15: fffffc000088ed40 X16: 0000000000000001 X17: 0000000000000000 Sep 10 07:54:34.871391 (XEN) X18: ffff800020d83c58 X19: 00000a000038a5d0 X20: 000000000000005d Sep 10 07:54:34.871391 (XEN) X21: 00000a0000350300 X22: 0000000020000000 X23: 000000000000005d Sep 10 07:54:34.883380 (XEN) X24: 000000000000005d X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:34.895408 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd897e60 Sep 10 07:54:34.895408 (XEN) Sep 10 07:54:34.895408 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:34.895408 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:34.907410 (XEN) Sep 10 07:54:34.907410 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:34.907410 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:34.907410 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:34.919425 (XEN) Sep 10 07:54:34.919425 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:34.919425 (XEN) HPFAR_EL2: 0000009010803b00 Sep 10 07:54:34.919425 (XEN) FAR_EL2: ffff80000b3b0100 Sep 10 07:54:34.919425 (XEN) Sep 10 07:54:34.919425 (XEN) Xen stack trace from sp=0000800ffd897e60: Sep 10 07:54:34.931387 (XEN) 0000800ffd897e70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:34.931387 (XEN) 000000000000005d 0000000000000000 0000000000000000 000000000001020d Sep 10 07:54:34.943411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.955411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.955411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.967406 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.967406 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.979429 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.979429 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.991399 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:34.991399 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.003409 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.015409 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.015409 (XEN) Xen call trace: Sep 10 07:54:35.015409 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:35.027409 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:35.027409 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:35.039372 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:35.039372 (XEN) Sep 10 07:54:35.039372 (XEN) *** Dumping CPU94 host state: *** Sep 10 07:54:35.051413 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:35.051413 (XEN) CPU: 94 Sep 10 07:54:35.051413 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:35.063412 (XEN) LR: 00000a0000278470 Sep 10 07:54:35.063412 (XEN) SP: 0000800ffd887e60 Sep 10 07:54:35.063412 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:35.075412 (XEN) X0: 0000000000000000 X1: 0000760ffd546000 X2: 0000800ffd88e078 Sep 10 07:54:35.075412 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:35.087424 (XEN) X6: 00000a000038a5c8 X7: 0000800ffd904740 X8: 0000000000000012 Sep 10 07:54:35.087424 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Sep 10 07:54:35.099644 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Sep 10 07:54:35.099712 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Sep 10 07:54:35.111489 (XEN) X18: 0000000000000000 X19: 00000a000038a5d0 X20: 000000000000005e Sep 10 07:54:35.123595 (XEN) X21: 00000a0000350380 X22: 0000000040000000 X23: 000000000000005e Sep 10 07:54:35.123660 (XEN) X24: 000000000000005e X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:35.135485 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd887e60 Sep 10 07:54:35.135550 (XEN) Sep 10 07:54:35.135591 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:35.147595 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:35.147654 (XEN) Sep 10 07:54:35.147695 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:35.147739 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:35.147801 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:35.159510 (XEN) Sep 10 07:54:35.159565 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:35.159610 (XEN) HPFAR_EL2: 0000009010804700 Sep 10 07:54:35.159654 (XEN) FAR_EL2: ffff80000b470100 Sep 10 07:54:35.159698 (XEN) Sep 10 07:54:35.171604 (XEN) Xen stack trace from sp=0000800ffd887e60: Sep 10 07:54:35.171668 (XEN) 0000800ffd887e70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:35.171719 (XEN) 000000000000005e 0000000000000000 0000000000000000 000000000001020e Sep 10 07:54:35.183513 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.195597 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.195660 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.207504 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.207569 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.219602 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.219665 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.231602 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.243487 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.243551 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.255586 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.255651 (XEN) Xen call trace: Sep 10 07:54:35.255695 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:35.267498 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:35.267564 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:35.279629 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:35.279688 (XEN) Sep 10 07:54:35.279729 (XEN) *** Dumping CPU95 host state: *** Sep 10 07:54:35.291484 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 10 07:54:35.291549 (XEN) CPU: 95 Sep 10 07:54:35.291592 (XEN) PC: 00000a000027848c arch/arm/domain.c#idle_loop+0x12c/0x19c Sep 10 07:54:35.303597 (XEN) LR: 00000a0000278470 Sep 10 07:54:35.303656 (XEN) SP: 0000800ffd81fe60 Sep 10 07:54:35.303702 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 10 07:54:35.315495 (XEN) X0: 0000000000000000 X1: 0000760ffd544000 X2: 0000800ffd88c078 Sep 10 07:54:35.315560 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000038a5c0 Sep 10 07:54:35.327593 (XEN) X6: 00000a000038a5c8 X7: 0000800ffd904c00 X8: 0000000000000012 Sep 10 07:54:35.327658 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Sep 10 07:54:35.339491 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Sep 10 07:54:35.351585 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Sep 10 07:54:35.351650 (XEN) X18: 0000000000000000 X19: 00000a000038a5d0 X20: 000000000000005f Sep 10 07:54:35.363485 (XEN) X21: 00000a0000350400 X22: 0000000080000000 X23: 000000000000005f Sep 10 07:54:35.363550 (XEN) X24: 000000000000005f X25: 0000000000000000 X26: 0000000000000000 Sep 10 07:54:35.375595 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd81fe60 Sep 10 07:54:35.375661 (XEN) Sep 10 07:54:35.375702 (XEN) VTCR_EL2: 00000000800d3590 Sep 10 07:54:35.387497 (XEN) VTTBR_EL2: 00010107fd80e000 Sep 10 07:54:35.387557 (XEN) Sep 10 07:54:35.387599 (XEN) SCTLR_EL2: 0000000030cd183d Sep 10 07:54:35.387644 (XEN) HCR_EL2: 00000000807c663f Sep 10 07:54:35.387687 (XEN) TTBR0_EL2: 000001071e927000 Sep 10 07:54:35.399583 (XEN) Sep 10 07:54:35.399638 (XEN) ESR_EL2: 0000000007e00000 Sep 10 07:54:35.399683 (XEN) HPFAR_EL2: 0000009010805100 Sep 10 07:54:35.399745 (XEN) FAR_EL2: ffff80000b510100 Sep 10 07:54:35.411491 (XEN) Sep 10 07:54:35.411546 (XEN) Xen stack trace from sp=0000800ffd81fe60: Sep 10 07:54:35.411594 (XEN) 0000800ffd81fe70 00000a000028444c 00000a0000349420 00000a00003805a8 Sep 10 07:54:35.423611 (XEN) 000000000000005f 0000000000000000 0000000000000000 000000000001020f Sep 10 07:54:35.423687 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.435486 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.435550 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.447593 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.447657 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.459478 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.459542 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.471595 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.483491 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.483554 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.495609 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 10 07:54:35.495673 (XEN) Xen call trace: Sep 10 07:54:35.495717 (XEN) [<00000a000027848c>] arch/arm/domain.c#idle_loop+0x12c/0x19c (PC) Sep 10 07:54:35.507499 (XEN) [<00000a0000278470>] arch/arm/domain.c#idle_loop+0x110/0x19c (LR) Sep 10 07:54:35.519571 (XEN) [<00000a000028444c>] start_secondary+0x218/0x21c Sep 10 07:54:35.519635 (XEN) [<00000a00003805a8>] 00000a00003805a8 Sep 10 07:54:35.519682 (XEN) Sep 10 07:54:35.519722 Sep 10 07:54:41.125263 (XEN) 'q' pressed -> dumping domain info (now = 1593678808700) Sep 10 07:54:41.147514 (XEN) General information for domain 0: Sep 10 07:54:41.147514 (XEN) refcnt=3 dying=0 pa Sep 10 07:54:41.149811 use_count=0 Sep 10 07:54:41.159320 (XEN) nr_pages=131072 xenheap_pages=2 dirty_cpus={} max_pages=131072 Sep 10 07:54:41.159320 (XEN) handle=00000000-0000-0000-0000-000000000000 vm_assist=00000020 Sep 10 07:54:41.169765 (XEN) p2m mappings for domain 0 (vmid 1): Sep 10 07:54:41.169831 (XEN) 1G mappings: 4984 (shattered 3) Sep 10 07:54:41.169878 (XEN) 2M mappings: 1444443 (shattered 107) Sep 10 07:54:41.183390 (XEN) 4K mappings: 54800 Sep 10 07:54:41.183390 (XEN) Rangesets belonging to domain 0: Sep 10 07:54:41.183390 (XEN) Interrupts { 32, 38, 48-51 } Sep 10 07:54:41.197680 (XEN) I/O Memory { 802000000-808000000, 810000000-820000000, 838000000-844000000, 846000000-848002000, 849000000-849002000, 84a000000-84a002000, 84b000000-84b002000, 868000000-880000000, 88001f000-880058000, 881010000-883000010, 902000000-908000000, 910000000-920000000, 938000000-944000000, 946000000-948002000, 949000000-949002000, 94a000000-94a002000, 94b000000-94b002000, 968000000-980000000 } Sep 10 07:54:41.223412 (XEN) NODE affinity for domain 0: [0] Sep 10 07:54:41.223412 (XEN) VCPU information and callbacks for domain 0: Sep 10 07:54:41.235412 (XEN) UNIT0 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.235412 (XEN) VCPU0: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.247410 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.247410 (XEN) GICH_LRs (vcpu 0) mask=0 Sep 10 07:54:41.247410 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.247410 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.247410 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.259410 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.259410 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.259410 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.259410 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.259410 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.259410 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.271405 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.271405 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.271405 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.271405 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.271405 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.283410 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.283410 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.283410 (XEN) No periodic timer Sep 10 07:54:41.283410 (XEN) UNIT1 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.283410 (XEN) VCPU1: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.295410 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.295410 (XEN) GICH_LRs (vcpu 1) mask=0 Sep 10 07:54:41.295410 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.307404 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.307404 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.307404 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.307404 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.307404 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.319404 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.319404 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.319404 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.319404 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.319404 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.319404 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.331404 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.331404 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.331404 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.331404 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.331404 (XEN) No periodic timer Sep 10 07:54:41.331404 (XEN) UNIT2 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.343409 (XEN) VCPU2: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.343409 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.355415 (XEN) GICH_LRs (vcpu 2) mask=0 Sep 10 07:54:41.355415 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.355415 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.355415 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.355415 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.367408 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.367408 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.367408 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.367408 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.367408 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.367408 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.379408 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.379408 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.379408 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.379408 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.379408 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.379408 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.391411 (XEN) No periodic timer Sep 10 07:54:41.391411 (XEN) UNIT3 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.391411 (XEN) VCPU3: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.403409 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.403409 (XEN) GICH_LRs (vcpu 3) mask=0 Sep 10 07:54:41.403409 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.403409 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.403409 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.415406 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.415406 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.415406 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.415406 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.415406 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.415406 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.427546 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.427607 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.427650 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.427691 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.427732 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.427774 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.439485 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.439542 (XEN) No periodic timer Sep 10 07:54:41.439587 (XEN) UNIT4 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.451555 (XEN) VCPU4: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.451621 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.451666 (XEN) GICH_LRs (vcpu 4) mask=0 Sep 10 07:54:41.463588 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.463645 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.463688 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.463730 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.463792 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.463836 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.475588 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.475645 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.475688 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.475730 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.475770 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.475811 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.487492 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.487550 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.487593 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.487635 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.487676 (XEN) No periodic timer Sep 10 07:54:41.487718 (XEN) UNIT5 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.499596 (XEN) VCPU5: CPU67 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.499661 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.511501 (XEN) GICH_LRs (vcpu 5) mask=0 Sep 10 07:54:41.511561 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.511605 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.511646 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.511687 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.511728 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.523590 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.523646 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.523689 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.523731 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.523772 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.523812 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.535492 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.535549 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.535592 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.535633 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.535674 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.547726 (XEN) No periodic timer Sep 10 07:54:41.547781 (XEN) UNIT6 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.547828 (XEN) VCPU6: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.559420 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.559479 (XEN) GICH_LRs (vcpu 6) mask=0 Sep 10 07:54:41.559526 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.559568 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.559614 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.571456 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.571556 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.571556 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.571634 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.571660 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.583527 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.583607 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.583633 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.583633 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.583633 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.583633 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.595537 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.595537 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.595644 (XEN) No periodic timer Sep 10 07:54:41.595644 (XEN) UNIT7 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.595644 (XEN) VCPU7: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.607523 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.607586 (XEN) GICH_LRs (vcpu 7) mask=0 Sep 10 07:54:41.619623 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.619686 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.619730 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.619771 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.619811 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.619851 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.631491 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.631550 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.631593 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.631635 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.631676 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.631718 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.643502 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.643561 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.643605 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.643647 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.643688 (XEN) No periodic timer Sep 10 07:54:41.643730 (XEN) UNIT8 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.655522 (XEN) VCPU8: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.655587 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.667494 (XEN) GICH_LRs (vcpu 8) mask=0 Sep 10 07:54:41.667572 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.667618 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.667660 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.667701 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.667741 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.679509 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.679567 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.679610 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.679652 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.679693 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.679734 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.691500 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.691558 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.691601 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.691643 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.691684 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.701116 (XEN) No periodic timer Sep 10 07:54:41.701172 (XEN) UNIT9 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.701221 (XEN) VCPU9: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.715519 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.715579 (XEN) GICH_LRs (vcpu 9) mask=0 Sep 10 07:54:41.715625 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.715666 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.727506 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.727564 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.727608 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.727650 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.727692 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.727733 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.739519 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.739578 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.739621 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.739664 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.739705 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.739746 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.751510 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.751568 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.751612 (XEN) No periodic timer Sep 10 07:54:41.751655 (XEN) UNIT10 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.751702 (XEN) VCPU10: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.763542 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.763542 (XEN) GICH_LRs (vcpu 10) mask=0 Sep 10 07:54:41.763630 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.775525 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.775585 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.775614 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.775614 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.775614 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.775614 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.787623 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.787684 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.787727 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.787768 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.787809 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.799508 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.799567 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.799610 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.799653 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.799694 (XEN) No periodic timer Sep 10 07:54:41.799735 (XEN) UNIT11 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.811533 (XEN) VCPU11: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.811615 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.823500 (XEN) GICH_LRs (vcpu 11) mask=0 Sep 10 07:54:41.823579 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.823593 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.823593 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.823593 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.835513 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.835513 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.835607 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.835683 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.835706 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.835706 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.847537 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.847600 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.847647 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.847677 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.847677 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.847677 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.859521 (XEN) No periodic timer Sep 10 07:54:41.859521 (XEN) UNIT12 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.859622 (XEN) VCPU12: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.871506 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.871581 (XEN) GICH_LRs (vcpu 12) mask=0 Sep 10 07:54:41.871597 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.871597 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.883509 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.883509 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.883592 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.883668 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.883698 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.883698 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.895514 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.895514 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.895627 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.895669 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.895669 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.895669 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.907512 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.907512 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.907603 (XEN) No periodic timer Sep 10 07:54:41.907673 (XEN) UNIT13 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.907701 (XEN) VCPU13: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.919515 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.919592 (XEN) GICH_LRs (vcpu 13) mask=0 Sep 10 07:54:41.931513 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.931513 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.931606 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.931669 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.931715 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.931748 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.943503 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.943560 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.943595 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.943595 (XEN) VCPU_LR[9]=0 Sep 10 07:54:41.943595 (XEN) VCPU_LR[10]=0 Sep 10 07:54:41.943595 (XEN) VCPU_LR[11]=0 Sep 10 07:54:41.955512 (XEN) VCPU_LR[12]=0 Sep 10 07:54:41.955512 (XEN) VCPU_LR[13]=0 Sep 10 07:54:41.955612 (XEN) VCPU_LR[14]=0 Sep 10 07:54:41.955682 (XEN) VCPU_LR[15]=0 Sep 10 07:54:41.955706 (XEN) No periodic timer Sep 10 07:54:41.967507 (XEN) UNIT14 affinities: hard={0-95} soft={0-95} Sep 10 07:54:41.967597 (XEN) VCPU14: CPU36 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:41.967617 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:41.979515 (XEN) GICH_LRs (vcpu 14) mask=0 Sep 10 07:54:41.979596 (XEN) VCPU_LR[0]=0 Sep 10 07:54:41.979596 (XEN) VCPU_LR[1]=0 Sep 10 07:54:41.979688 (XEN) VCPU_LR[2]=0 Sep 10 07:54:41.979708 (XEN) VCPU_LR[3]=0 Sep 10 07:54:41.991506 (XEN) VCPU_LR[4]=0 Sep 10 07:54:41.991571 (XEN) VCPU_LR[5]=0 Sep 10 07:54:41.991625 (XEN) VCPU_LR[6]=0 Sep 10 07:54:41.991658 (XEN) VCPU_LR[7]=0 Sep 10 07:54:41.991658 (XEN) VCPU_LR[8]=0 Sep 10 07:54:41.991658 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.003516 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.003516 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.003611 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.003687 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.003700 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.003700 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.015519 (XEN) No periodic timer Sep 10 07:54:42.015582 (XEN) UNIT15 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.015638 (XEN) VCPU15: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.027513 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.027513 (XEN) GICH_LRs (vcpu 15) mask=0 Sep 10 07:54:42.027616 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.027683 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.039422 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.039574 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.039617 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.039617 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.039617 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.039617 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.051513 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.051513 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.051597 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.051671 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.051705 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.051705 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.063506 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.063605 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.063616 (XEN) No periodic timer Sep 10 07:54:42.063616 (XEN) UNIT16 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.075508 (XEN) VCPU16: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.075587 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.075587 (XEN) GICH_LRs (vcpu 16) mask=0 Sep 10 07:54:42.087524 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.087588 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.087625 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.087625 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.087625 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.099516 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.099516 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.099609 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.099672 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.099717 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.099752 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.111426 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.111584 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.111619 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.111619 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.111619 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.111619 (XEN) No periodic timer Sep 10 07:54:42.123516 (XEN) UNIT17 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.123516 (XEN) VCPU17: CPU89 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.123618 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.135492 (XEN) GICH_LRs (vcpu 17) mask=0 Sep 10 07:54:42.135580 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.135595 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.135595 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.135595 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.147513 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.147513 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.147596 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.147672 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.147703 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.147703 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.159491 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.159555 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.159621 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.159637 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.159637 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.171515 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.171515 (XEN) No periodic timer Sep 10 07:54:42.171612 (XEN) UNIT18 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.171684 (XEN) VCPU18: CPU6 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.183503 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.183566 (XEN) GICH_LRs (vcpu 18) mask=0 Sep 10 07:54:42.183624 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.183640 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.195513 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.195513 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.195618 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.195673 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.195703 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.195703 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.207514 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.207570 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.207601 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.207601 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.207601 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.219512 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.219597 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.219597 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.219684 (XEN) No periodic timer Sep 10 07:54:42.219700 (XEN) UNIT19 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.231492 (XEN) VCPU19: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.231589 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.231596 (XEN) GICH_LRs (vcpu 19) mask=0 Sep 10 07:54:42.243516 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.243516 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.243598 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.243663 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.243723 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.255505 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.255578 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.255597 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.255597 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.255597 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.255597 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.267508 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.267508 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.267604 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.267669 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.267699 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.267699 (XEN) No periodic timer Sep 10 07:54:42.279500 (XEN) UNIT20 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.279601 (XEN) VCPU20: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.291508 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.291508 (XEN) GICH_LRs (vcpu 20) mask=0 Sep 10 07:54:42.291597 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.291677 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.291696 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.303499 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.303570 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.303601 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.303601 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.303601 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.303601 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.315514 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.315599 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.315599 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.315684 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.315703 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.315703 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.327476 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.327542 (XEN) No periodic timer Sep 10 07:54:42.327616 (XEN) UNIT21 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.327623 (XEN) VCPU21: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.339513 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.339594 (XEN) GICH_LRs (vcpu 21) mask=0 Sep 10 07:54:42.339594 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.351489 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.351566 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.351621 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.351640 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.351640 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.351640 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.363512 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.363512 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.363615 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.363672 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.363702 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.363702 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.375508 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.375508 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.375591 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.375662 (XEN) No periodic timer Sep 10 07:54:42.375671 (XEN) UNIT22 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.387514 (XEN) VCPU22: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.387514 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.399508 (XEN) GICH_LRs (vcpu 22) mask=0 Sep 10 07:54:42.399581 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.399596 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.399596 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.399596 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.399596 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.411510 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.411510 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.411607 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.411670 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.411700 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.411700 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.423489 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.423552 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.423600 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.423658 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.423674 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.423674 (XEN) No periodic timer Sep 10 07:54:42.435508 (XEN) UNIT23 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.435594 (XEN) VCPU23: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.447506 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.447579 (XEN) GICH_LRs (vcpu 23) mask=0 Sep 10 07:54:42.447598 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.447598 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.447598 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.459500 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.459500 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.459591 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.459693 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.459693 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.471483 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.471558 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.471619 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.471635 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.471635 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.471635 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.483513 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.483513 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.483603 (XEN) No periodic timer Sep 10 07:54:42.483665 (XEN) UNIT24 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.483733 (XEN) VCPU24: CPU7 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.495512 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.495589 (XEN) GICH_LRs (vcpu 24) mask=0 Sep 10 07:54:42.495605 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.507512 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.507512 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.507591 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.507591 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.507591 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.507668 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.519449 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.519553 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.519635 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.519635 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.519635 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.531492 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.531568 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.531591 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.531591 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.531591 (XEN) No periodic timer Sep 10 07:54:42.531591 (XEN) UNIT25 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.543513 (XEN) VCPU25: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.543599 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.555493 (XEN) GICH_LRs (vcpu 25) mask=0 Sep 10 07:54:42.555557 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.555620 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.555636 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.555636 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.555636 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.567509 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.567509 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.567609 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.567680 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.567700 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.567700 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.579497 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.579574 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.579589 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.579589 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.579589 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.591513 (XEN) No periodic timer Sep 10 07:54:42.591593 (XEN) UNIT26 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.591593 (XEN) VCPU26: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.603498 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.603577 (XEN) GICH_LRs (vcpu 26) mask=0 Sep 10 07:54:42.603629 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.603650 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.615522 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.615522 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.615621 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.615680 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.615710 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.615710 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.627501 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.627574 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.627595 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.627595 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.627595 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.627595 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.639588 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.639676 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.639676 (XEN) No periodic timer Sep 10 07:54:42.639750 (XEN) UNIT27 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.639807 (XEN) VCPU27: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.651501 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.651585 (XEN) GICH_LRs (vcpu 27) mask=0 Sep 10 07:54:42.663513 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.663592 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.663592 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.663662 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.663727 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.663742 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.675491 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.675556 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.675596 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.675635 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.675644 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.675644 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.687512 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.687512 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.687610 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.687671 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.687701 (XEN) No periodic timer Sep 10 07:54:42.687701 (XEN) UNIT28 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.699521 (XEN) VCPU28: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.699594 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.711506 (XEN) GICH_LRs (vcpu 28) mask=0 Sep 10 07:54:42.711506 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.711601 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.711669 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.711693 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.723494 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.723586 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.723602 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.723602 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.723602 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.723602 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.735512 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.735588 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.735588 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.735667 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.735725 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.747509 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.747571 (XEN) No periodic timer Sep 10 07:54:42.747594 (XEN) UNIT29 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.747594 (XEN) VCPU29: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.759501 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.759501 (XEN) GICH_LRs (vcpu 29) mask=0 Sep 10 07:54:42.759603 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.759669 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.771412 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.771412 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.771412 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.771412 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.771412 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.771412 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.783411 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.783411 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.783411 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.783411 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.783411 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.783411 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.795411 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.795411 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.795411 (XEN) No periodic timer Sep 10 07:54:42.795411 (XEN) UNIT30 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.807413 (XEN) VCPU30: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.807413 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.807413 (XEN) GICH_LRs (vcpu 30) mask=0 Sep 10 07:54:42.819413 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.819413 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.819413 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.819413 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.819413 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.819413 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.831408 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.831408 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.831408 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.831408 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.831408 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.831408 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.843385 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.843385 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.843385 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.843385 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.843385 (XEN) No periodic timer Sep 10 07:54:42.855408 (XEN) UNIT31 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.855408 (XEN) VCPU31: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.855408 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.867415 (XEN) GICH_LRs (vcpu 31) mask=0 Sep 10 07:54:42.867415 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.867415 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.867415 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.879412 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.879412 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.879412 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.879412 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.879412 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.879412 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.891410 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.891410 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.891410 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.891410 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.891410 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.891410 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.903411 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.903411 (XEN) No periodic timer Sep 10 07:54:42.903411 (XEN) UNIT32 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.903411 (XEN) VCPU32: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.915411 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.915411 (XEN) GICH_LRs (vcpu 32) mask=0 Sep 10 07:54:42.915411 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.915411 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.927411 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.927411 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.927411 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.927411 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.927411 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.927411 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.939410 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.939410 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.939410 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.939410 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.939410 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.939410 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.951407 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.951407 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.951407 (XEN) No periodic timer Sep 10 07:54:42.951407 (XEN) UNIT33 affinities: hard={0-95} soft={0-95} Sep 10 07:54:42.963399 (XEN) VCPU33: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:42.963399 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:42.975413 (XEN) GICH_LRs (vcpu 33) mask=0 Sep 10 07:54:42.975413 (XEN) VCPU_LR[0]=0 Sep 10 07:54:42.975413 (XEN) VCPU_LR[1]=0 Sep 10 07:54:42.975413 (XEN) VCPU_LR[2]=0 Sep 10 07:54:42.975413 (XEN) VCPU_LR[3]=0 Sep 10 07:54:42.975413 (XEN) VCPU_LR[4]=0 Sep 10 07:54:42.987410 (XEN) VCPU_LR[5]=0 Sep 10 07:54:42.987410 (XEN) VCPU_LR[6]=0 Sep 10 07:54:42.987410 (XEN) VCPU_LR[7]=0 Sep 10 07:54:42.987410 (XEN) VCPU_LR[8]=0 Sep 10 07:54:42.987410 (XEN) VCPU_LR[9]=0 Sep 10 07:54:42.987410 (XEN) VCPU_LR[10]=0 Sep 10 07:54:42.999409 (XEN) VCPU_LR[11]=0 Sep 10 07:54:42.999409 (XEN) VCPU_LR[12]=0 Sep 10 07:54:42.999409 (XEN) VCPU_LR[13]=0 Sep 10 07:54:42.999409 (XEN) VCPU_LR[14]=0 Sep 10 07:54:42.999409 (XEN) VCPU_LR[15]=0 Sep 10 07:54:42.999409 (XEN) No periodic timer Sep 10 07:54:43.011411 (XEN) UNIT34 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.011411 (XEN) VCPU34: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.023419 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.023419 (XEN) GICH_LRs (vcpu 34) mask=0 Sep 10 07:54:43.023419 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.023419 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.023419 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.035409 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.035409 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.035409 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.035409 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.035409 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.035409 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.047407 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.047407 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.047407 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.047407 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.047407 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.047407 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.059410 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.059410 (XEN) No periodic timer Sep 10 07:54:43.059410 (XEN) UNIT35 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.059410 (XEN) VCPU35: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.071418 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.071418 (XEN) GICH_LRs (vcpu 35) mask=0 Sep 10 07:54:43.071418 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.083407 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.083407 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.083407 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.083407 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.083407 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.083407 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.095394 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.095394 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.095394 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.095394 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.095394 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.095394 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.107412 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.107412 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.107412 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.107412 (XEN) No periodic timer Sep 10 07:54:43.107412 (XEN) UNIT36 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.119409 (XEN) VCPU36: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.119409 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.131403 (XEN) GICH_LRs (vcpu 36) mask=0 Sep 10 07:54:43.131403 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.131403 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.131403 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.131403 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.131403 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.143408 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.143408 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.143408 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.143408 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.143408 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.143408 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.155409 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.155409 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.155409 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.155409 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.155409 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.155409 (XEN) No periodic timer Sep 10 07:54:43.167407 (XEN) UNIT37 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.167407 (XEN) VCPU37: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.179410 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.179410 (XEN) GICH_LRs (vcpu 37) mask=0 Sep 10 07:54:43.179410 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.179410 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.179410 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.191405 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.191405 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.191405 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.191405 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.191405 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.191405 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.203401 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.203401 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.203401 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.203401 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.203401 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.203401 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.215397 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.215397 (XEN) No periodic timer Sep 10 07:54:43.215397 (XEN) UNIT38 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.215397 (XEN) VCPU38: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.227409 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.227409 (XEN) GICH_LRs (vcpu 38) mask=0 Sep 10 07:54:43.239405 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.239405 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.239405 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.239405 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.239405 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.239405 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.251411 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.251411 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.251411 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.251411 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.251411 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.251411 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.263408 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.263408 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.263408 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.263408 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.263408 (XEN) No periodic timer Sep 10 07:54:43.263408 (XEN) UNIT39 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.275413 (XEN) VCPU39: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.275413 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.287412 (XEN) GICH_LRs (vcpu 39) mask=0 Sep 10 07:54:43.287412 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.287412 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.287412 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.287412 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.287412 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.299412 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.299412 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.299412 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.299412 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.299412 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.299412 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.311410 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.311410 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.311410 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.311410 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.311410 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.323409 (XEN) No periodic timer Sep 10 07:54:43.323409 (XEN) UNIT40 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.323409 (XEN) VCPU40: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.335408 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.335408 (XEN) GICH_LRs (vcpu 40) mask=0 Sep 10 07:54:43.335408 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.335408 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.335408 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.347393 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.347393 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.347393 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.347393 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.347393 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.359406 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.359406 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.359406 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.359406 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.359406 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.359406 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.371408 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.371408 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.371408 (XEN) No periodic timer Sep 10 07:54:43.371408 (XEN) UNIT41 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.383410 (XEN) VCPU41: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.383410 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.383410 (XEN) GICH_LRs (vcpu 41) mask=0 Sep 10 07:54:43.395409 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.395409 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.395409 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.395409 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.395409 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.395409 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.407410 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.407410 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.407410 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.407410 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.407410 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.407410 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.419411 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.419411 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.419411 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.419411 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.419411 (XEN) No periodic timer Sep 10 07:54:43.419411 (XEN) UNIT42 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.431407 (XEN) VCPU42: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.431407 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.443411 (XEN) GICH_LRs (vcpu 42) mask=0 Sep 10 07:54:43.443411 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.443411 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.443411 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.443411 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.455410 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.455410 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.455410 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.455410 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.455410 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.455410 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.467406 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.467406 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.467406 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.467406 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.467406 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.467406 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.479407 (XEN) No periodic timer Sep 10 07:54:43.479407 (XEN) UNIT43 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.479407 (XEN) VCPU43: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.491407 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.491407 (XEN) GICH_LRs (vcpu 43) mask=0 Sep 10 07:54:43.491407 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.491407 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.503408 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.503408 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.503408 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.503408 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.503408 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.503408 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.515403 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.515403 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.515403 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.515403 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.515403 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.515403 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.527414 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.527414 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.527414 (XEN) No periodic timer Sep 10 07:54:43.527414 (XEN) UNIT44 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.539411 (XEN) VCPU44: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.539411 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.539411 (XEN) GICH_LRs (vcpu 44) mask=0 Sep 10 07:54:43.551409 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.551409 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.551409 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.551409 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.551409 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.551409 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.563411 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.563411 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.563411 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.563411 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.563411 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.563411 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.575412 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.575412 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.575412 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.575412 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.575412 (XEN) No periodic timer Sep 10 07:54:43.575412 (XEN) UNIT45 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.587408 (XEN) VCPU45: CPU73 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.587408 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.599401 (XEN) GICH_LRs (vcpu 45) mask=0 Sep 10 07:54:43.599401 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.599401 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.599401 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.611410 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.611410 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.611410 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.611410 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.611410 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.611410 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.623408 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.623408 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.623408 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.623408 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.623408 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.623408 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.635410 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.635410 (XEN) No periodic timer Sep 10 07:54:43.635410 (XEN) UNIT46 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.635410 (XEN) VCPU46: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.647410 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.647410 (XEN) GICH_LRs (vcpu 46) mask=0 Sep 10 07:54:43.647410 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.647410 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.659409 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.659409 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.659409 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.659409 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.659409 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.659409 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.671411 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.671411 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.671411 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.671411 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.671411 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.683412 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.683412 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.683412 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.683412 (XEN) No periodic timer Sep 10 07:54:43.683412 (XEN) UNIT47 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.695408 (XEN) VCPU47: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.695408 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.695408 (XEN) GICH_LRs (vcpu 47) mask=0 Sep 10 07:54:43.707408 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.707408 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.707408 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.707408 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.707408 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.707408 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.719409 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.719409 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.719409 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.719409 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.719409 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.719409 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.731398 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.731398 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.731398 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.731398 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.731398 (XEN) No periodic timer Sep 10 07:54:43.743413 (XEN) UNIT48 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.743413 (XEN) VCPU48: CPU9 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.755412 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.755412 (XEN) GICH_LRs (vcpu 48) mask=0 Sep 10 07:54:43.755412 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.755412 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.755412 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.767492 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.767506 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.767506 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.767506 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.767506 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.767506 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.779624 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.779686 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.779730 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.779771 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.779812 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.779854 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.791492 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.791550 (XEN) No periodic timer Sep 10 07:54:43.791595 (XEN) UNIT49 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.791643 (XEN) VCPU49: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.803597 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.803657 (XEN) GICH_LRs (vcpu 49) mask=0 Sep 10 07:54:43.803703 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.815502 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.815561 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.815605 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.815647 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.815688 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.815730 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.827583 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.827641 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.827684 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.827727 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.827768 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.827809 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.839486 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.839544 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.839588 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.839630 (XEN) No periodic timer Sep 10 07:54:43.839673 (XEN) UNIT50 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.851583 (XEN) VCPU50: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.851668 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.863502 (XEN) GICH_LRs (vcpu 50) mask=0 Sep 10 07:54:43.863563 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.863607 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.863649 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.863690 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.863731 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.875590 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.875647 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.875690 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.875732 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.875774 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.875815 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.887514 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.887572 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.887614 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.887656 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.887697 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.887738 (XEN) No periodic timer Sep 10 07:54:43.899597 (XEN) UNIT51 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.899659 (XEN) VCPU51: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.911503 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.911564 (XEN) GICH_LRs (vcpu 51) mask=0 Sep 10 07:54:43.911610 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.911652 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.911693 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.923595 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.923652 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.923696 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.923737 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.923778 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.923819 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.935508 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.935566 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.935609 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.935651 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.935693 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.935734 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.947597 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.947654 (XEN) No periodic timer Sep 10 07:54:43.947698 (XEN) UNIT52 affinities: hard={0-95} soft={0-95} Sep 10 07:54:43.947746 (XEN) VCPU52: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:43.980089 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:43.980165 (XEN) GICH_LRs (vcpu 52) mask=0 Sep 10 07:54:43.980214 (XEN) VCPU_LR[0]=0 Sep 10 07:54:43.980317 (XEN) VCPU_LR[1]=0 Sep 10 07:54:43.980360 (XEN) VCPU_LR[2]=0 Sep 10 07:54:43.980401 (XEN) VCPU_LR[3]=0 Sep 10 07:54:43.980443 (XEN) VCPU_LR[4]=0 Sep 10 07:54:43.980484 (XEN) VCPU_LR[5]=0 Sep 10 07:54:43.980524 (XEN) VCPU_LR[6]=0 Sep 10 07:54:43.983496 (XEN) VCPU_LR[7]=0 Sep 10 07:54:43.983554 (XEN) VCPU_LR[8]=0 Sep 10 07:54:43.983597 (XEN) VCPU_LR[9]=0 Sep 10 07:54:43.983639 (XEN) VCPU_LR[10]=0 Sep 10 07:54:43.983680 (XEN) VCPU_LR[11]=0 Sep 10 07:54:43.995415 (XEN) VCPU_LR[12]=0 Sep 10 07:54:43.995415 (XEN) VCPU_LR[13]=0 Sep 10 07:54:43.995415 (XEN) VCPU_LR[14]=0 Sep 10 07:54:43.995415 (XEN) VCPU_LR[15]=0 Sep 10 07:54:43.995415 (XEN) No periodic timer Sep 10 07:54:43.995415 (XEN) UNIT53 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.007534 (XEN) VCPU53: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.007603 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.019556 (XEN) GICH_LRs (vcpu 53) mask=0 Sep 10 07:54:44.019627 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.019627 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.019627 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.019627 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.019627 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.031509 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.031509 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.031609 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.031678 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.031699 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.031699 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.043512 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.043581 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.043603 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.043603 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.043603 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.055511 (XEN) No periodic timer Sep 10 07:54:44.055511 (XEN) UNIT54 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.055610 (XEN) VCPU54: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.067503 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.067573 (XEN) GICH_LRs (vcpu 54) mask=0 Sep 10 07:54:44.067591 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.067591 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.067591 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.079517 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.079517 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.079599 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.079663 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.079722 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.079746 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.091524 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.091595 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.091616 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.091616 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.091616 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.091616 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.103485 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.103485 (XEN) No periodic timer Sep 10 07:54:44.103581 (XEN) UNIT55 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.103581 (XEN) VCPU55: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.115408 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.115408 (XEN) GICH_LRs (vcpu 55) mask=0 Sep 10 07:54:44.127416 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.127416 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.127416 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.127416 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.127416 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.127416 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.139415 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.139415 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.139415 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.139415 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.139415 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.139415 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.151415 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.151415 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.151415 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.151415 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.151415 (XEN) No periodic timer Sep 10 07:54:44.151415 (XEN) UNIT56 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.163406 (XEN) VCPU56: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.163406 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.175413 (XEN) GICH_LRs (vcpu 56) mask=0 Sep 10 07:54:44.175413 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.175413 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.175413 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.175413 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.187413 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.187413 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.187413 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.187413 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.187413 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.187413 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.199409 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.199409 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.199409 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.199409 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.199409 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.199409 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.211419 (XEN) No periodic timer Sep 10 07:54:44.211419 (XEN) UNIT57 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.211419 (XEN) VCPU57: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.223419 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.223419 (XEN) GICH_LRs (vcpu 57) mask=0 Sep 10 07:54:44.223419 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.223419 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.223419 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.235408 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.235408 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.235408 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.235408 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.235408 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.247417 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.247417 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.247417 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.247417 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.247417 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.247417 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.259416 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.259416 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.259416 (XEN) No periodic timer Sep 10 07:54:44.259416 (XEN) UNIT58 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.271407 (XEN) VCPU58: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.271407 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.271407 (XEN) GICH_LRs (vcpu 58) mask=0 Sep 10 07:54:44.283408 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.283408 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.283408 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.283408 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.283408 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.283408 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.295410 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.295410 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.295410 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.295410 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.295410 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.295410 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.307409 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.307409 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.307409 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.307409 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.307409 (XEN) No periodic timer Sep 10 07:54:44.307409 (XEN) UNIT59 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.319412 (XEN) VCPU59: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.319412 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.331406 (XEN) GICH_LRs (vcpu 59) mask=0 Sep 10 07:54:44.331406 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.331406 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.331406 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.331406 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.343409 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.343409 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.343409 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.343409 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.343409 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.343409 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.355411 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.355411 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.355411 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.355411 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.355411 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.355411 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.367404 (XEN) No periodic timer Sep 10 07:54:44.367404 (XEN) UNIT60 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.367404 (XEN) VCPU60: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.379418 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.379418 (XEN) GICH_LRs (vcpu 60) mask=0 Sep 10 07:54:44.379418 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.391413 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.391413 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.391413 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.391413 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.391413 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.391413 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.403418 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.403418 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.403418 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.403418 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.403418 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.403418 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.415419 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.415419 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.415419 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.415419 (XEN) No periodic timer Sep 10 07:54:44.415419 (XEN) UNIT61 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.427418 (XEN) VCPU61: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.427418 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.427418 (XEN) GICH_LRs (vcpu 61) mask=0 Sep 10 07:54:44.439406 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.439406 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.439406 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.439406 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.439406 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.439406 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.451412 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.451412 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.451412 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.451412 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.451412 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.451412 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.463409 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.463409 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.463409 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.463409 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.463409 (XEN) No periodic timer Sep 10 07:54:44.475404 (XEN) UNIT62 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.475404 (XEN) VCPU62: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.475404 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.487393 (XEN) GICH_LRs (vcpu 62) mask=0 Sep 10 07:54:44.487393 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.487393 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.487393 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.499405 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.499405 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.499405 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.499405 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.499405 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.499405 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.511408 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.511408 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.511408 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.511408 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.511408 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.511408 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.523408 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.523408 (XEN) No periodic timer Sep 10 07:54:44.523408 (XEN) UNIT63 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.523408 (XEN) VCPU63: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.535412 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.535412 (XEN) GICH_LRs (vcpu 63) mask=0 Sep 10 07:54:44.535412 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.547414 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.547414 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.547414 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.547414 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.547414 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.547414 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.559410 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.559410 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.559410 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.559410 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.559410 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.559410 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.571408 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.571408 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.571408 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.571408 (XEN) No periodic timer Sep 10 07:54:44.571408 (XEN) UNIT64 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.583396 (XEN) VCPU64: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.583396 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.583396 (XEN) GICH_LRs (vcpu 64) mask=0 Sep 10 07:54:44.595382 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.595382 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.595382 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.595382 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.595382 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.595382 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.607407 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.607407 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.607407 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.607407 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.607407 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.619395 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.619395 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.619395 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.619395 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.619395 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.631408 (XEN) No periodic timer Sep 10 07:54:44.631408 (XEN) UNIT65 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.631408 (XEN) VCPU65: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.643411 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.643411 (XEN) GICH_LRs (vcpu 65) mask=0 Sep 10 07:54:44.643411 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.643411 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.643411 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.655411 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.655411 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.655411 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.655411 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.655411 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.655411 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.667415 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.667415 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.667415 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.667415 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.667415 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.667415 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.679412 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.679412 (XEN) No periodic timer Sep 10 07:54:44.679412 (XEN) UNIT66 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.679412 (XEN) VCPU66: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.691407 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.691407 (XEN) GICH_LRs (vcpu 66) mask=0 Sep 10 07:54:44.691407 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.703398 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.703398 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.703398 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.703398 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.703398 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.703398 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.715409 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.715409 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.715409 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.715409 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.715409 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.715409 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.727411 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.727411 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.727411 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.727411 (XEN) No periodic timer Sep 10 07:54:44.727411 (XEN) UNIT67 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.739403 (XEN) VCPU67: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.739403 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.751411 (XEN) GICH_LRs (vcpu 67) mask=0 Sep 10 07:54:44.751411 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.751411 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.751411 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.751411 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.763408 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.763408 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.763408 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.763408 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.763408 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.763408 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.775411 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.775411 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.775411 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.775411 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.775411 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.775411 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.787411 (XEN) No periodic timer Sep 10 07:54:44.787411 (XEN) UNIT68 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.787411 (XEN) VCPU68: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.799408 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.799408 (XEN) GICH_LRs (vcpu 68) mask=0 Sep 10 07:54:44.799408 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.799408 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.799408 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.811409 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.811409 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.811409 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.811409 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.811409 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.811409 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.823448 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.823448 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.823448 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.823448 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.823448 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.835407 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.835407 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.835407 (XEN) No periodic timer Sep 10 07:54:44.835407 (XEN) UNIT69 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.835407 (XEN) VCPU69: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.847412 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.847412 (XEN) GICH_LRs (vcpu 69) mask=0 Sep 10 07:54:44.847412 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.859413 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.859413 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.859413 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.859413 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.859413 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.859413 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.871377 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.871377 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.871377 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.871377 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.871377 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.883391 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.883391 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.883391 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.883391 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.883391 (XEN) No periodic timer Sep 10 07:54:44.883391 (XEN) UNIT70 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.895525 (XEN) VCPU70: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.895595 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.907422 (XEN) GICH_LRs (vcpu 70) mask=0 Sep 10 07:54:44.907422 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.907422 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.907422 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.907422 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.919416 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.919416 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.919416 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.919416 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.919416 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.919416 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.931416 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.931416 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.931416 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.931416 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.931416 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.931416 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.943423 (XEN) No periodic timer Sep 10 07:54:44.943423 (XEN) UNIT71 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.943423 (XEN) VCPU71: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:44.955418 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:44.955418 (XEN) GICH_LRs (vcpu 71) mask=0 Sep 10 07:54:44.955418 (XEN) VCPU_LR[0]=0 Sep 10 07:54:44.955418 (XEN) VCPU_LR[1]=0 Sep 10 07:54:44.967419 (XEN) VCPU_LR[2]=0 Sep 10 07:54:44.967419 (XEN) VCPU_LR[3]=0 Sep 10 07:54:44.967419 (XEN) VCPU_LR[4]=0 Sep 10 07:54:44.967419 (XEN) VCPU_LR[5]=0 Sep 10 07:54:44.967419 (XEN) VCPU_LR[6]=0 Sep 10 07:54:44.967419 (XEN) VCPU_LR[7]=0 Sep 10 07:54:44.979417 (XEN) VCPU_LR[8]=0 Sep 10 07:54:44.979417 (XEN) VCPU_LR[9]=0 Sep 10 07:54:44.979417 (XEN) VCPU_LR[10]=0 Sep 10 07:54:44.979417 (XEN) VCPU_LR[11]=0 Sep 10 07:54:44.979417 (XEN) VCPU_LR[12]=0 Sep 10 07:54:44.979417 (XEN) VCPU_LR[13]=0 Sep 10 07:54:44.991413 (XEN) VCPU_LR[14]=0 Sep 10 07:54:44.991413 (XEN) VCPU_LR[15]=0 Sep 10 07:54:44.991413 (XEN) No periodic timer Sep 10 07:54:44.991413 (XEN) UNIT72 affinities: hard={0-95} soft={0-95} Sep 10 07:54:44.991413 (XEN) VCPU72: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.003410 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.003410 (XEN) GICH_LRs (vcpu 72) mask=0 Sep 10 07:54:45.015410 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.015410 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.015410 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.015410 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.015410 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.015410 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.027414 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.027414 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.027414 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.027414 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.027414 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.027414 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.039411 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.039411 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.039411 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.039411 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.039411 (XEN) No periodic timer Sep 10 07:54:45.051411 (XEN) UNIT73 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.051411 (XEN) VCPU73: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.051411 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.063417 (XEN) GICH_LRs (vcpu 73) mask=0 Sep 10 07:54:45.063417 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.063417 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.063417 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.063417 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.075506 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.075567 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.075610 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.075651 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.075691 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.075731 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.087407 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.087407 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.087407 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.087407 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.087407 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.087407 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.099408 (XEN) No periodic timer Sep 10 07:54:45.099408 (XEN) UNIT74 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.099408 (XEN) VCPU74: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.111533 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.111549 (XEN) GICH_LRs (vcpu 74) mask=0 Sep 10 07:54:45.111549 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.111549 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.123621 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.123682 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.123726 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.123768 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.123809 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.135500 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.135558 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.135602 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.135644 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.135686 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.135727 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.147592 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.147649 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.147693 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.147734 (XEN) No periodic timer Sep 10 07:54:45.147777 (XEN) UNIT75 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.159506 (XEN) VCPU75: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.159572 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.159619 (XEN) GICH_LRs (vcpu 75) mask=0 Sep 10 07:54:45.171594 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.171651 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.171694 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.171735 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.171775 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.171816 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.183521 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.183579 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.183622 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.183663 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.183705 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.183747 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.195591 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.195648 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.195691 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.195732 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.195773 (XEN) No periodic timer Sep 10 07:54:45.207495 (XEN) UNIT76 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.207559 (XEN) VCPU76: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.207611 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.219594 (XEN) GICH_LRs (vcpu 76) mask=0 Sep 10 07:54:45.219653 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.219697 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.219737 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.219778 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.231485 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.231542 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.231586 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.231627 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.231668 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.231709 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.243603 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.243678 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.243724 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.243766 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.243807 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.243848 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.255484 (XEN) No periodic timer Sep 10 07:54:45.255542 (XEN) UNIT77 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.255591 (XEN) VCPU77: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.267600 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.267659 (XEN) GICH_LRs (vcpu 77) mask=0 Sep 10 07:54:45.267704 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.279492 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.279550 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.279594 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.279636 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.279678 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.279718 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.291591 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.291648 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.291691 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.291732 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.291774 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.291815 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.303492 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.303550 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.303593 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.303635 (XEN) No periodic timer Sep 10 07:54:45.303677 (XEN) UNIT78 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.315595 (XEN) VCPU78: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.315660 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.315707 (XEN) GICH_LRs (vcpu 78) mask=0 Sep 10 07:54:45.327492 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.327550 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.327593 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.327635 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.327676 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.339512 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.339570 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.339614 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.339655 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.339697 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.339738 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.351488 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.351546 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.351589 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.351631 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.351673 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.351714 (XEN) No periodic timer Sep 10 07:54:45.363613 (XEN) UNIT79 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.363675 (XEN) VCPU79: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.363727 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.375496 (XEN) GICH_LRs (vcpu 79) mask=0 Sep 10 07:54:45.375556 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.375599 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.375641 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.387597 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.387655 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.387698 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.387740 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.387780 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.387821 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.399502 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.399560 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.399603 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.399645 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.399687 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.399728 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.411594 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.411651 (XEN) No periodic timer Sep 10 07:54:45.411695 (XEN) UNIT80 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.411743 (XEN) VCPU80: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.423477 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.423510 (XEN) GICH_LRs (vcpu 80) mask=0 Sep 10 07:54:45.423535 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.435497 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.435554 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.435597 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.435639 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.435680 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.435739 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.447500 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.447558 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.447601 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.447642 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.447684 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.447726 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.459556 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.459604 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.459647 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.459688 (XEN) No periodic timer Sep 10 07:54:45.459730 (XEN) UNIT81 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.471484 (XEN) VCPU81: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.471551 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.471598 (XEN) GICH_LRs (vcpu 81) mask=0 Sep 10 07:54:45.483598 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.483655 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.483698 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.483741 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.483782 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.495497 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.495555 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.495599 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.495641 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.495682 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.495723 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.507582 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.507639 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.507682 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.507725 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.507766 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.519490 (XEN) No periodic timer Sep 10 07:54:45.519549 (XEN) UNIT82 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.519598 (XEN) VCPU82: CPU67 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.531592 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.531652 (XEN) GICH_LRs (vcpu 82) mask=0 Sep 10 07:54:45.531698 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.531740 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.543511 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.543572 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.543615 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.543657 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.543698 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.543739 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.555549 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.555609 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.555653 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.555695 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.555736 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.555776 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.567489 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.567547 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.567591 (XEN) No periodic timer Sep 10 07:54:45.567633 (XEN) UNIT83 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.567680 (XEN) VCPU83: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.579612 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.579671 (XEN) GICH_LRs (vcpu 83) mask=0 Sep 10 07:54:45.579716 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.591499 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.591556 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.591599 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.591641 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.591682 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.591723 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.603602 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.603659 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.603703 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.603744 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.603785 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.603827 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.615510 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.615567 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.615611 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.615652 (XEN) No periodic timer Sep 10 07:54:45.615694 (XEN) UNIT84 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.627598 (XEN) VCPU84: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.627663 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.639476 (XEN) GICH_LRs (vcpu 84) mask=0 Sep 10 07:54:45.639599 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.639631 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.639663 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.639708 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.651587 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.651643 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.651686 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.651728 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.651768 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.651808 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.663471 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.663528 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.663572 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.663613 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.663654 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.663695 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.675582 (XEN) No periodic timer Sep 10 07:54:45.675639 (XEN) UNIT85 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.675688 (XEN) VCPU85: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.687482 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.687542 (XEN) GICH_LRs (vcpu 85) mask=0 Sep 10 07:54:45.687588 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.687629 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.699586 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.699644 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.699687 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.699729 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.699769 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.699810 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.711488 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.711546 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.711590 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.711632 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.711674 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.711715 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.723524 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.723555 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.723579 (XEN) No periodic timer Sep 10 07:54:45.723602 (XEN) UNIT86 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.723628 (XEN) VCPU86: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.735495 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.735555 (XEN) GICH_LRs (vcpu 86) mask=0 Sep 10 07:54:45.747584 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.747643 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.747686 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.747727 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.747768 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.747808 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.759467 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.759527 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.759570 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.759611 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.759652 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.759693 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.771592 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.771649 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.771691 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.771732 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.771774 (XEN) No periodic timer Sep 10 07:54:45.783466 (XEN) UNIT87 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.783500 (XEN) VCPU87: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.783528 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.795596 (XEN) GICH_LRs (vcpu 87) mask=0 Sep 10 07:54:45.795655 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.795699 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.795740 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.795780 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.807485 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.807542 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.807585 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.807626 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.807667 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.807707 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.819590 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.819647 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.819690 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.819731 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.819773 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.819814 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.831491 (XEN) No periodic timer Sep 10 07:54:45.831549 (XEN) UNIT88 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.831598 (XEN) VCPU88: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.843602 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.843662 (XEN) GICH_LRs (vcpu 88) mask=0 Sep 10 07:54:45.843707 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.843750 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.855486 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.855545 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.855588 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.855630 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.855671 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.855712 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.867593 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.867651 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.867694 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.867736 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.867777 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.867818 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.879485 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.879543 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.879586 (XEN) No periodic timer Sep 10 07:54:45.879629 (XEN) UNIT89 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.891596 (XEN) VCPU89: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.891663 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.891709 (XEN) GICH_LRs (vcpu 89) mask=0 Sep 10 07:54:45.903486 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.903531 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.903574 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.903616 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.903657 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.915590 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.915648 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.915691 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.915732 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.915773 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.915813 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.927496 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.927553 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.927597 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.927639 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.927680 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.927721 (XEN) No periodic timer Sep 10 07:54:45.939608 (XEN) UNIT90 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.939671 (XEN) VCPU90: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.939723 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.951509 (XEN) GICH_LRs (vcpu 90) mask=0 Sep 10 07:54:45.951569 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.951612 (XEN) VCPU_LR[1]=0 Sep 10 07:54:45.951654 (XEN) VCPU_LR[2]=0 Sep 10 07:54:45.951695 (XEN) VCPU_LR[3]=0 Sep 10 07:54:45.963581 (XEN) VCPU_LR[4]=0 Sep 10 07:54:45.963637 (XEN) VCPU_LR[5]=0 Sep 10 07:54:45.963680 (XEN) VCPU_LR[6]=0 Sep 10 07:54:45.963721 (XEN) VCPU_LR[7]=0 Sep 10 07:54:45.963762 (XEN) VCPU_LR[8]=0 Sep 10 07:54:45.963802 (XEN) VCPU_LR[9]=0 Sep 10 07:54:45.975497 (XEN) VCPU_LR[10]=0 Sep 10 07:54:45.975554 (XEN) VCPU_LR[11]=0 Sep 10 07:54:45.975597 (XEN) VCPU_LR[12]=0 Sep 10 07:54:45.975638 (XEN) VCPU_LR[13]=0 Sep 10 07:54:45.975679 (XEN) VCPU_LR[14]=0 Sep 10 07:54:45.987590 (XEN) VCPU_LR[15]=0 Sep 10 07:54:45.987650 (XEN) No periodic timer Sep 10 07:54:45.987694 (XEN) UNIT91 affinities: hard={0-95} soft={0-95} Sep 10 07:54:45.987742 (XEN) VCPU91: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:45.999499 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:45.999558 (XEN) GICH_LRs (vcpu 91) mask=0 Sep 10 07:54:45.999603 (XEN) VCPU_LR[0]=0 Sep 10 07:54:45.999646 (XEN) VCPU_LR[1]=0 Sep 10 07:54:46.011583 (XEN) VCPU_LR[2]=0 Sep 10 07:54:46.011640 (XEN) VCPU_LR[3]=0 Sep 10 07:54:46.011683 (XEN) VCPU_LR[4]=0 Sep 10 07:54:46.011724 (XEN) VCPU_LR[5]=0 Sep 10 07:54:46.011765 (XEN) VCPU_LR[6]=0 Sep 10 07:54:46.023500 (XEN) VCPU_LR[7]=0 Sep 10 07:54:46.023545 (XEN) VCPU_LR[8]=0 Sep 10 07:54:46.023584 (XEN) VCPU_LR[9]=0 Sep 10 07:54:46.023625 (XEN) VCPU_LR[10]=0 Sep 10 07:54:46.023666 (XEN) VCPU_LR[11]=0 Sep 10 07:54:46.023707 (XEN) VCPU_LR[12]=0 Sep 10 07:54:46.035592 (XEN) VCPU_LR[13]=0 Sep 10 07:54:46.035650 (XEN) VCPU_LR[14]=0 Sep 10 07:54:46.035693 (XEN) VCPU_LR[15]=0 Sep 10 07:54:46.035752 (XEN) No periodic timer Sep 10 07:54:46.035796 (XEN) UNIT92 affinities: hard={0-95} soft={0-95} Sep 10 07:54:46.047497 (XEN) VCPU92: CPU34 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:46.047563 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:46.047609 (XEN) GICH_LRs (vcpu 92) mask=0 Sep 10 07:54:46.059598 (XEN) VCPU_LR[0]=0 Sep 10 07:54:46.059654 (XEN) VCPU_LR[1]=0 Sep 10 07:54:46.059697 (XEN) VCPU_LR[2]=0 Sep 10 07:54:46.059737 (XEN) VCPU_LR[3]=0 Sep 10 07:54:46.059778 (XEN) VCPU_LR[4]=0 Sep 10 07:54:46.071486 (XEN) VCPU_LR[5]=0 Sep 10 07:54:46.071544 (XEN) VCPU_LR[6]=0 Sep 10 07:54:46.071588 (XEN) VCPU_LR[7]=0 Sep 10 07:54:46.071630 (XEN) VCPU_LR[8]=0 Sep 10 07:54:46.071671 (XEN) VCPU_LR[9]=0 Sep 10 07:54:46.071712 (XEN) VCPU_LR[10]=0 Sep 10 07:54:46.083579 (XEN) VCPU_LR[11]=0 Sep 10 07:54:46.083643 (XEN) VCPU_LR[12]=0 Sep 10 07:54:46.083687 (XEN) VCPU_LR[13]=0 Sep 10 07:54:46.083728 (XEN) VCPU_LR[14]=0 Sep 10 07:54:46.083770 (XEN) VCPU_LR[15]=0 Sep 10 07:54:46.083810 (XEN) No periodic timer Sep 10 07:54:46.095514 (XEN) UNIT93 affinities: hard={0-95} soft={0-95} Sep 10 07:54:46.095578 (XEN) VCPU93: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:46.095630 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:46.107597 (XEN) GICH_LRs (vcpu 93) mask=0 Sep 10 07:54:46.107656 (XEN) VCPU_LR[0]=0 Sep 10 07:54:46.107699 (XEN) VCPU_LR[1]=0 Sep 10 07:54:46.107740 (XEN) VCPU_LR[2]=0 Sep 10 07:54:46.119502 (XEN) VCPU_LR[3]=0 Sep 10 07:54:46.119561 (XEN) VCPU_LR[4]=0 Sep 10 07:54:46.119604 (XEN) VCPU_LR[5]=0 Sep 10 07:54:46.119646 (XEN) VCPU_LR[6]=0 Sep 10 07:54:46.119687 (XEN) VCPU_LR[7]=0 Sep 10 07:54:46.119728 (XEN) VCPU_LR[8]=0 Sep 10 07:54:46.131592 (XEN) VCPU_LR[9]=0 Sep 10 07:54:46.131650 (XEN) VCPU_LR[10]=0 Sep 10 07:54:46.131694 (XEN) VCPU_LR[11]=0 Sep 10 07:54:46.131735 (XEN) VCPU_LR[12]=0 Sep 10 07:54:46.131776 (XEN) VCPU_LR[13]=0 Sep 10 07:54:46.131816 (XEN) VCPU_LR[14]=0 Sep 10 07:54:46.143491 (XEN) VCPU_LR[15]=0 Sep 10 07:54:46.143550 (XEN) No periodic timer Sep 10 07:54:46.143587 (XEN) UNIT94 affinities: hard={0-95} soft={0-95} Sep 10 07:54:46.143613 (XEN) VCPU94: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:46.155598 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:46.155657 (XEN) GICH_LRs (vcpu 94) mask=0 Sep 10 07:54:46.155702 (XEN) VCPU_LR[0]=0 Sep 10 07:54:46.167493 (XEN) VCPU_LR[1]=0 Sep 10 07:54:46.167549 (XEN) VCPU_LR[2]=0 Sep 10 07:54:46.167592 (XEN) VCPU_LR[3]=0 Sep 10 07:54:46.167633 (XEN) VCPU_LR[4]=0 Sep 10 07:54:46.167674 (XEN) VCPU_LR[5]=0 Sep 10 07:54:46.167715 (XEN) VCPU_LR[6]=0 Sep 10 07:54:46.179597 (XEN) VCPU_LR[7]=0 Sep 10 07:54:46.179654 (XEN) VCPU_LR[8]=0 Sep 10 07:54:46.179697 (XEN) VCPU_LR[9]=0 Sep 10 07:54:46.179738 (XEN) VCPU_LR[10]=0 Sep 10 07:54:46.179778 (XEN) VCPU_LR[11]=0 Sep 10 07:54:46.179819 (XEN) VCPU_LR[12]=0 Sep 10 07:54:46.191504 (XEN) VCPU_LR[13]=0 Sep 10 07:54:46.191560 (XEN) VCPU_LR[14]=0 Sep 10 07:54:46.191603 (XEN) VCPU_LR[15]=0 Sep 10 07:54:46.191645 (XEN) No periodic timer Sep 10 07:54:46.191687 (XEN) UNIT95 affinities: hard={0-95} soft={0-95} Sep 10 07:54:46.203599 (XEN) VCPU95: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 10 07:54:46.203635 (XEN) pause_count=0 pause_flags=1 Sep 10 07:54:46.215509 (XEN) GICH_LRs (vcpu 95) mask=0 Sep 10 07:54:46.215569 (XEN) VCPU_LR[0]=0 Sep 10 07:54:46.215613 (XEN) VCPU_LR[1]=0 Sep 10 07:54:46.215655 (XEN) VCPU_LR[2]=0 Sep 10 07:54:46.215695 (XEN) VCPU_LR[3]=0 Sep 10 07:54:46.215735 (XEN) VCPU_LR[4]=0 Sep 10 07:54:46.227589 (XEN) VCPU_LR[5]=0 Sep 10 07:54:46.227647 (XEN) VCPU_LR[6]=0 Sep 10 07:54:46.227690 (XEN) VCPU_LR[7]=0 Sep 10 07:54:46.227731 (XEN) VCPU_LR[8]=0 Sep 10 07:54:46.227772 (XEN) VCPU_LR[9]=0 Sep 10 07:54:46.227812 (XEN) VCPU_LR[10]=0 Sep 10 07:54:46.239506 (XEN) VCPU_LR[11]=0 Sep 10 07:54:46.239565 (XEN) VCPU_LR[12]=0 Sep 10 07:54:46.239608 (XEN) VCPU_LR[13]=0 Sep 10 07:54:46.239649 (XEN) VCPU_LR[14]=0 Sep 10 07:54:46.239690 (XEN) VCPU_LR[15]=0 Sep 10 07:54:46.239730 (XEN) No periodic timer Sep 10 07:54:46.251587 (XEN) Notifying guest 0:0 (virq 1, port 0) Sep 10 07:54:46.251647 (XEN) Notifying guest 0:1 (virq 1, port 0) Sep 10 07:54:46.251694 (XEN) Notifying guest 0:2 (virq 1, port 0) Sep 10 07:54:46.263501 (XEN) Notifying guest 0:3 (virq 1, port 0) Sep 10 07:54:46.263562 (XEN) Notifying guest 0:4 (virq 1, port 0) Sep 10 07:54:46.263613 (XEN) Notifying guest 0:5 (virq 1, port 0) Sep 10 07:54:46.275588 (XEN) Notifying guest 0:6 (virq 1, port 0) Sep 10 07:54:46.275649 (XEN) Notifying guest 0:7 (virq 1, port 0) Sep 10 07:54:46.275696 (XEN) Notifying guest 0:8 (virq 1, port 0) Sep 10 07:54:46.287492 (XEN) Notifying guest 0:9 (virq 1, port 0) Sep 10 07:54:46.287553 (XEN) Notifying guest 0:10 (virq 1, port 0) Sep 10 07:54:46.287599 (XEN) Notifying guest 0:11 (virq 1, port 0) Sep 10 07:54:46.299596 (XEN) Notifying guest 0:12 (virq 1, port 0) Sep 10 07:54:46.299657 (XEN) Notifying guest 0:13 (virq 1, port 0) Sep 10 07:54:46.299704 (XEN) Notifying guest 0:14 (virq 1, port 0) Sep 10 07:54:46.311510 (XEN) Notifying guest 0:15 (virq 1, port 0) Sep 10 07:54:46.311572 (XEN) Notifying guest 0:16 (virq 1, port 0) Sep 10 07:54:46.311619 (XEN) Notifying guest 0:17 (virq 1, port 0) Sep 10 07:54:46.323411 (XEN) Notifying guest 0:18 (virq 1, port 0) Sep 10 07:54:46.323411 (XEN) Notifying guest 0:19 (virq 1, port 0) Sep 10 07:54:46.323411 (XEN) Notifying guest 0:20 (virq 1, port 0) Sep 10 07:54:46.335410 (XEN) Notifying guest 0:21 (virq 1, port 0) Sep 10 07:54:46.335410 (XEN) Notifying guest 0:22 (virq 1, port 0) Sep 10 07:54:46.335410 (XEN) Notifying guest 0:23 (virq 1, port 0) Sep 10 07:54:46.347409 (XEN) Notifying guest 0:24 (virq 1, port 0) Sep 10 07:54:46.347409 (XEN) Notifying guest 0:25 (virq 1, port 0) Sep 10 07:54:46.347409 (XEN) Notifying guest 0:26 (virq 1, port 0) Sep 10 07:54:46.347409 (XEN) Notifying guest 0:27 (virq 1, port 0) Sep 10 07:54:46.359411 (XEN) Notifying guest 0:28 (virq 1, port 0) Sep 10 07:54:46.359411 (XEN) Notifying guest 0:29 (virq 1, port 0) Sep 10 07:54:46.359411 (XEN) Notifying guest 0:30 (virq 1, port 0) Sep 10 07:54:46.371416 (XEN) Notifying guest 0:31 (virq 1, port 0) Sep 10 07:54:46.371416 (XEN) Notifying guest 0:32 (virq 1, port 0) Sep 10 07:54:46.371416 (XEN) Notifying guest 0:33 (virq 1, port 0) Sep 10 07:54:46.383410 (XEN) Notifying guest 0:34 (virq 1, port 0) Sep 10 07:54:46.383410 (XEN) Notifying guest 0:35 (virq 1, port 0) Sep 10 07:54:46.383410 (XEN) Notifying guest 0:36 (virq 1, port 0) Sep 10 07:54:46.395397 (XEN) Notifying guest 0:37 (virq 1, port 0) Sep 10 07:54:46.395397 (XEN) Notifying guest 0:38 (virq 1, port 0) Sep 10 07:54:46.407409 (XEN) Notifying guest 0:39 (virq 1, port 0) Sep 10 07:54:46.407409 (XEN) Notifying guest 0:40 (virq 1, port 0) Sep 10 07:54:46.407409 (XEN) Notifying guest 0:41 (virq 1, port 0) Sep 10 07:54:46.419413 (XEN) Notifying guest 0:42 (virq 1, port 0) Sep 10 07:54:46.419413 (XEN) Notifying guest 0:43 (virq 1, port 0) Sep 10 07:54:46.419413 (XEN) Notifying guest 0:44 (virq 1, port 0) Sep 10 07:54:46.431412 (XEN) Notifying guest 0:45 (virq 1, port 0) Sep 10 07:54:46.431412 (XEN) Notifying guest 0:46 (virq 1, port 0) Sep 10 07:54:46.431412 (XEN) Notifying guest 0:47 (virq 1, port 0) Sep 10 07:54:46.431412 (XEN) Notifying guest 0:48 (virq 1, port 0) Sep 10 07:54:46.443414 (XEN) Notifying guest 0:49 (virq 1, port 0) Sep 10 07:54:46.443414 (XEN) Notifying guest 0:50 (virq 1, port 0) Sep 10 07:54:46.443414 (XEN) Notifying guest 0:51 (virq 1, port 0) Sep 10 07:54:46.455409 (XEN) Notifying guest 0:52 (virq 1, port 0) Sep 10 07:54:46.455409 (XEN) Notifying guest 0:53 (virq 1, port 0) Sep 10 07:54:46.455409 (XEN) Notifying guest 0:54 (virq 1, port 0) Sep 10 07:54:46.467409 (XEN) Notifying guest 0:55 (virq 1, port 0) Sep 10 07:54:46.467409 (XEN) Notifying guest 0:56 (virq 1, port 0) Sep 10 07:54:46.467409 (XEN) Notifying guest 0:57 (virq 1, port 0) Sep 10 07:54:46.479409 (XEN) Notifying guest 0:58 (virq 1, port 0) Sep 10 07:54:46.479409 (XEN) Notifying guest 0:59 (virq 1, port 0) Sep 10 07:54:46.479409 (XEN) Notifying guest 0:60 (virq 1, port 0) Sep 10 07:54:46.491510 (XEN) Notifying guest 0:61 (virq 1, port 0) Sep 10 07:54:46.491573 (XEN) Notifying guest 0:62 (virq 1, port 0) Sep 10 07:54:46.491619 (XEN) Notifying guest 0:63 (virq 1, port 0) Sep 10 07:54:46.503413 (XEN) Notifying guest 0:64 (virq 1, port 0) Sep 10 07:54:46.503413 (XEN) Notifying guest 0:65 (virq 1, port 0) Sep 10 07:54:46.503413 (XEN) Notifying guest 0:66 (virq 1, port 0) Sep 10 07:54:46.515412 (XEN) Notifying guest 0:67 (virq 1, port 0) Sep 10 07:54:46.515412 (XEN) Notifying guest 0:68 (virq 1, port 0) Sep 10 07:54:46.515412 (XEN) Notifying guest 0:69 (virq 1, port 0) Sep 10 07:54:46.527397 (XEN) Notifying guest 0:70 (virq 1, port 0) Sep 10 07:54:46.527397 (XEN) Notifying guest 0:71 (virq 1, port 0) Sep 10 07:54:46.527397 (XEN) Notifying guest 0:72 (virq 1, port 0) Sep 10 07:54:46.539416 (XEN) Notifying guest 0:73 (virq 1, port 0) Sep 10 07:54:46.539416 (XEN) Notifying guest 0:74 (virq 1, port 0) Sep 10 07:54:46.539416 (XEN) Notifying guest 0:75 (virq 1, port 0) Sep 10 07:54:46.551408 (XEN) Notifying guest 0:76 (virq 1, port 0) Sep 10 07:54:46.551408 (XEN) Notifying guest 0:77 (virq 1, port 0) Sep 10 07:54:46.551408 (XEN) Notifying guest 0:78 (virq 1, port 0) Sep 10 07:54:46.563408 (XEN) Notifying guest 0:79 (virq 1, port 0) Sep 10 07:54:46.563408 (XEN) Notifying guest 0:80 (virq 1, port 0) Sep 10 07:54:46.563408 (XEN) Notifying guest 0:81 (virq 1, port 0) Sep 10 07:54:46.575398 (XEN) Notifying guest 0:82 (virq 1, port 0) Sep 10 07:54:46.575398 (XEN) Notifying guest 0:83 (virq 1, port 0) Sep 10 07:54:46.575398 (XEN) Notifying guest 0:84 (virq 1, port 0) Sep 10 07:54:46.587508 (XEN) Notifying guest 0:85 (virq 1, port 0) Sep 10 07:54:46.587573 (XEN) Notifying guest 0:86 (virq 1, port 0) Sep 10 07:54:46.587619 (XEN) Notifying guest 0:87 (virq 1, port 0) Sep 10 07:54:46.599411 (XEN) Notifying guest 0:88 (virq 1, port 0) Sep 10 07:54:46.599411 (XEN) Notifying guest 0:89 (virq 1, port 0) Sep 10 07:54:46.599411 (XEN) Notifying guest 0:90 (virq 1, port 0) Sep 10 07:54:46.611410 (XEN) Notifying guest 0:91 (virq 1, port 0) Sep 10 07:54:46.611410 (XEN) Notifying guest 0:92 (virq 1, port 0) Sep 10 07:54:46.611410 (XEN) Notifying guest 0:93 (virq 1, port 0) Sep 10 07:54:46.623395 (XEN) Notifying guest 0:94 (virq 1, port 0) Sep 10 07:54:46.623395 (XEN) Notifying guest 0:95 (virq 1, port 0) Sep 10 07:54:46.623395 Sep 10 07:54:53.129265 (XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input) Sep 10 07:54:53.155565 Sep 10 07:54:53.157003