Sep 12 04:31:09.907065 (XEN) VTCR_EL2: 00000000800d3590 Sep 12 04:31:09.907349 (XEN) VTTBR_EL2: 00010107eb7a3000 Sep 12 04:31:09.916835 (XEN) Sep 12 04:31:09.916907 (XEN) SCTLR_EL2: 0000000030cd183d Sep 12 04:31:09.916952 (XEN) HCR_EL2: 00000000807c663f Sep 12 04:31:09.916995 (XEN) TTBR0_EL2: 000001071e295000 Sep 12 04:31:09.928856 (XEN) Sep 12 04:31:09.928910 (XEN) ESR_EL2: 0000000007e00000 Sep 12 04:31:09.928976 (XEN) HPFAR_EL2: 0000009010802f00 Sep 12 04:31:09.929020 (XEN) FAR_EL2: ffff8000832f0100 Sep 12 04:31:09.929062 (XEN) Sep 12 04:31:09.929100 (XEN) Xen stack trace from sp=0000800ffd837e60: Sep 12 04:31:09.940869 (XEN) 0000800ffd837e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Sep 12 04:31:09.940954 (XEN) 000000000000005c 0000000000000000 0000000000000000 000000000001020c Sep 12 04:31:09.952870 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:09.964861 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:09.964924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:09.976854 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:09.976938 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:09.988855 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:09.988918 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.000863 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.000926 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.012861 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.024852 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.024915 (XEN) Xen call trace: Sep 12 04:31:10.024958 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Sep 12 04:31:10.036856 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Sep 12 04:31:10.036941 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Sep 12 04:31:10.048867 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Sep 12 04:31:10.048927 (XEN) Sep 12 04:31:10.048967 (XEN) *** Dumping CPU93 host state: *** Sep 12 04:31:10.049012 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 12 04:31:10.060863 (XEN) CPU: 93 Sep 12 04:31:10.060919 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Sep 12 04:31:10.072850 (XEN) LR: 00000a000025d1b0 Sep 12 04:31:10.072908 (XEN) SP: 0000800ffd827e60 Sep 12 04:31:10.072953 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 12 04:31:10.073024 (XEN) X0: 0000000000000000 X1: 0000760ffd514000 X2: 0000800ffd82c048 Sep 12 04:31:10.084862 (XEN) X3: ffffffffffffff9f X4: 0000000000000000 X5: 00000a000034e5a8 Sep 12 04:31:10.096855 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd82f280 X8: 0000000000000012 Sep 12 04:31:10.096918 (XEN) X9: 0000000000000000 X10: ffff000002126870 X11: 0000000000000040 Sep 12 04:31:10.108854 (XEN) X12: ffff800009c7ebb0 X13: 0000000000000001 X14: 0000000000000000 Sep 12 04:31:10.108939 (XEN) X15: ffff00007fba7d80 X16: ffff800008008000 X17: ffff8000763f1000 Sep 12 04:31:10.120857 (XEN) X18: ffffffffffffffff X19: 00000a000034e5b8 X20: 000000000000005d Sep 12 04:31:10.120920 (XEN) X21: 00000a0000320e00 X22: 0000000020000000 X23: 000000000000005d Sep 12 04:31:10.132861 (XEN) X24: 000000000000005d X25: 0000000000000000 X26: 0000000000000000 Sep 12 04:31:10.132924 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd827e60 Sep 12 04:31:10.144863 (XEN) Sep 12 04:31:10.144916 (XEN) VTCR_EL2: 00000000800d3590 Sep 12 04:31:10.144961 (XEN) VTTBR_EL2: 00020100017d6000 Sep 12 04:31:10.156943 (XEN) Sep 12 04:31:10.156996 (XEN) SCTLR_EL2: 0000000030cd183d Sep 12 04:31:10.157040 (XEN) HCR_EL2: 00000000807c663f Sep 12 04:31:10.157100 (XEN) TTBR0_EL2: 000001071e295000 Sep 12 04:31:10.157147 (XEN) Sep 12 04:31:10.168880 (XEN) ESR_EL2: 0000000007e00000 Sep 12 04:31:10.168938 (XEN) HPFAR_EL2: 0000000000030500 Sep 12 04:31:10.168983 (XEN) FAR_EL2: ffff80000a030100 Sep 12 04:31:10.169026 (XEN) Sep 12 04:31:10.169065 (XEN) Xen stack trace from sp=0000800ffd827e60: Sep 12 04:31:10.180883 (XEN) 0000800ffd827e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Sep 12 04:31:10.180947 (XEN) 000000000000005d 0000000000000000 0000000000000000 000000000001020d Sep 12 04:31:10.192888 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.192951 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.204900 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.216898 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.216961 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.228901 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.228964 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.240900 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.240983 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.252918 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.252981 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.264910 (XEN) Xen call trace: Sep 12 04:31:10.264965 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Sep 12 04:31:10.276898 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Sep 12 04:31:10.276962 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Sep 12 04:31:10.288907 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Sep 12 04:31:10.288967 (XEN) Sep 12 04:31:10.289008 (XEN) *** Dumping CPU94 host state: *** Sep 12 04:31:10.289075 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 12 04:31:10.300903 (XEN) CPU: 94 Sep 12 04:31:10.300958 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Sep 12 04:31:10.301008 (XEN) LR: 00000a000025d1b0 Sep 12 04:31:10.312913 (XEN) SP: 0000800feb7bfe60 Sep 12 04:31:10.312991 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 12 04:31:10.313044 (XEN) X0: 0000000000000000 X1: 0000760ffd512000 X2: 0000800ffd82a048 Sep 12 04:31:10.324910 (XEN) X3: ffffffffffffff9f X4: 0000000000000000 X5: 00000a000034e5a8 Sep 12 04:31:10.324974 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd82f740 X8: 0000000000000012 Sep 12 04:31:10.336912 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Sep 12 04:31:10.348900 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Sep 12 04:31:10.348963 (XEN) X15: 0000000000000001 X16: 1fffe00006de2e41 X17: 0000000000000000 Sep 12 04:31:10.360903 (XEN) X18: ffff80009525bc58 X19: 00000a000034e5b8 X20: 000000000000005e Sep 12 04:31:10.360968 (XEN) X21: 00000a0000320e80 X22: 0000000040000000 X23: 000000000000005e Sep 12 04:31:10.372912 (XEN) X24: 000000000000005e X25: 0000000000000000 X26: 0000000000000000 Sep 12 04:31:10.372997 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800feb7bfe60 Sep 12 04:31:10.384910 (XEN) Sep 12 04:31:10.384963 (XEN) VTCR_EL2: 00000000800d3590 Sep 12 04:31:10.385009 (XEN) VTTBR_EL2: 00010107eb7a3000 Sep 12 04:31:10.396891 (XEN) Sep 12 04:31:10.396967 (XEN) SCTLR_EL2: 0000000030cd183d Sep 12 04:31:10.397014 (XEN) HCR_EL2: 00000000807c663f Sep 12 04:31:10.397057 (XEN) TTBR0_EL2: 000001071e295000 Sep 12 04:31:10.397099 (XEN) Sep 12 04:31:10.397137 (XEN) ESR_EL2: 0000000007e00000 Sep 12 04:31:10.408909 (XEN) HPFAR_EL2: 0000009010804700 Sep 12 04:31:10.408986 (XEN) FAR_EL2: ffff800083470100 Sep 12 04:31:10.409033 (XEN) Sep 12 04:31:10.409073 (XEN) Xen stack trace from sp=0000800feb7bfe60: Sep 12 04:31:10.420906 (XEN) 0000800feb7bfe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Sep 12 04:31:10.420990 (XEN) 000000000000005e 0000000000000000 0000000000000000 000000000001020e Sep 12 04:31:10.432899 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.432961 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.444907 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.444970 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.456903 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.468880 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.468914 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.480902 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.480966 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.492897 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.492959 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.504915 (XEN) Xen call trace: Sep 12 04:31:10.504971 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Sep 12 04:31:10.516861 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Sep 12 04:31:10.516924 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Sep 12 04:31:10.516995 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Sep 12 04:31:10.528906 (XEN) Sep 12 04:31:10.528959 (XEN) *** Dumping CPU95 host state: *** Sep 12 04:31:10.529005 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Sep 12 04:31:10.540900 (XEN) CPU: 95 Sep 12 04:31:10.540977 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Sep 12 04:31:10.541028 (XEN) LR: 00000a000025d1b0 Sep 12 04:31:10.541071 (XEN) SP: 0000800feb7afe60 Sep 12 04:31:10.552904 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Sep 12 04:31:10.552968 (XEN) X0: 0000000000000000 X1: 0000760feb49e000 X2: 0000800feb7b6048 Sep 12 04:31:10.564916 (XEN) X3: ffffffffffffff9f X4: 0000000000000000 X5: 00000a000034e5a8 Sep 12 04:31:10.564979 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd82fc00 X8: 0000000000000012 Sep 12 04:31:10.576908 (XEN) X9: 0000000000000000 X10: ffff000002126270 X11: 0000000000000040 Sep 12 04:31:10.576972 (XEN) X12: ffff800009c7ebb0 X13: 0000000000000001 X14: 0000000000000000 Sep 12 04:31:10.588901 (XEN) X15: ffff00007fba7d80 X16: ffff800008008000 X17: ffff8000763f1000 Sep 12 04:31:10.600896 (XEN) X18: ffffffffffffffff X19: 00000a000034e5b8 X20: 000000000000005f Sep 12 04:31:10.600958 (XEN) X21: 00000a0000320f00 X22: 0000000080000000 X23: 000000000000005f Sep 12 04:31:10.612897 (XEN) X24: 000000000000005f X25: 0000000000000000 X26: 0000000000000000 Sep 12 04:31:10.612960 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800feb7afe60 Sep 12 04:31:10.624905 (XEN) Sep 12 04:31:10.624979 (XEN) VTCR_EL2: 00000000800d3590 Sep 12 04:31:10.625025 (XEN) VTTBR_EL2: 00020100014d3000 Sep 12 04:31:10.625070 (XEN) Sep 12 04:31:10.625110 (XEN) SCTLR_EL2: 0000000030cd183d Sep 12 04:31:10.636908 (XEN) HCR_EL2: 00000000807c663f Sep 12 04:31:10.636987 (XEN) TTBR0_EL2: 000001071e295000 Sep 12 04:31:10.637032 (XEN) Sep 12 04:31:10.637071 (XEN) ESR_EL2: 0000000007e00000 Sep 12 04:31:10.648892 (XEN) HPFAR_EL2: 0000000000030500 Sep 12 04:31:10.648949 (XEN) FAR_EL2: ffff80000a030100 Sep 12 04:31:10.649017 (XEN) Sep 12 04:31:10.649056 (XEN) Xen stack trace from sp=0000800feb7afe60: Sep 12 04:31:10.649103 (XEN) 0000800feb7afe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Sep 12 04:31:10.660926 (XEN) 000000000000005f 0000000000000000 0000000000000000 000000000001020f Sep 12 04:31:10.672911 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.672995 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.684899 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.684961 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.696906 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.696969 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.708906 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.720898 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.720961 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.732900 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.732962 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Sep 12 04:31:10.744903 (XEN) Xen call trace: Sep 12 04:31:10.744960 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Sep 12 04:31:10.745010 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Sep 12 04:31:10.756922 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Sep 12 04:31:10.756984 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Sep 12 04:31:10.768854 (XEN) Sep 12 04:31:10.768907 Sep 12 04:31:16.611621 (XEN) 'q' pressed -> dumping domain info (now = 2509293268520) Sep 12 04:31:16.636931 (XEN) General information for domain 0: Sep 12 04:31:16.636993 (XEN) refcnt=3 dying=0 p Sep 12 04:31:16.639254 ause_count=0 Sep 12 04:31:16.648762 (XEN) nr_pages=131072 xenheap_pages=2 dirty_cpus={} max_pages=131072 Sep 12 04:31:16.648808 (XEN) handle=00000000-0000-0000-0000-000000000000 vm_assist=00000020 Sep 12 04:31:16.660894 (XEN) p2m mappings for domain 0 (vmid 1): Sep 12 04:31:16.660955 (XEN) 1G mappings: 4984 (shattered 3) Sep 12 04:31:16.661001 (XEN) 2M mappings: 1444361 (shattered 189) Sep 12 04:31:16.672861 (XEN) 4K mappings: 96784 Sep 12 04:31:16.672941 (XEN) Rangesets belonging to domain 0: Sep 12 04:31:16.672989 (XEN) Interrupts { 32, 38, 48-51 } Sep 12 04:31:16.673033 (XEN) I/O Memory { 802000000-808000000, 810000000-820000000, 838000000-844000000, 846000000-848002000, 849000000-849002000, 84a000000-84a002000, 84b000000-84b002000, 868000000-880000000, 88001f000-880058000, 881010000-883000010, 902000000-908000000, 910000000-920000000, 938000000-944000000, 946000000-948002000, 949000000-949002000, 94a000000-94a002000, 94b000000-94b002000, 968000000-980000000 } Sep 12 04:31:16.708925 (XEN) NODE affinity for domain 0: [0] Sep 12 04:31:16.720905 (XEN) VCPU information and callbacks for domain 0: Sep 12 04:31:16.720967 (XEN) UNIT0 affinities: hard={0-95} soft={0-95} Sep 12 04:31:16.721015 (XEN) VCPU0: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:16.732913 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:16.732972 (XEN) GICH_LRs (vcpu 0) mask=0 Sep 12 04:31:16.733017 (XEN) VCPU_LR[0]=0 Sep 12 04:31:16.744902 (XEN) VCPU_LR[1]=0 Sep 12 04:31:16.744959 (XEN) VCPU_LR[2]=0 Sep 12 04:31:16.745001 (XEN) VCPU_LR[3]=0 Sep 12 04:31:16.745042 (XEN) VCPU_LR[4]=0 Sep 12 04:31:16.745083 (XEN) VCPU_LR[5]=0 Sep 12 04:31:16.745124 (XEN) VCPU_LR[6]=0 Sep 12 04:31:16.756902 (XEN) VCPU_LR[7]=0 Sep 12 04:31:16.756958 (XEN) VCPU_LR[8]=0 Sep 12 04:31:16.757000 (XEN) VCPU_LR[9]=0 Sep 12 04:31:16.757042 (XEN) VCPU_LR[10]=0 Sep 12 04:31:16.757083 (XEN) VCPU_LR[11]=0 Sep 12 04:31:16.768895 (XEN) VCPU_LR[12]=0 Sep 12 04:31:16.768953 (XEN) VCPU_LR[13]=0 Sep 12 04:31:16.769021 (XEN) VCPU_LR[14]=0 Sep 12 04:31:16.769065 (XEN) VCPU_LR[15]=0 Sep 12 04:31:16.769106 (XEN) No periodic timer Sep 12 04:31:16.769147 (XEN) UNIT1 affinities: hard={0-95} soft={0-95} Sep 12 04:31:16.780903 (XEN) VCPU1: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:16.780967 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:16.792911 (XEN) GICH_LRs (vcpu 1) mask=0 Sep 12 04:31:16.792969 (XEN) VCPU_LR[0]=0 Sep 12 04:31:16.793012 (XEN) VCPU_LR[1]=0 Sep 12 04:31:16.793052 (XEN) VCPU_LR[2]=0 Sep 12 04:31:16.793092 (XEN) VCPU_LR[3]=0 Sep 12 04:31:16.793132 (XEN) VCPU_LR[4]=0 Sep 12 04:31:16.804902 (XEN) VCPU_LR[5]=0 Sep 12 04:31:16.804958 (XEN) VCPU_LR[6]=0 Sep 12 04:31:16.805000 (XEN) VCPU_LR[7]=0 Sep 12 04:31:16.805040 (XEN) VCPU_LR[8]=0 Sep 12 04:31:16.805080 (XEN) VCPU_LR[9]=0 Sep 12 04:31:16.805119 (XEN) VCPU_LR[10]=0 Sep 12 04:31:16.816878 (XEN) VCPU_LR[11]=0 Sep 12 04:31:16.816935 (XEN) VCPU_LR[12]=0 Sep 12 04:31:16.816977 (XEN) VCPU_LR[13]=0 Sep 12 04:31:16.817017 (XEN) VCPU_LR[14]=0 Sep 12 04:31:16.817058 (XEN) VCPU_LR[15]=0 Sep 12 04:31:16.828881 (XEN) No periodic timer Sep 12 04:31:16.828937 (XEN) UNIT2 affinities: hard={0-95} soft={0-95} Sep 12 04:31:16.828984 (XEN) VCPU2: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:16.840905 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:16.840964 (XEN) GICH_LRs (vcpu 2) mask=0 Sep 12 04:31:16.841009 (XEN) VCPU_LR[0]=0 Sep 12 04:31:16.841049 (XEN) VCPU_LR[1]=0 Sep 12 04:31:16.852900 (XEN) VCPU_LR[2]=0 Sep 12 04:31:16.852956 (XEN) VCPU_LR[3]=0 Sep 12 04:31:16.852998 (XEN) VCPU_LR[4]=0 Sep 12 04:31:16.853038 (XEN) VCPU_LR[5]=0 Sep 12 04:31:16.853078 (XEN) VCPU_LR[6]=0 Sep 12 04:31:16.853118 (XEN) VCPU_LR[7]=0 Sep 12 04:31:16.864896 (XEN) VCPU_LR[8]=0 Sep 12 04:31:16.864952 (XEN) VCPU_LR[9]=0 Sep 12 04:31:16.864994 (XEN) VCPU_LR[10]=0 Sep 12 04:31:16.865035 (XEN) VCPU_LR[11]=0 Sep 12 04:31:16.865075 (XEN) VCPU_LR[12]=0 Sep 12 04:31:16.865117 (XEN) VCPU_LR[13]=0 Sep 12 04:31:16.876896 (XEN) VCPU_LR[14]=0 Sep 12 04:31:16.876953 (XEN) VCPU_LR[15]=0 Sep 12 04:31:16.876995 (XEN) No periodic timer Sep 12 04:31:16.877036 (XEN) UNIT3 affinities: hard={0-95} soft={0-95} Sep 12 04:31:16.877082 (XEN) VCPU3: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:16.888917 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:16.888977 (XEN) GICH_LRs (vcpu 3) mask=0 Sep 12 04:31:16.889022 (XEN) VCPU_LR[0]=0 Sep 12 04:31:16.900897 (XEN) VCPU_LR[1]=0 Sep 12 04:31:16.900952 (XEN) VCPU_LR[2]=0 Sep 12 04:31:16.900995 (XEN) VCPU_LR[3]=0 Sep 12 04:31:16.901038 (XEN) VCPU_LR[4]=0 Sep 12 04:31:16.901078 (XEN) VCPU_LR[5]=0 Sep 12 04:31:16.901118 (XEN) VCPU_LR[6]=0 Sep 12 04:31:16.912912 (XEN) VCPU_LR[7]=0 Sep 12 04:31:16.912967 (XEN) VCPU_LR[8]=0 Sep 12 04:31:16.913009 (XEN) VCPU_LR[9]=0 Sep 12 04:31:16.913049 (XEN) VCPU_LR[10]=0 Sep 12 04:31:16.913088 (XEN) VCPU_LR[11]=0 Sep 12 04:31:16.913127 (XEN) VCPU_LR[12]=0 Sep 12 04:31:16.924897 (XEN) VCPU_LR[13]=0 Sep 12 04:31:16.924953 (XEN) VCPU_LR[14]=0 Sep 12 04:31:16.924994 (XEN) VCPU_LR[15]=0 Sep 12 04:31:16.925035 (XEN) No periodic timer Sep 12 04:31:16.925077 (XEN) UNIT4 affinities: hard={0-95} soft={0-95} Sep 12 04:31:16.936903 (XEN) VCPU4: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:16.936966 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:16.948896 (XEN) GICH_LRs (vcpu 4) mask=0 Sep 12 04:31:16.948956 (XEN) VCPU_LR[0]=0 Sep 12 04:31:16.948998 (XEN) VCPU_LR[1]=0 Sep 12 04:31:16.949038 (XEN) VCPU_LR[2]=0 Sep 12 04:31:16.949078 (XEN) VCPU_LR[3]=0 Sep 12 04:31:16.960894 (XEN) VCPU_LR[4]=0 Sep 12 04:31:16.960932 (XEN) VCPU_LR[5]=0 Sep 12 04:31:16.960957 (XEN) VCPU_LR[6]=0 Sep 12 04:31:16.960979 (XEN) VCPU_LR[7]=0 Sep 12 04:31:16.961001 (XEN) VCPU_LR[8]=0 Sep 12 04:31:16.961022 (XEN) VCPU_LR[9]=0 Sep 12 04:31:16.972926 (XEN) VCPU_LR[10]=0 Sep 12 04:31:16.972983 (XEN) VCPU_LR[11]=0 Sep 12 04:31:16.973026 (XEN) VCPU_LR[12]=0 Sep 12 04:31:16.973067 (XEN) VCPU_LR[13]=0 Sep 12 04:31:16.973107 (XEN) VCPU_LR[14]=0 Sep 12 04:31:16.973146 (XEN) VCPU_LR[15]=0 Sep 12 04:31:16.984901 (XEN) No periodic timer Sep 12 04:31:16.984957 (XEN) UNIT5 affinities: hard={0-95} soft={0-95} Sep 12 04:31:16.985005 (XEN) VCPU5: CPU67 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:16.996901 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:16.996959 (XEN) GICH_LRs (vcpu 5) mask=0 Sep 12 04:31:16.997003 (XEN) VCPU_LR[0]=0 Sep 12 04:31:16.997044 (XEN) VCPU_LR[1]=0 Sep 12 04:31:16.997085 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.008906 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.008961 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.009004 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.009045 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.009090 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.009150 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.020904 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.020960 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.021002 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.021044 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.021084 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.032904 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.032960 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.033004 (XEN) No periodic timer Sep 12 04:31:17.033046 (XEN) UNIT6 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.033092 (XEN) VCPU6: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.044908 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.044966 (XEN) GICH_LRs (vcpu 6) mask=0 Sep 12 04:31:17.045010 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.056900 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.056955 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.056996 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.057037 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.057077 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.057117 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.068887 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.068942 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.068984 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.069024 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.069064 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.080904 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.080961 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.081003 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.081044 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.081083 (XEN) No periodic timer Sep 12 04:31:17.081125 (XEN) UNIT7 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.092907 (XEN) VCPU7: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.092971 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.104902 (XEN) GICH_LRs (vcpu 7) mask=0 Sep 12 04:31:17.104961 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.105005 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.105046 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.105086 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.116898 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.116954 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.116996 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.117037 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.117077 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.117117 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.128894 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.128951 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.128994 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.129036 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.129077 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.129117 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.140900 (XEN) No periodic timer Sep 12 04:31:17.140956 (XEN) UNIT8 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.141004 (XEN) VCPU8: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.152899 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.152957 (XEN) GICH_LRs (vcpu 8) mask=0 Sep 12 04:31:17.153001 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.153041 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.153082 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.164905 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.164960 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.165021 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.165065 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.165105 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.165145 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.176900 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.176955 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.176997 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.177038 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.177077 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.177117 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.188899 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.188955 (XEN) No periodic timer Sep 12 04:31:17.188997 (XEN) UNIT9 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.189042 (XEN) VCPU9: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.200900 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.200957 (XEN) GICH_LRs (vcpu 9) mask=0 Sep 12 04:31:17.212895 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.212951 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.212993 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.213033 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.213073 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.213112 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.224896 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.224952 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.224994 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.225034 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.225074 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.225114 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.236899 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.236955 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.236998 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.237038 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.237078 (XEN) No periodic timer Sep 12 04:31:17.237119 (XEN) UNIT10 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.248904 (XEN) VCPU10: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.248967 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.260899 (XEN) GICH_LRs (vcpu 10) mask=0 Sep 12 04:31:17.260957 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.260999 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.261039 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.261079 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.272895 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.272953 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.272995 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.273035 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.273075 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.273115 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.284893 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.284951 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.284993 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.285034 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.285073 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.285113 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.296910 (XEN) No periodic timer Sep 12 04:31:17.296966 (XEN) UNIT11 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.297013 (XEN) VCPU11: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.308901 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.308959 (XEN) GICH_LRs (vcpu 11) mask=0 Sep 12 04:31:17.309004 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.309044 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.309085 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.320910 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.320965 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.321006 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.321046 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.321086 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.321125 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.332891 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.332947 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.332988 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.333028 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.333068 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.344900 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.344955 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.344997 (XEN) No periodic timer Sep 12 04:31:17.345038 (XEN) UNIT12 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.356894 (XEN) VCPU12: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.356958 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.357004 (XEN) GICH_LRs (vcpu 12) mask=0 Sep 12 04:31:17.368899 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.368972 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.369018 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.369057 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.369097 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.369136 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.380899 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.380955 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.380996 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.381036 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.381076 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.381116 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.392898 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.392954 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.392996 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.393036 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.393076 (XEN) No periodic timer Sep 12 04:31:17.393117 (XEN) UNIT13 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.404909 (XEN) VCPU13: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.404973 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.416905 (XEN) GICH_LRs (vcpu 13) mask=0 Sep 12 04:31:17.416963 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.417005 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.417046 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.417086 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.428906 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.428961 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.429003 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.429043 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.429082 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.429122 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.440897 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.440953 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.440995 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.441035 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.441075 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.441115 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.452889 (XEN) No periodic timer Sep 12 04:31:17.452945 (XEN) UNIT14 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.452993 (XEN) VCPU14: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.464910 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.464967 (XEN) GICH_LRs (vcpu 14) mask=0 Sep 12 04:31:17.465011 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.465052 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.476902 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.476957 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.476998 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.477038 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.477078 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.477118 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.488902 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.488957 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.488999 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.489039 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.489079 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.500889 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.500947 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.500990 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.501030 (XEN) No periodic timer Sep 12 04:31:17.501071 (XEN) UNIT15 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.512912 (XEN) VCPU15: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.512976 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.513020 (XEN) GICH_LRs (vcpu 15) mask=0 Sep 12 04:31:17.524902 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.524957 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.524999 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.525039 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.525079 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.525118 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.536901 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.536956 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.536997 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.537037 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.537077 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.537117 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.548903 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.548958 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.549000 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.549040 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.549080 (XEN) No periodic timer Sep 12 04:31:17.549121 (XEN) UNIT16 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.560905 (XEN) VCPU16: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.560987 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.572912 (XEN) GICH_LRs (vcpu 16) mask=0 Sep 12 04:31:17.572970 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.573011 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.573051 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.573093 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.584887 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.584942 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.584984 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.585024 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.585064 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.596898 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.596953 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.596995 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.597036 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.597076 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.597117 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.608900 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.608956 (XEN) No periodic timer Sep 12 04:31:17.608999 (XEN) UNIT17 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.609045 (XEN) VCPU17: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.620908 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.620966 (XEN) GICH_LRs (vcpu 17) mask=0 Sep 12 04:31:17.621010 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.632902 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.632958 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.632999 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.633040 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.633080 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.633120 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.644896 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.644953 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.644995 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.645035 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.645074 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.645114 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.656896 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.656951 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.656994 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.657035 (XEN) No periodic timer Sep 12 04:31:17.657076 (XEN) UNIT18 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.668909 (XEN) VCPU18: CPU9 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.668972 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.669017 (XEN) GICH_LRs (vcpu 18) mask=0 Sep 12 04:31:17.680899 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.680955 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.680996 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.681036 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.681076 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.681116 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.692897 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.692952 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.692994 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.693035 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.693075 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.693115 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.704896 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.704951 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.704992 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.705033 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.705072 (XEN) No periodic timer Sep 12 04:31:17.716900 (XEN) UNIT19 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.716961 (XEN) VCPU19: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.728900 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.728958 (XEN) GICH_LRs (vcpu 19) mask=0 Sep 12 04:31:17.729002 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.729043 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.729083 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.740897 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.740952 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.740994 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.741034 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.741074 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.741114 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.752905 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.752960 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.753001 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.753042 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.753082 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.753122 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.764918 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.764975 (XEN) No periodic timer Sep 12 04:31:17.765017 (XEN) UNIT20 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.765063 (XEN) VCPU20: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.776906 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.776963 (XEN) GICH_LRs (vcpu 20) mask=0 Sep 12 04:31:17.777007 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.788912 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.788968 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.789010 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.789050 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.789090 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.789129 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.800913 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.800969 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.801010 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.801050 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.801090 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.801130 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.812899 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.812954 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.812996 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.813037 (XEN) No periodic timer Sep 12 04:31:17.813077 (XEN) UNIT21 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.824913 (XEN) VCPU21: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.824977 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.825022 (XEN) GICH_LRs (vcpu 21) mask=0 Sep 12 04:31:17.836896 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.836952 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.836994 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.837034 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.837074 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.848887 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.848942 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.848984 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.849024 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.849064 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.849105 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.860904 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.860959 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.861000 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.861041 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.861080 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.872898 (XEN) No periodic timer Sep 12 04:31:17.872954 (XEN) UNIT22 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.873001 (XEN) VCPU22: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.884897 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.884955 (XEN) GICH_LRs (vcpu 22) mask=0 Sep 12 04:31:17.884999 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.885040 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.885080 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.896914 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.896968 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.897009 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.897050 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.897090 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.897130 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.908896 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.908951 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.908993 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.909033 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.909073 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.909114 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.920912 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.920967 (XEN) No periodic timer Sep 12 04:31:17.921010 (XEN) UNIT23 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.921056 (XEN) VCPU23: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.932907 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.932965 (XEN) GICH_LRs (vcpu 23) mask=0 Sep 12 04:31:17.933009 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.944902 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.944957 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.944998 (XEN) VCPU_LR[3]=0 Sep 12 04:31:17.945038 (XEN) VCPU_LR[4]=0 Sep 12 04:31:17.945078 (XEN) VCPU_LR[5]=0 Sep 12 04:31:17.945117 (XEN) VCPU_LR[6]=0 Sep 12 04:31:17.956899 (XEN) VCPU_LR[7]=0 Sep 12 04:31:17.956955 (XEN) VCPU_LR[8]=0 Sep 12 04:31:17.956996 (XEN) VCPU_LR[9]=0 Sep 12 04:31:17.957054 (XEN) VCPU_LR[10]=0 Sep 12 04:31:17.957097 (XEN) VCPU_LR[11]=0 Sep 12 04:31:17.957137 (XEN) VCPU_LR[12]=0 Sep 12 04:31:17.968907 (XEN) VCPU_LR[13]=0 Sep 12 04:31:17.968963 (XEN) VCPU_LR[14]=0 Sep 12 04:31:17.969005 (XEN) VCPU_LR[15]=0 Sep 12 04:31:17.969045 (XEN) No periodic timer Sep 12 04:31:17.969085 (XEN) UNIT24 affinities: hard={0-95} soft={0-95} Sep 12 04:31:17.980911 (XEN) VCPU24: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:17.980974 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:17.992903 (XEN) GICH_LRs (vcpu 24) mask=0 Sep 12 04:31:17.992960 (XEN) VCPU_LR[0]=0 Sep 12 04:31:17.993002 (XEN) VCPU_LR[1]=0 Sep 12 04:31:17.993042 (XEN) VCPU_LR[2]=0 Sep 12 04:31:17.993082 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.004907 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.004963 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.005005 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.005046 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.005086 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.005125 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.016897 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.016954 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.016996 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.017037 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.017077 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.017117 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.028897 (XEN) No periodic timer Sep 12 04:31:18.028953 (XEN) UNIT25 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.029001 (XEN) VCPU25: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.040897 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.040955 (XEN) GICH_LRs (vcpu 25) mask=0 Sep 12 04:31:18.041000 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.041040 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.041080 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.052910 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.052965 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.053006 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.053046 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.053086 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.053125 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.064900 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.064955 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.064997 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.065037 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.065077 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.076908 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.076965 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.077008 (XEN) No periodic timer Sep 12 04:31:18.077049 (XEN) UNIT26 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.077095 (XEN) VCPU26: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.088898 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.088956 (XEN) GICH_LRs (vcpu 26) mask=0 Sep 12 04:31:18.100900 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.100955 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.100998 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.101038 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.101078 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.101117 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.112903 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.112958 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.112999 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.113039 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.113079 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.113119 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.124902 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.124958 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.125000 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.125041 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.125080 (XEN) No periodic timer Sep 12 04:31:18.125121 (XEN) UNIT27 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.136910 (XEN) VCPU27: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.136973 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.148905 (XEN) GICH_LRs (vcpu 27) mask=0 Sep 12 04:31:18.148962 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.149004 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.149044 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.149084 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.160908 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.160964 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.161023 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.161067 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.161106 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.161146 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.172900 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.172956 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.172998 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.173038 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.173078 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.173118 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.184901 (XEN) No periodic timer Sep 12 04:31:18.184957 (XEN) UNIT28 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.185004 (XEN) VCPU28: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.196905 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.196963 (XEN) GICH_LRs (vcpu 28) mask=0 Sep 12 04:31:18.197008 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.197048 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.208900 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.208955 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.208997 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.209038 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.209078 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.209118 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.220887 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.220943 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.220984 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.221025 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.221065 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.232898 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.232954 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.232997 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.233037 (XEN) No periodic timer Sep 12 04:31:18.233079 (XEN) UNIT29 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.244899 (XEN) VCPU29: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.244963 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.245008 (XEN) GICH_LRs (vcpu 29) mask=0 Sep 12 04:31:18.256794 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.256824 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.256846 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.256868 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.256890 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.256911 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.268901 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.268957 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.268999 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.269038 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.269078 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.269118 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.280898 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.280953 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.280995 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.281035 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.281075 (XEN) No periodic timer Sep 12 04:31:18.292908 (XEN) UNIT30 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.292970 (XEN) VCPU30: CPU7 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.293021 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.304908 (XEN) GICH_LRs (vcpu 30) mask=0 Sep 12 04:31:18.304966 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.305007 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.305047 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.305088 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.316893 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.316948 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.316990 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.317029 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.317070 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.317109 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.328909 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.328964 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.329006 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.329047 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.329086 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.329126 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.340896 (XEN) No periodic timer Sep 12 04:31:18.340952 (XEN) UNIT31 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.341000 (XEN) VCPU31: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.352918 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.352976 (XEN) GICH_LRs (vcpu 31) mask=0 Sep 12 04:31:18.353020 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.364918 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.364976 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.365017 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.365057 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.365097 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.365136 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.376898 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.376954 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.376996 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.377037 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.377077 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.377117 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.388899 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.388955 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.388997 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.389037 (XEN) No periodic timer Sep 12 04:31:18.389079 (XEN) UNIT32 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.400898 (XEN) VCPU32: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.400962 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.401007 (XEN) GICH_LRs (vcpu 32) mask=0 Sep 12 04:31:18.412917 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.412973 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.413014 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.413055 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.413095 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.413134 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.424896 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.424951 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.424993 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.425033 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.425073 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.425113 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.436903 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.436959 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.437001 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.437041 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.437082 (XEN) No periodic timer Sep 12 04:31:18.448903 (XEN) UNIT33 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.448964 (XEN) VCPU33: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.449015 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.460897 (XEN) GICH_LRs (vcpu 33) mask=0 Sep 12 04:31:18.460954 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.460996 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.461036 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.461076 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.472903 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.472959 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.473000 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.473041 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.473080 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.484899 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.484954 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.484996 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.485036 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.485076 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.485116 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.496899 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.496954 (XEN) No periodic timer Sep 12 04:31:18.496996 (XEN) UNIT34 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.497043 (XEN) VCPU34: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.508912 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.508970 (XEN) GICH_LRs (vcpu 34) mask=0 Sep 12 04:31:18.509014 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.520900 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.520956 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.520998 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.521037 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.521077 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.521117 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.532908 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.532963 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.533005 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.533046 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.533088 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.533128 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.544903 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.544959 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.545001 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.545042 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.545084 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.556910 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.556986 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.557033 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.557075 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.557116 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.568904 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.568961 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.569005 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.569047 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.580910 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.580967 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.581009 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.581050 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.592899 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.592957 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.592999 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.593041 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.604891 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.604949 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.604992 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.605034 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.616898 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.616955 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.616998 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.617040 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.617082 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.628908 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.628964 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.629007 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.629049 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.640902 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.640959 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.641003 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.641044 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.652905 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.652962 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.653005 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.653047 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.664903 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.664962 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.665006 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.665047 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.665089 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.676898 (XEN) Inflight irq=8298 lr=255 Sep 12 04:31:18.676955 (XEN) Pending irq=8298 Sep 12 04:31:18.676997 (XEN) Pending irq=8298 Sep 12 04:31:18.677038 (XEN) Pending irq=8298 Sep 12 04:31:18.677079 (XEN) Pending irq=8298 Sep 12 04:31:18.688894 (XEN) Pending irq=8298 Sep 12 04:31:18.688950 (XEN) Pending irq=8298 Sep 12 04:31:18.688992 (XEN) Pending irq=8298 Sep 12 04:31:18.689032 (XEN) Pending irq=8298 Sep 12 04:31:18.689072 (XEN) Pending irq=8298 Sep 12 04:31:18.689112 (XEN) Pending irq=8298 Sep 12 04:31:18.700899 (XEN) Pending irq=8298 Sep 12 04:31:18.700955 (XEN) Pending irq=8298 Sep 12 04:31:18.700997 (XEN) Pending irq=8298 Sep 12 04:31:18.701037 (XEN) Pending irq=8298 Sep 12 04:31:18.701077 (XEN) Pending irq=8298 Sep 12 04:31:18.701117 (XEN) Pending irq=8298 Sep 12 04:31:18.712904 (XEN) Pending irq=8298 Sep 12 04:31:18.712958 (XEN) Pending irq=8298 Sep 12 04:31:18.713000 (XEN) Pending irq=8298 Sep 12 04:31:18.713040 (XEN) Pending irq=8298 Sep 12 04:31:18.713080 (XEN) Pending irq=8298 Sep 12 04:31:18.724898 (XEN) Pending irq=8298 Sep 12 04:31:18.724954 (XEN) Pending irq=8298 Sep 12 04:31:18.724996 (XEN) Pending irq=8298 Sep 12 04:31:18.725036 (XEN) Pending irq=8298 Sep 12 04:31:18.725076 (XEN) Pending irq=8298 Sep 12 04:31:18.736902 (XEN) Pending irq=8298 Sep 12 04:31:18.736958 (XEN) Pending irq=8298 Sep 12 04:31:18.737000 (XEN) Pending irq=8298 Sep 12 04:31:18.737041 (XEN) Pending irq=8298 Sep 12 04:31:18.737081 (XEN) Pending irq=8298 Sep 12 04:31:18.737122 (XEN) Pending irq=8298 Sep 12 04:31:18.748911 (XEN) Pending irq=8298 Sep 12 04:31:18.748966 (XEN) Pending irq=8298 Sep 12 04:31:18.749008 (XEN) Pending irq=8298 Sep 12 04:31:18.749048 (XEN) Pending irq=8298 Sep 12 04:31:18.749087 (XEN) Pending irq=8298 Sep 12 04:31:18.749145 (XEN) Pending irq=8298 Sep 12 04:31:18.760897 (XEN) Pending irq=8298 Sep 12 04:31:18.760952 (XEN) Pending irq=8298 Sep 12 04:31:18.760994 (XEN) Pending irq=8298 Sep 12 04:31:18.761034 (XEN) Pending irq=8298 Sep 12 04:31:18.761074 (XEN) Pending irq=8298 Sep 12 04:31:18.772893 (XEN) Pending irq=8298 Sep 12 04:31:18.772950 (XEN) Pending irq=8298 Sep 12 04:31:18.772992 (XEN) Pending irq=8298 Sep 12 04:31:18.773033 (XEN) Pending irq=8298 Sep 12 04:31:18.773073 (XEN) Pending irq=8298 Sep 12 04:31:18.773112 (XEN) Pending irq=8298 Sep 12 04:31:18.784899 (XEN) Pending irq=8298 Sep 12 04:31:18.784955 (XEN) Pending irq=8298 Sep 12 04:31:18.784997 (XEN) Pending irq=8298 Sep 12 04:31:18.785037 (XEN) Pending irq=8298 Sep 12 04:31:18.785077 (XEN) Pending irq=8298 Sep 12 04:31:18.785116 (XEN) Pending irq=8298 Sep 12 04:31:18.796910 (XEN) Pending irq=8298 Sep 12 04:31:18.796966 (XEN) Pending irq=8298 Sep 12 04:31:18.797008 (XEN) Pending irq=8298 Sep 12 04:31:18.797049 (XEN) Pending irq=8298 Sep 12 04:31:18.797089 (XEN) Pending irq=8298 Sep 12 04:31:18.797129 (XEN) No periodic timer Sep 12 04:31:18.808901 (XEN) UNIT35 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.808961 (XEN) VCPU35: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.820896 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.820955 (XEN) GICH_LRs (vcpu 35) mask=0 Sep 12 04:31:18.820999 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.821039 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.821080 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.832913 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.832969 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.833010 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.833051 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.833091 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.833131 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.844858 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.844914 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.844956 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.844996 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.845036 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.845076 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.856893 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.856949 (XEN) No periodic timer Sep 12 04:31:18.856991 (XEN) UNIT36 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.857037 (XEN) VCPU36: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.868909 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.868968 (XEN) GICH_LRs (vcpu 36) mask=0 Sep 12 04:31:18.869012 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.880897 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.880952 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.880994 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.881034 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.881074 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.881115 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.892912 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.892967 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.893008 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.893048 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.893088 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.893128 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.904899 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.904954 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.904996 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.905036 (XEN) No periodic timer Sep 12 04:31:18.905077 (XEN) UNIT37 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.916916 (XEN) VCPU37: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.916979 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.928896 (XEN) GICH_LRs (vcpu 37) mask=0 Sep 12 04:31:18.928954 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.928997 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.929037 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.929076 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.929116 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.940893 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.940948 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.940989 (XEN) VCPU_LR[7]=0 Sep 12 04:31:18.941029 (XEN) VCPU_LR[8]=0 Sep 12 04:31:18.941069 (XEN) VCPU_LR[9]=0 Sep 12 04:31:18.941109 (XEN) VCPU_LR[10]=0 Sep 12 04:31:18.952892 (XEN) VCPU_LR[11]=0 Sep 12 04:31:18.952966 (XEN) VCPU_LR[12]=0 Sep 12 04:31:18.953011 (XEN) VCPU_LR[13]=0 Sep 12 04:31:18.953051 (XEN) VCPU_LR[14]=0 Sep 12 04:31:18.953091 (XEN) VCPU_LR[15]=0 Sep 12 04:31:18.953130 (XEN) No periodic timer Sep 12 04:31:18.964907 (XEN) UNIT38 affinities: hard={0-95} soft={0-95} Sep 12 04:31:18.964968 (XEN) VCPU38: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:18.976896 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:18.976955 (XEN) GICH_LRs (vcpu 38) mask=0 Sep 12 04:31:18.976999 (XEN) VCPU_LR[0]=0 Sep 12 04:31:18.977039 (XEN) VCPU_LR[1]=0 Sep 12 04:31:18.988899 (XEN) VCPU_LR[2]=0 Sep 12 04:31:18.988955 (XEN) VCPU_LR[3]=0 Sep 12 04:31:18.988997 (XEN) VCPU_LR[4]=0 Sep 12 04:31:18.989037 (XEN) VCPU_LR[5]=0 Sep 12 04:31:18.989077 (XEN) VCPU_LR[6]=0 Sep 12 04:31:18.989117 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.000892 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.000947 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.000990 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.001030 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.001071 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.001110 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.012913 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.012969 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.013011 (XEN) No periodic timer Sep 12 04:31:19.013052 (XEN) UNIT39 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.013098 (XEN) VCPU39: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.024916 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.024973 (XEN) GICH_LRs (vcpu 39) mask=0 Sep 12 04:31:19.036902 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.036958 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.037000 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.037040 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.037080 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.037119 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.048895 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.048951 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.048993 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.049033 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.049073 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.049113 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.060896 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.060952 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.060995 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.061036 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.061075 (XEN) No periodic timer Sep 12 04:31:19.061116 (XEN) UNIT40 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.072916 (XEN) VCPU40: CPU73 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.072980 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.084902 (XEN) GICH_LRs (vcpu 40) mask=0 Sep 12 04:31:19.084961 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.085003 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.085044 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.085083 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.085123 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.096905 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.096960 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.097002 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.097042 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.097082 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.097122 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.108888 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.108944 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.108986 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.109026 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.109066 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.120899 (XEN) No periodic timer Sep 12 04:31:19.120954 (XEN) UNIT41 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.121002 (XEN) VCPU41: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.132900 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.132958 (XEN) GICH_LRs (vcpu 41) mask=0 Sep 12 04:31:19.133003 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.133044 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.144902 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.144957 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.144999 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.145039 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.145078 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.145137 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.156897 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.156953 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.156995 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.157035 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.157075 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.157115 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.168908 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.168963 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.169004 (XEN) No periodic timer Sep 12 04:31:19.169046 (XEN) UNIT42 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.180895 (XEN) VCPU42: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.180960 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.181005 (XEN) GICH_LRs (vcpu 42) mask=0 Sep 12 04:31:19.192896 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.192952 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.192994 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.193034 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.193074 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.193114 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.204899 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.204955 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.204996 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.205037 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.205078 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.205118 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.216899 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.216955 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.216997 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.217037 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.217077 (XEN) No periodic timer Sep 12 04:31:19.217118 (XEN) UNIT43 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.228903 (XEN) VCPU43: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.228967 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.240896 (XEN) GICH_LRs (vcpu 43) mask=0 Sep 12 04:31:19.240953 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.240995 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.241035 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.241075 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.252905 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.252959 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.253001 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.253041 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.253081 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.253121 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.264899 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.264954 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.264995 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.265035 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.265075 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.276895 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.276951 (XEN) No periodic timer Sep 12 04:31:19.276994 (XEN) UNIT44 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.277040 (XEN) VCPU44: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.288897 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.288955 (XEN) GICH_LRs (vcpu 44) mask=0 Sep 12 04:31:19.288999 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.289039 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.300910 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.300965 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.301006 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.301046 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.301086 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.301126 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.312901 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.312957 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.312998 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.313038 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.313078 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.313118 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.324917 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.324972 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.325014 (XEN) No periodic timer Sep 12 04:31:19.325056 (XEN) UNIT45 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.336900 (XEN) VCPU45: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.336964 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.337009 (XEN) GICH_LRs (vcpu 45) mask=0 Sep 12 04:31:19.348900 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.348956 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.349015 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.349059 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.349099 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.349139 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.360888 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.360944 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.360986 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.361026 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.361066 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.372900 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.372956 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.372998 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.373038 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.373078 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.373118 (XEN) No periodic timer Sep 12 04:31:19.384906 (XEN) UNIT46 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.384967 (XEN) VCPU46: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.396894 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.396954 (XEN) GICH_LRs (vcpu 46) mask=0 Sep 12 04:31:19.396999 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.397039 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.397079 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.408891 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.408947 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.408989 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.409029 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.409069 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.409109 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.420910 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.420966 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.421009 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.421049 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.421090 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.421129 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.432899 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.432956 (XEN) No periodic timer Sep 12 04:31:19.432999 (XEN) UNIT47 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.433045 (XEN) VCPU47: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.444902 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.444960 (XEN) GICH_LRs (vcpu 47) mask=0 Sep 12 04:31:19.445004 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.445045 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.456904 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.456959 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.457001 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.457041 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.457082 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.457122 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.468909 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.468963 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.469005 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.469045 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.469085 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.480946 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.481003 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.481045 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.481085 (XEN) No periodic timer Sep 12 04:31:19.481127 (XEN) UNIT48 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.492936 (XEN) VCPU48: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.493000 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.504902 (XEN) GICH_LRs (vcpu 48) mask=0 Sep 12 04:31:19.504961 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.505004 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.505044 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.505083 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.505122 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.516852 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.516901 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.516937 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.516974 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.517012 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.517044 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.528898 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.528954 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.528995 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.529036 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.529076 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.529116 (XEN) No periodic timer Sep 12 04:31:19.540904 (XEN) UNIT49 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.540965 (XEN) VCPU49: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.552923 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.552983 (XEN) GICH_LRs (vcpu 49) mask=0 Sep 12 04:31:19.553028 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.553068 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.553107 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.564899 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.564956 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.564998 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.565038 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.565078 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.565117 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.576914 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.576969 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.577012 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.577052 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.577092 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.577131 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.588912 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.588968 (XEN) No periodic timer Sep 12 04:31:19.589011 (XEN) UNIT50 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.589057 (XEN) VCPU50: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.600905 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.600962 (XEN) GICH_LRs (vcpu 50) mask=0 Sep 12 04:31:19.601006 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.612888 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.612945 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.612986 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.613027 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.613067 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.624896 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.624953 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.624995 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.625036 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.625075 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.625115 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.636900 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.636957 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.636999 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.637040 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.637080 (XEN) No periodic timer Sep 12 04:31:19.637121 (XEN) UNIT51 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.648904 (XEN) VCPU51: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.648968 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.660895 (XEN) GICH_LRs (vcpu 51) mask=0 Sep 12 04:31:19.660953 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.660995 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.661035 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.661075 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.661115 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.672909 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.672964 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.673006 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.673046 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.673085 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.673125 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.684902 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.684957 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.685000 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.685040 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.685081 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.696895 (XEN) No periodic timer Sep 12 04:31:19.696953 (XEN) UNIT52 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.697001 (XEN) VCPU52: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.708900 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.708958 (XEN) GICH_LRs (vcpu 52) mask=0 Sep 12 04:31:19.709002 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.709043 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.709084 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.720901 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.720956 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.720997 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.721037 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.721077 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.721117 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.732902 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.732958 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.733000 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.733041 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.733081 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.733121 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.744891 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.744947 (XEN) No periodic timer Sep 12 04:31:19.745009 (XEN) UNIT53 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.756894 (XEN) VCPU53: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.756963 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.757021 (XEN) GICH_LRs (vcpu 53) mask=0 Sep 12 04:31:19.768898 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.768954 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.768995 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.769035 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.769075 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.769115 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.780896 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.780952 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.780994 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.781034 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.781074 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.781114 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.792911 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.792967 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.793009 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.793049 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.793089 (XEN) No periodic timer Sep 12 04:31:19.793130 (XEN) UNIT54 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.804905 (XEN) VCPU54: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.804969 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.816900 (XEN) GICH_LRs (vcpu 54) mask=0 Sep 12 04:31:19.816958 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.817000 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.817040 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.817080 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.828892 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.828949 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.828991 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.829032 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.829072 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.829112 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.840897 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.840955 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.840997 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.841037 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.841077 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.841117 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.852903 (XEN) No periodic timer Sep 12 04:31:19.852959 (XEN) UNIT55 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.853007 (XEN) VCPU55: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.864892 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.864950 (XEN) GICH_LRs (vcpu 55) mask=0 Sep 12 04:31:19.864994 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.865035 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.876899 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.876954 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.876996 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.877036 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.877076 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.877117 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.888911 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.888966 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.889008 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.889048 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.889088 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.889128 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.900901 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.900956 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.900998 (XEN) No periodic timer Sep 12 04:31:19.901039 (XEN) UNIT56 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.912943 (XEN) VCPU56: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.912986 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.913031 (XEN) GICH_LRs (vcpu 56) mask=0 Sep 12 04:31:19.924908 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.924964 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.925006 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.925046 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.925086 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.925126 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.936898 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.936953 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.936994 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.937035 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.937075 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.937115 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.948926 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.948979 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.949021 (XEN) VCPU_LR[14]=0 Sep 12 04:31:19.949061 (XEN) VCPU_LR[15]=0 Sep 12 04:31:19.949100 (XEN) No periodic timer Sep 12 04:31:19.949141 (XEN) UNIT57 affinities: hard={0-95} soft={0-95} Sep 12 04:31:19.960902 (XEN) VCPU57: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:19.960966 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:19.972912 (XEN) GICH_LRs (vcpu 57) mask=0 Sep 12 04:31:19.972970 (XEN) VCPU_LR[0]=0 Sep 12 04:31:19.973012 (XEN) VCPU_LR[1]=0 Sep 12 04:31:19.973052 (XEN) VCPU_LR[2]=0 Sep 12 04:31:19.973092 (XEN) VCPU_LR[3]=0 Sep 12 04:31:19.984900 (XEN) VCPU_LR[4]=0 Sep 12 04:31:19.984955 (XEN) VCPU_LR[5]=0 Sep 12 04:31:19.984997 (XEN) VCPU_LR[6]=0 Sep 12 04:31:19.985038 (XEN) VCPU_LR[7]=0 Sep 12 04:31:19.985078 (XEN) VCPU_LR[8]=0 Sep 12 04:31:19.985118 (XEN) VCPU_LR[9]=0 Sep 12 04:31:19.996890 (XEN) VCPU_LR[10]=0 Sep 12 04:31:19.996946 (XEN) VCPU_LR[11]=0 Sep 12 04:31:19.996988 (XEN) VCPU_LR[12]=0 Sep 12 04:31:19.997028 (XEN) VCPU_LR[13]=0 Sep 12 04:31:19.997067 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.008906 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.008963 (XEN) No periodic timer Sep 12 04:31:20.009006 (XEN) UNIT58 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.009052 (XEN) VCPU58: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.020898 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.020956 (XEN) GICH_LRs (vcpu 58) mask=0 Sep 12 04:31:20.021000 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.021041 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.032900 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.032955 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.032996 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.033036 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.033076 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.033116 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.044913 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.044968 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.045009 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.045050 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.045090 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.045129 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.056903 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.056960 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.057002 (XEN) No periodic timer Sep 12 04:31:20.057043 (XEN) UNIT59 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.068882 (XEN) VCPU59: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.068922 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.068947 (XEN) GICH_LRs (vcpu 59) mask=0 Sep 12 04:31:20.080907 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.080963 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.081005 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.081045 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.081085 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.081125 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.092903 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.092958 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.093000 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.093041 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.093081 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.093121 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.104903 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.104959 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.105000 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.105041 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.105082 (XEN) No periodic timer Sep 12 04:31:20.105122 (XEN) UNIT60 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.116907 (XEN) VCPU60: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.116971 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.128890 (XEN) GICH_LRs (vcpu 60) mask=0 Sep 12 04:31:20.128948 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.128990 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.129030 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.140901 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.140957 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.140998 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.141039 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.141097 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.141140 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.152903 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.152958 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.153000 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.153041 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.153081 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.153121 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.164890 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.164946 (XEN) No periodic timer Sep 12 04:31:20.164989 (XEN) UNIT61 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.165035 (XEN) VCPU61: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.176908 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.176966 (XEN) GICH_LRs (vcpu 61) mask=0 Sep 12 04:31:20.177010 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.188895 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.188951 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.188992 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.189032 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.189072 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.189112 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.200898 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.200954 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.200996 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.201037 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.201077 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.201118 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.212901 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.212957 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.213000 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.213040 (XEN) No periodic timer Sep 12 04:31:20.213081 (XEN) UNIT62 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.224906 (XEN) VCPU62: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.224970 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.225014 (XEN) GICH_LRs (vcpu 62) mask=0 Sep 12 04:31:20.236900 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.236956 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.236997 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.237038 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.237078 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.237118 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.248890 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.248946 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.248988 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.249027 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.249068 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.260899 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.260954 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.260996 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.261036 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.261076 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.261115 (XEN) No periodic timer Sep 12 04:31:20.272902 (XEN) UNIT63 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.272963 (XEN) VCPU63: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.284900 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.284959 (XEN) GICH_LRs (vcpu 63) mask=0 Sep 12 04:31:20.285003 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.285044 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.285085 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.296914 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.296969 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.297010 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.297051 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.297090 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.297130 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.308919 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.308997 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.309017 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.309085 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.309103 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.309138 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.320915 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.320971 (XEN) No periodic timer Sep 12 04:31:20.321014 (XEN) UNIT64 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.321087 (XEN) VCPU64: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.332927 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.332985 (XEN) GICH_LRs (vcpu 64) mask=0 Sep 12 04:31:20.333055 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.344906 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.344961 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.345022 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.345066 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.345106 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.345145 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.356901 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.356957 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.356999 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.357040 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.357080 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.357120 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.368932 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.368976 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.369003 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.369043 (XEN) No periodic timer Sep 12 04:31:20.369085 (XEN) UNIT65 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.380891 (XEN) VCPU65: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.380956 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.392966 (XEN) GICH_LRs (vcpu 65) mask=0 Sep 12 04:31:20.393032 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.393073 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.393090 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.393129 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.393169 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.404976 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.405034 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.405064 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.405094 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.405134 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.405173 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.416904 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.416959 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.417001 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.417041 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.417080 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.428899 (XEN) No periodic timer Sep 12 04:31:20.428955 (XEN) UNIT66 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.429002 (XEN) VCPU66: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.440901 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.440959 (XEN) GICH_LRs (vcpu 66) mask=0 Sep 12 04:31:20.441004 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.441044 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.441085 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.452899 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.452955 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.452996 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.453036 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.453076 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.453115 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.464910 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.464965 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.465007 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.465047 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.465086 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.465125 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.476900 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.476955 (XEN) No periodic timer Sep 12 04:31:20.476998 (XEN) UNIT67 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.477044 (XEN) VCPU67: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.488907 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.488965 (XEN) GICH_LRs (vcpu 67) mask=0 Sep 12 04:31:20.489009 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.500849 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.500904 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.500946 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.500986 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.501026 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.512901 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.512957 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.512998 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.513038 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.513078 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.513117 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.524900 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.524956 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.524998 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.525038 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.525079 (XEN) No periodic timer Sep 12 04:31:20.525120 (XEN) UNIT68 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.536905 (XEN) VCPU68: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.536968 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.548917 (XEN) GICH_LRs (vcpu 68) mask=0 Sep 12 04:31:20.548976 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.549019 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.549059 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.549098 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.560896 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.560953 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.560995 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.561035 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.561075 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.561115 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.572895 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.572951 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.572993 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.573034 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.573075 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.573115 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.584908 (XEN) No periodic timer Sep 12 04:31:20.584965 (XEN) UNIT69 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.585012 (XEN) VCPU69: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.596900 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.596958 (XEN) GICH_LRs (vcpu 69) mask=0 Sep 12 04:31:20.597002 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.597043 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.597083 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.608900 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.608955 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.608997 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.609036 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.609076 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.609116 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.620898 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.620953 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.620995 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.621035 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.621075 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.632884 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.632941 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.632983 (XEN) No periodic timer Sep 12 04:31:20.633024 (XEN) UNIT70 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.644901 (XEN) VCPU70: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.644965 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.645009 (XEN) GICH_LRs (vcpu 70) mask=0 Sep 12 04:31:20.656900 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.656955 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.656997 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.657037 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.657078 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.657117 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.668856 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.668912 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.668954 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.668994 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.669034 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.669074 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.680966 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.681021 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.681063 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.681104 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.681143 (XEN) No periodic timer Sep 12 04:31:20.681184 (XEN) UNIT71 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.692950 (XEN) VCPU71: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.693013 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.704961 (XEN) GICH_LRs (vcpu 71) mask=0 Sep 12 04:31:20.705018 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.705060 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.705099 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.705138 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.716945 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.717001 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.717043 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.717083 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.717122 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.717162 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.728942 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.728998 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.729040 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.729081 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.729120 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.729160 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.740945 (XEN) No periodic timer Sep 12 04:31:20.741019 (XEN) UNIT72 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.741070 (XEN) VCPU72: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.752947 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.753005 (XEN) GICH_LRs (vcpu 72) mask=0 Sep 12 04:31:20.753049 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.753089 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.764906 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.764963 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.765005 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.765045 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.765084 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.765124 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.776946 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.777001 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.777042 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.777083 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.777122 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.788954 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.789011 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.789053 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.789093 (XEN) No periodic timer Sep 12 04:31:20.789133 (XEN) UNIT73 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.800999 (XEN) VCPU73: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.801063 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.801108 (XEN) GICH_LRs (vcpu 73) mask=0 Sep 12 04:31:20.813004 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.813059 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.813101 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.813141 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.813181 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.813220 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.824980 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.825037 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.825079 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.825119 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.825159 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.825198 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.836914 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.836970 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.837011 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.837051 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.837091 (XEN) No periodic timer Sep 12 04:31:20.848910 (XEN) UNIT74 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.848979 (XEN) VCPU74: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.849047 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.860913 (XEN) GICH_LRs (vcpu 74) mask=0 Sep 12 04:31:20.860971 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.861028 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.861077 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.861108 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.872897 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.872952 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.872994 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.873035 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.873075 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.873115 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.884886 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.884941 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.884983 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.885023 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.885063 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.896908 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.896964 (XEN) No periodic timer Sep 12 04:31:20.897006 (XEN) UNIT75 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.897052 (XEN) VCPU75: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.908908 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.908966 (XEN) GICH_LRs (vcpu 75) mask=0 Sep 12 04:31:20.909010 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.920892 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.920948 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.920991 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.921031 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.921071 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.921111 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.932903 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.932959 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.933001 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.933041 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.933081 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.933140 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.944907 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.944963 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.945005 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.945045 (XEN) No periodic timer Sep 12 04:31:20.945086 (XEN) UNIT76 affinities: hard={0-95} soft={0-95} Sep 12 04:31:20.956905 (XEN) VCPU76: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:20.956969 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:20.957014 (XEN) GICH_LRs (vcpu 76) mask=0 Sep 12 04:31:20.968911 (XEN) VCPU_LR[0]=0 Sep 12 04:31:20.968967 (XEN) VCPU_LR[1]=0 Sep 12 04:31:20.969009 (XEN) VCPU_LR[2]=0 Sep 12 04:31:20.969048 (XEN) VCPU_LR[3]=0 Sep 12 04:31:20.969088 (XEN) VCPU_LR[4]=0 Sep 12 04:31:20.969127 (XEN) VCPU_LR[5]=0 Sep 12 04:31:20.980904 (XEN) VCPU_LR[6]=0 Sep 12 04:31:20.980959 (XEN) VCPU_LR[7]=0 Sep 12 04:31:20.981001 (XEN) VCPU_LR[8]=0 Sep 12 04:31:20.981041 (XEN) VCPU_LR[9]=0 Sep 12 04:31:20.981081 (XEN) VCPU_LR[10]=0 Sep 12 04:31:20.981121 (XEN) VCPU_LR[11]=0 Sep 12 04:31:20.992903 (XEN) VCPU_LR[12]=0 Sep 12 04:31:20.992958 (XEN) VCPU_LR[13]=0 Sep 12 04:31:20.992999 (XEN) VCPU_LR[14]=0 Sep 12 04:31:20.993040 (XEN) VCPU_LR[15]=0 Sep 12 04:31:20.993080 (XEN) No periodic timer Sep 12 04:31:21.004896 (XEN) UNIT77 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.004957 (XEN) VCPU77: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.005008 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.016904 (XEN) GICH_LRs (vcpu 77) mask=0 Sep 12 04:31:21.016961 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.017003 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.017043 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.028931 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.029003 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.029048 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.029084 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.029126 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.029161 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.040899 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.040954 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.040996 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.041036 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.041076 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.041116 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.052901 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.052958 (XEN) No periodic timer Sep 12 04:31:21.053001 (XEN) UNIT78 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.053048 (XEN) VCPU78: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.064906 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.064964 (XEN) GICH_LRs (vcpu 78) mask=0 Sep 12 04:31:21.065008 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.076906 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.076962 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.077004 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.077044 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.077084 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.077124 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.088899 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.088955 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.088997 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.089037 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.089077 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.089116 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.100901 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.100956 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.100999 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.101039 (XEN) No periodic timer Sep 12 04:31:21.101080 (XEN) UNIT79 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.112900 (XEN) VCPU79: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.112964 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.113008 (XEN) GICH_LRs (vcpu 79) mask=0 Sep 12 04:31:21.124904 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.124960 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.125001 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.125041 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.125081 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.136887 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.136943 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.136985 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.137044 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.137087 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.137127 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.148900 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.148955 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.148996 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.149036 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.149076 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.160896 (XEN) No periodic timer Sep 12 04:31:21.160952 (XEN) UNIT80 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.160999 (XEN) VCPU80: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.172895 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.172953 (XEN) GICH_LRs (vcpu 80) mask=0 Sep 12 04:31:21.172998 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.173038 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.173078 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.184914 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.184969 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.185010 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.185050 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.185090 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.185130 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.196902 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.196957 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.196999 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.197040 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.197080 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.197120 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.208901 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.208956 (XEN) No periodic timer Sep 12 04:31:21.208998 (XEN) UNIT81 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.209044 (XEN) VCPU81: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.220904 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.220961 (XEN) GICH_LRs (vcpu 81) mask=0 Sep 12 04:31:21.221006 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.232899 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.232955 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.232996 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.233037 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.233077 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.233116 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.244898 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.244953 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.244995 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.245035 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.245076 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.245116 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.256912 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.256967 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.257008 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.257048 (XEN) No periodic timer Sep 12 04:31:21.257089 (XEN) UNIT82 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.268892 (XEN) VCPU82: CPU67 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.268955 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.280898 (XEN) GICH_LRs (vcpu 82) mask=0 Sep 12 04:31:21.280956 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.280998 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.281039 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.281078 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.292933 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.292989 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.293031 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.293072 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.293112 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.293151 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.304900 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.304932 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.304955 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.304977 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.304998 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.305020 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.316899 (XEN) No periodic timer Sep 12 04:31:21.316955 (XEN) UNIT83 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.317003 (XEN) VCPU83: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.328912 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.328970 (XEN) GICH_LRs (vcpu 83) mask=0 Sep 12 04:31:21.329014 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.329055 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.329095 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.340919 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.340974 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.341016 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.341055 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.341095 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.341133 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.352901 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.352957 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.352998 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.353038 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.353079 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.364902 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.364958 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.365000 (XEN) No periodic timer Sep 12 04:31:21.365041 (XEN) UNIT84 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.365088 (XEN) VCPU84: CPU6 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.376908 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.376965 (XEN) GICH_LRs (vcpu 84) mask=0 Sep 12 04:31:21.377009 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.388895 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.388951 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.388993 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.389033 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.389072 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.389112 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.400896 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.400951 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.400992 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.401032 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.401073 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.412930 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.441662 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.441798 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.441860 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.441883 (XEN) No periodic timer Sep 12 04:31:21.441906 (XEN) UNIT85 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.442045 (XEN) VCPU85: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.442096 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.442139 (XEN) GICH_LRs (vcpu 85) mask=0 Sep 12 04:31:21.442182 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.442221 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.442261 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.442301 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.448907 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.448963 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.449005 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.449045 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.449086 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.460917 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.460972 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.461014 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.461055 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.461096 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.461136 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.472939 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.472995 (XEN) No periodic timer Sep 12 04:31:21.473037 (XEN) UNIT86 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.473084 (XEN) VCPU86: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.484929 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.484987 (XEN) GICH_LRs (vcpu 86) mask=0 Sep 12 04:31:21.485032 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.496927 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.496983 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.497032 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.497073 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.497114 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.497154 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.508926 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.508982 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.509024 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.509065 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.509105 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.509145 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.520913 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.520969 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.521012 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.521053 (XEN) No periodic timer Sep 12 04:31:21.521094 (XEN) UNIT87 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.532920 (XEN) VCPU87: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.532985 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.544977 (XEN) GICH_LRs (vcpu 87) mask=0 Sep 12 04:31:21.545039 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.545082 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.545123 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.545162 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.556915 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.556971 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.557014 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.557055 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.557095 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.557135 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.568915 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.568971 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.569013 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.569054 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.569095 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.569135 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.580944 (XEN) No periodic timer Sep 12 04:31:21.581002 (XEN) UNIT88 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.581050 (XEN) VCPU88: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.592920 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.592978 (XEN) GICH_LRs (vcpu 88) mask=0 Sep 12 04:31:21.593023 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.593064 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.593105 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.604917 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.604972 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.605014 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.605056 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.605095 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.605136 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.616893 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.616949 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.616991 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.617035 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.617075 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.628915 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.628973 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.629015 (XEN) No periodic timer Sep 12 04:31:21.629058 (XEN) UNIT89 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.629104 (XEN) VCPU89: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.640928 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.640986 (XEN) GICH_LRs (vcpu 89) mask=0 Sep 12 04:31:21.641031 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.652908 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.652964 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.653006 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.653046 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.653087 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.664932 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.664994 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.665037 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.665077 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.665118 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.665158 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.676919 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.676975 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.677018 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.677058 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.677100 (XEN) No periodic timer Sep 12 04:31:21.677141 (XEN) UNIT90 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.688931 (XEN) VCPU90: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.688995 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.700914 (XEN) GICH_LRs (vcpu 90) mask=0 Sep 12 04:31:21.700972 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.701015 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.701055 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.701096 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.712919 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.712975 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.713017 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.713058 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.713098 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.713138 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.724921 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.724977 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.725020 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.725061 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.725101 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.725142 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.736917 (XEN) No periodic timer Sep 12 04:31:21.736992 (XEN) UNIT91 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.737043 (XEN) VCPU91: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.748920 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.748978 (XEN) GICH_LRs (vcpu 91) mask=0 Sep 12 04:31:21.749023 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.749064 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.760916 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.760972 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.761015 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.761055 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.761096 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.761136 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.772916 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.772973 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.773015 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.773055 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.773096 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.773136 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.784908 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.784964 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.785006 (XEN) No periodic timer Sep 12 04:31:21.785048 (XEN) UNIT92 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.796926 (XEN) VCPU92: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.796990 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.797035 (XEN) GICH_LRs (vcpu 92) mask=0 Sep 12 04:31:21.808920 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.808976 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.809018 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.809059 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.809098 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.809139 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.820913 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.820969 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.821012 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.821051 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.821092 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.821132 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.832934 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.832990 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.833032 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.833074 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.833114 (XEN) No periodic timer Sep 12 04:31:21.844911 (XEN) UNIT93 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.844980 (XEN) VCPU93: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.845031 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.856924 (XEN) GICH_LRs (vcpu 93) mask=0 Sep 12 04:31:21.856982 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.857025 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.857065 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.857106 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.868921 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.868977 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.869018 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.869058 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.869099 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.869139 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.880914 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.880969 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.881011 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.881053 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.881093 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.881133 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.892927 (XEN) No periodic timer Sep 12 04:31:21.892983 (XEN) UNIT94 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.893031 (XEN) VCPU94: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.904914 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.904972 (XEN) GICH_LRs (vcpu 94) mask=0 Sep 12 04:31:21.905017 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.916911 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.916967 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.917009 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.917049 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.917089 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.917129 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.928933 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.928989 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.929030 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.929070 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.929110 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.929150 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.940943 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.941000 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.941043 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.941083 (XEN) No periodic timer Sep 12 04:31:21.941124 (XEN) UNIT95 affinities: hard={0-95} soft={0-95} Sep 12 04:31:21.952922 (XEN) VCPU95: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 12 04:31:21.952987 (XEN) pause_count=0 pause_flags=1 Sep 12 04:31:21.953032 (XEN) GICH_LRs (vcpu 95) mask=0 Sep 12 04:31:21.964930 (XEN) VCPU_LR[0]=0 Sep 12 04:31:21.964986 (XEN) VCPU_LR[1]=0 Sep 12 04:31:21.965027 (XEN) VCPU_LR[2]=0 Sep 12 04:31:21.965067 (XEN) VCPU_LR[3]=0 Sep 12 04:31:21.965107 (XEN) VCPU_LR[4]=0 Sep 12 04:31:21.965147 (XEN) VCPU_LR[5]=0 Sep 12 04:31:21.976927 (XEN) VCPU_LR[6]=0 Sep 12 04:31:21.976982 (XEN) VCPU_LR[7]=0 Sep 12 04:31:21.977023 (XEN) VCPU_LR[8]=0 Sep 12 04:31:21.977063 (XEN) VCPU_LR[9]=0 Sep 12 04:31:21.977102 (XEN) VCPU_LR[10]=0 Sep 12 04:31:21.977142 (XEN) VCPU_LR[11]=0 Sep 12 04:31:21.988922 (XEN) VCPU_LR[12]=0 Sep 12 04:31:21.988977 (XEN) VCPU_LR[13]=0 Sep 12 04:31:21.989019 (XEN) VCPU_LR[14]=0 Sep 12 04:31:21.989059 (XEN) VCPU_LR[15]=0 Sep 12 04:31:21.989099 (XEN) No periodic timer Sep 12 04:31:22.000920 (XEN) Notifying guest 0:0 (virq 1, port 0) Sep 12 04:31:22.000979 (XEN) Notifying guest 0:1 (virq 1, port 0) Sep 12 04:31:22.001024 (XEN) Notifying guest 0:2 (virq 1, port 0) Sep 12 04:31:22.001068 (XEN) Notifying guest 0:3 (virq 1, port 0) Sep 12 04:31:22.012928 (XEN) Notifying guest 0:4 (virq 1, port 0) Sep 12 04:31:22.012986 (XEN) Notifying guest 0:5 (virq 1, port 0) Sep 12 04:31:22.013031 (XEN) Notifying guest 0:6 (virq 1, port 0) Sep 12 04:31:22.024925 (XEN) Notifying guest 0:7 (virq 1, port 0) Sep 12 04:31:22.024984 (XEN) Notifying guest 0:8 (virq 1, port 0) Sep 12 04:31:22.025029 (XEN) Notifying guest 0:9 (virq 1, port 0) Sep 12 04:31:22.036917 (XEN) Notifying guest 0:10 (virq 1, port 0) Sep 12 04:31:22.036976 (XEN) Notifying guest 0:11 (virq 1, port 0) Sep 12 04:31:22.048915 (XEN) Notifying guest 0:12 (virq 1, port 0) Sep 12 04:31:22.048975 (XEN) Notifying guest 0:13 (virq 1, port 0) Sep 12 04:31:22.049021 (XEN) Notifying guest 0:14 (virq 1, port 0) Sep 12 04:31:22.049065 (XEN) Notifying guest 0:15 (virq 1, port 0) Sep 12 04:31:22.060925 (XEN) Notifying guest 0:16 (virq 1, port 0) Sep 12 04:31:22.060984 (XEN) Notifying guest 0:17 (virq 1, port 0) Sep 12 04:31:22.061029 (XEN) Notifying guest 0:18 (virq 1, port 0) Sep 12 04:31:22.072942 (XEN) Notifying guest 0:19 (virq 1, port 0) Sep 12 04:31:22.073002 (XEN) Notifying guest 0:20 (virq 1, port 0) Sep 12 04:31:22.073048 (XEN) Notifying guest 0:21 (virq 1, port 0) Sep 12 04:31:22.084934 (XEN) Notifying guest 0:22 (virq 1, port 0) Sep 12 04:31:22.084993 (XEN) Notifying guest 0:23 (virq 1, port 0) Sep 12 04:31:22.085038 (XEN) Notifying guest 0:24 (virq 1, port 0) Sep 12 04:31:22.096925 (XEN) Notifying guest 0:25 (virq 1, port 0) Sep 12 04:31:22.096984 (XEN) Notifying guest 0:26 (virq 1, port 0) Sep 12 04:31:22.097029 (XEN) Notifying guest 0:27 (virq 1, port 0) Sep 12 04:31:22.108922 (XEN) Notifying guest 0:28 (virq 1, port 0) Sep 12 04:31:22.108981 (XEN) Notifying guest 0:29 (virq 1, port 0) Sep 12 04:31:22.109026 (XEN) Notifying guest 0:30 (virq 1, port 0) Sep 12 04:31:22.120920 (XEN) Notifying guest 0:31 (virq 1, port 0) Sep 12 04:31:22.120980 (XEN) Notifying guest 0:32 (virq 1, port 0) Sep 12 04:31:22.121024 (XEN) Notifying guest 0:33 (virq 1, port 0) Sep 12 04:31:22.132923 (XEN) Notifying guest 0:34 (virq 1, port 0) Sep 12 04:31:22.132981 (XEN) Notifying guest 0:35 (virq 1, port 0) Sep 12 04:31:22.133026 (XEN) Notifying guest 0:36 (virq 1, port 0) Sep 12 04:31:22.144923 (XEN) Notifying guest 0:37 (virq 1, port 0) Sep 12 04:31:22.144981 (XEN) Notifying guest 0:38 (virq 1, port 0) Sep 12 04:31:22.145027 (XEN) Notifying guest 0:39 (virq 1, port 0) Sep 12 04:31:22.156910 (XEN) Notifying guest 0:40 (virq 1, port 0) Sep 12 04:31:22.156969 (XEN) Notifying guest 0:41 (virq 1, port 0) Sep 12 04:31:22.157036 (XEN) Notifying guest 0:42 (virq 1, port 0) Sep 12 04:31:22.168918 (XEN) Notifying guest 0:43 (virq 1, port 0) Sep 12 04:31:22.168977 (XEN) Notifying guest 0:44 (virq 1, port 0) Sep 12 04:31:22.169022 (XEN) Notifying guest 0:45 (virq 1, port 0) Sep 12 04:31:22.180915 (XEN) Notifying guest 0:46 (virq 1, port 0) Sep 12 04:31:22.180974 (XEN) Notifying guest 0:47 (virq 1, port 0) Sep 12 04:31:22.181019 (XEN) Notifying guest 0:48 (virq 1, port 0) Sep 12 04:31:22.192931 (XEN) Notifying guest 0:49 (virq 1, port 0) Sep 12 04:31:22.192989 (XEN) Notifying guest 0:50 (virq 1, port 0) Sep 12 04:31:22.193034 (XEN) Notifying guest 0:51 (virq 1, port 0) Sep 12 04:31:22.204914 (XEN) Notifying guest 0:52 (virq 1, port 0) Sep 12 04:31:22.204973 (XEN) Notifying guest 0:53 (virq 1, port 0) Sep 12 04:31:22.205018 (XEN) Notifying guest 0:54 (virq 1, port 0) Sep 12 04:31:22.216922 (XEN) Notifying guest 0:55 (virq 1, port 0) Sep 12 04:31:22.216982 (XEN) Notifying guest 0:56 (virq 1, port 0) Sep 12 04:31:22.217027 (XEN) Notifying guest 0:57 (virq 1, port 0) Sep 12 04:31:22.228921 (XEN) Notifying guest 0:58 (virq 1, port 0) Sep 12 04:31:22.228980 (XEN) Notifying guest 0:59 (virq 1, port 0) Sep 12 04:31:22.229026 (XEN) Notifying guest 0:60 (virq 1, port 0) Sep 12 04:31:22.240919 (XEN) Notifying guest 0:61 (virq 1, port 0) Sep 12 04:31:22.240979 (XEN) Notifying guest 0:62 (virq 1, port 0) Sep 12 04:31:22.241024 (XEN) Notifying guest 0:63 (virq 1, port 0) Sep 12 04:31:22.252918 (XEN) Notifying guest 0:64 (virq 1, port 0) Sep 12 04:31:22.252977 (XEN) Notifying guest 0:65 (virq 1, port 0) Sep 12 04:31:22.253022 (XEN) Notifying guest 0:66 (virq 1, port 0) Sep 12 04:31:22.264915 (XEN) Notifying guest 0:67 (virq 1, port 0) Sep 12 04:31:22.264974 (XEN) Notifying guest 0:68 (virq 1, port 0) Sep 12 04:31:22.265020 (XEN) Notifying guest 0:69 (virq 1, port 0) Sep 12 04:31:22.276917 (XEN) Notifying guest 0:70 (virq 1, port 0) Sep 12 04:31:22.276977 (XEN) Notifying guest 0:71 (virq 1, port 0) Sep 12 04:31:22.277022 (XEN) Notifying guest 0:72 (virq 1, port 0) Sep 12 04:31:22.288919 (XEN) Notifying guest 0:73 (virq 1, port 0) Sep 12 04:31:22.288988 (XEN) Notifying guest 0:74 (virq 1, port 0) Sep 12 04:31:22.289035 (XEN) Notifying guest 0:75 (virq 1, port 0) Sep 12 04:31:22.300923 (XEN) Notifying guest 0:76 (virq 1, port 0) Sep 12 04:31:22.300983 (XEN) Notifying guest 0:77 (virq 1, port 0) Sep 12 04:31:22.301028 (XEN) Notifying guest 0:78 (virq 1, port 0) Sep 12 04:31:22.312921 (XEN) Notifying guest 0:79 (virq 1, port 0) Sep 12 04:31:22.312980 (XEN) Notifying guest 0:80 (virq 1, port 0) Sep 12 04:31:22.313026 (XEN) Notifying guest 0:81 (virq 1, port 0) Sep 12 04:31:22.324904 (XEN) Notifying guest 0:82 (virq 1, port 0) Sep 12 04:31:22.324963 (XEN) Notifying guest 0:83 (virq 1, port 0) Sep 12 04:31:22.325009 (XEN) Notifying guest 0:84 (virq 1, port 0) Sep 12 04:31:22.336929 (XEN) Notifying guest 0:85 (virq 1, port 0) Sep 12 04:31:22.336988 (XEN) Notifying guest 0:86 (virq 1, port 0) Sep 12 04:31:22.337033 (XEN) Notifying guest 0:87 (virq 1, port 0) Sep 12 04:31:22.348913 (XEN) Notifying guest 0:88 (virq 1, port 0) Sep 12 04:31:22.348973 (XEN) Notifying guest 0:89 (virq 1, port 0) Sep 12 04:31:22.349018 (XEN) Notifying guest 0:90 (virq 1, port 0) Sep 12 04:31:22.360881 (XEN) Notifying guest 0:91 (virq 1, port 0) Sep 12 04:31:22.360941 (XEN) Notifying guest 0:92 (virq 1, port 0) Sep 12 04:31:22.360987 (XEN) Notifying guest 0:93 (virq 1, port 0) Sep 12 04:31:22.372887 (XEN) Notifying guest 0:94 (virq 1, port 0) Sep 12 04:31:22.372948 (XEN) Notifying guest 0:95 (virq 1, port 0) Sep 12 04:31:22.372995 Sep 12 04:31:28.622550 (XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input) Sep 12 04:31:28.643546 Sep 12 04:31:28.644858