Sep 15 01:45:07.750789 (XEN) VCPU_LR[1]=0 Sep 15 01:45:07.750962 (XEN) VCPU_LR[2]=0 Sep 15 01:45:07.760792 (XEN) VCPU_LR[3]=0 Sep 15 01:45:07.760823 (XEN) VCPU_LR[4]=0 Sep 15 01:45:07.760848 (XEN) VCPU_LR[5]=0 Sep 15 01:45:07.760883 (XEN) VCPU_LR[6]=0 Sep 15 01:45:07.760906 (XEN) VCPU_LR[7]=0 Sep 15 01:45:07.760928 (XEN) VCPU_LR[8]=0 Sep 15 01:45:07.772776 (XEN) VCPU_LR[9]=0 Sep 15 01:45:07.772802 (XEN) VCPU_LR[10]=0 Sep 15 01:45:07.772835 (XEN) VCPU_LR[11]=0 Sep 15 01:45:07.772860 (XEN) VCPU_LR[12]=0 Sep 15 01:45:07.772882 (XEN) VCPU_LR[13]=0 Sep 15 01:45:07.784759 (XEN) VCPU_LR[14]=0 Sep 15 01:45:07.784786 (XEN) VCPU_LR[15]=0 Sep 15 01:45:07.784818 (XEN) No periodic timer Sep 15 01:45:07.784841 (XEN) UNIT6 affinities: hard={0-95} soft={0-95} Sep 15 01:45:07.784866 (XEN) VCPU6: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:07.796762 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:07.796791 (XEN) GICH_LRs (vcpu 6) mask=0 Sep 15 01:45:07.796825 (XEN) VCPU_LR[0]=0 Sep 15 01:45:07.808759 (XEN) VCPU_LR[1]=0 Sep 15 01:45:07.808785 (XEN) VCPU_LR[2]=0 Sep 15 01:45:07.808807 (XEN) VCPU_LR[3]=0 Sep 15 01:45:07.808829 (XEN) VCPU_LR[4]=0 Sep 15 01:45:07.808862 (XEN) VCPU_LR[5]=0 Sep 15 01:45:07.820749 (XEN) VCPU_LR[6]=0 Sep 15 01:45:07.820776 (XEN) VCPU_LR[7]=0 Sep 15 01:45:07.820799 (XEN) VCPU_LR[8]=0 Sep 15 01:45:07.820823 (XEN) VCPU_LR[9]=0 Sep 15 01:45:07.820854 (XEN) VCPU_LR[10]=0 Sep 15 01:45:07.820877 (XEN) VCPU_LR[11]=0 Sep 15 01:45:07.832747 (XEN) VCPU_LR[12]=0 Sep 15 01:45:07.832772 (XEN) VCPU_LR[13]=0 Sep 15 01:45:07.832794 (XEN) VCPU_LR[14]=0 Sep 15 01:45:07.832825 (XEN) VCPU_LR[15]=0 Sep 15 01:45:07.832848 (XEN) No periodic timer Sep 15 01:45:07.832869 (XEN) UNIT7 affinities: hard={0-95} soft={0-95} Sep 15 01:45:07.844718 (XEN) VCPU7: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:07.844747 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:07.856753 (XEN) GICH_LRs (vcpu 7) mask=0 Sep 15 01:45:07.856779 (XEN) VCPU_LR[0]=0 Sep 15 01:45:07.856804 (XEN) VCPU_LR[1]=0 Sep 15 01:45:07.856826 (XEN) VCPU_LR[2]=0 Sep 15 01:45:07.856848 (XEN) VCPU_LR[3]=0 Sep 15 01:45:07.868756 (XEN) VCPU_LR[4]=0 Sep 15 01:45:07.868791 (XEN) VCPU_LR[5]=0 Sep 15 01:45:07.868814 (XEN) VCPU_LR[6]=0 Sep 15 01:45:07.868836 (XEN) VCPU_LR[7]=0 Sep 15 01:45:07.868857 (XEN) VCPU_LR[8]=0 Sep 15 01:45:07.868878 (XEN) VCPU_LR[9]=0 Sep 15 01:45:07.880749 (XEN) VCPU_LR[10]=0 Sep 15 01:45:07.880775 (XEN) VCPU_LR[11]=0 Sep 15 01:45:07.880800 (XEN) VCPU_LR[12]=0 Sep 15 01:45:07.880823 (XEN) VCPU_LR[13]=0 Sep 15 01:45:07.880845 (XEN) VCPU_LR[14]=0 Sep 15 01:45:07.880877 (XEN) VCPU_LR[15]=0 Sep 15 01:45:07.892755 (XEN) No periodic timer Sep 15 01:45:07.892781 (XEN) UNIT8 affinities: hard={0-95} soft={0-95} Sep 15 01:45:07.892806 (XEN) VCPU8: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:07.904765 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:07.904804 (XEN) GICH_LRs (vcpu 8) mask=0 Sep 15 01:45:07.904829 (XEN) VCPU_LR[0]=0 Sep 15 01:45:07.904853 (XEN) VCPU_LR[1]=0 Sep 15 01:45:07.904875 (XEN) VCPU_LR[2]=0 Sep 15 01:45:07.916704 (XEN) VCPU_LR[3]=0 Sep 15 01:45:07.916738 (XEN) VCPU_LR[4]=0 Sep 15 01:45:07.916761 (XEN) VCPU_LR[5]=0 Sep 15 01:45:07.916782 (XEN) VCPU_LR[6]=0 Sep 15 01:45:07.916804 (XEN) VCPU_LR[7]=0 Sep 15 01:45:07.916826 (XEN) VCPU_LR[8]=0 Sep 15 01:45:07.928770 (XEN) VCPU_LR[9]=0 Sep 15 01:45:07.928800 (XEN) VCPU_LR[10]=0 Sep 15 01:45:07.928825 (XEN) VCPU_LR[11]=0 Sep 15 01:45:07.928847 (XEN) VCPU_LR[12]=0 Sep 15 01:45:07.928869 (XEN) VCPU_LR[13]=0 Sep 15 01:45:07.940710 (XEN) VCPU_LR[14]=0 Sep 15 01:45:07.940736 (XEN) VCPU_LR[15]=0 Sep 15 01:45:07.940758 (XEN) No periodic timer Sep 15 01:45:07.940781 (XEN) UNIT9 affinities: hard={0-95} soft={0-95} Sep 15 01:45:07.952753 (XEN) VCPU9: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:07.952803 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:07.952833 (XEN) GICH_LRs (vcpu 9) mask=0 Sep 15 01:45:07.964830 (XEN) VCPU_LR[0]=0 Sep 15 01:45:07.964889 (XEN) VCPU_LR[1]=0 Sep 15 01:45:07.964933 (XEN) VCPU_LR[2]=0 Sep 15 01:45:07.964998 (XEN) VCPU_LR[3]=0 Sep 15 01:45:07.965041 (XEN) VCPU_LR[4]=0 Sep 15 01:45:07.965085 (XEN) VCPU_LR[5]=0 Sep 15 01:45:07.976818 (XEN) VCPU_LR[6]=0 Sep 15 01:45:07.976869 (XEN) VCPU_LR[7]=0 Sep 15 01:45:07.976930 (XEN) VCPU_LR[8]=0 Sep 15 01:45:07.976971 (XEN) VCPU_LR[9]=0 Sep 15 01:45:07.977016 (XEN) VCPU_LR[10]=0 Sep 15 01:45:07.977072 (XEN) VCPU_LR[11]=0 Sep 15 01:45:07.988764 (XEN) VCPU_LR[12]=0 Sep 15 01:45:07.988790 (XEN) VCPU_LR[13]=0 Sep 15 01:45:07.988812 (XEN) VCPU_LR[14]=0 Sep 15 01:45:07.988835 (XEN) VCPU_LR[15]=0 Sep 15 01:45:07.988870 (XEN) No periodic timer Sep 15 01:45:07.988894 (XEN) UNIT10 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.000815 (XEN) VCPU10: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.000874 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.012731 (XEN) GICH_LRs (vcpu 10) mask=0 Sep 15 01:45:08.012768 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.012791 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.012813 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.012834 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.012856 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.024803 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.024852 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.024893 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.024933 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.024973 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.025030 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.036819 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.036874 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.036916 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.036956 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.037019 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.048791 (XEN) No periodic timer Sep 15 01:45:08.048839 (XEN) UNIT11 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.048886 (XEN) VCPU11: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.060775 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.060844 (XEN) GICH_LRs (vcpu 11) mask=0 Sep 15 01:45:08.060892 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.060933 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.072804 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.072850 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.072908 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.072949 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.072989 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.073028 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.084784 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.084848 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.084895 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.084936 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.084976 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.085020 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.096775 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.096836 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.096878 (XEN) No periodic timer Sep 15 01:45:08.096920 (XEN) UNIT12 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.108806 (XEN) VCPU12: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.108879 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.108924 (XEN) GICH_LRs (vcpu 12) mask=0 Sep 15 01:45:08.120836 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.120893 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.120936 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.120999 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.121042 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.121081 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.132825 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.132885 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.132950 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.132996 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.133038 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.133078 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.144775 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.144858 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.144899 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.144944 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.145004 (XEN) No periodic timer Sep 15 01:45:08.145049 (XEN) UNIT13 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.156800 (XEN) VCPU13: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.156855 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.168790 (XEN) GICH_LRs (vcpu 13) mask=0 Sep 15 01:45:08.168842 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.168884 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.168924 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.168981 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.180771 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.180822 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.180863 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.180903 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.180964 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.192831 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.192889 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.192932 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.192972 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.193034 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.193076 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.204832 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.204890 (XEN) No periodic timer Sep 15 01:45:08.204933 (XEN) UNIT14 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.205001 (XEN) VCPU14: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.216842 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.216900 (XEN) GICH_LRs (vcpu 14) mask=0 Sep 15 01:45:08.216945 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.216985 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.228808 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.228838 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.228860 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.228882 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.228904 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.228938 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.240756 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.240789 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.240812 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.240834 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.240856 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.240880 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.252735 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.252761 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.252784 (XEN) No periodic timer Sep 15 01:45:08.252809 (XEN) UNIT15 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.264784 (XEN) VCPU15: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.264843 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.264888 (XEN) GICH_LRs (vcpu 15) mask=0 Sep 15 01:45:08.276768 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.276814 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.276859 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.276900 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.276944 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.276985 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.288772 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.288832 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.288872 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.288916 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.288957 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.288997 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.300785 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.300831 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.300872 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.300912 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.300958 (XEN) No periodic timer Sep 15 01:45:08.300999 (XEN) UNIT16 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.312795 (XEN) VCPU16: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.324766 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.324833 (XEN) GICH_LRs (vcpu 16) mask=0 Sep 15 01:45:08.324878 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.324919 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.324959 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.336784 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.336847 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.336888 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.336929 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.336969 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.337008 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.348770 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.348834 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.348893 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.348941 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.348982 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.349022 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.360787 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.360833 (XEN) No periodic timer Sep 15 01:45:08.360874 (XEN) UNIT17 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.360918 (XEN) VCPU17: CPU72 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.372786 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.372838 (XEN) GICH_LRs (vcpu 17) mask=0 Sep 15 01:45:08.372882 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.372922 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.384784 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.384835 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.384876 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.384916 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.384956 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.384999 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.396785 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.396831 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.396872 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.396912 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.396957 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.408782 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.408832 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.408873 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.408915 (XEN) No periodic timer Sep 15 01:45:08.408958 (XEN) UNIT18 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.420799 (XEN) VCPU18: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.420856 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.420900 (XEN) GICH_LRs (vcpu 18) mask=0 Sep 15 01:45:08.432784 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.432833 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.432874 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.432914 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.432955 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.432998 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.444794 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.444843 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.444884 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.444929 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.444969 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.456763 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.456821 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.456867 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.456907 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.456950 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.456991 (XEN) No periodic timer Sep 15 01:45:08.468791 (XEN) UNIT19 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.468842 (XEN) VCPU19: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.480734 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.480761 (XEN) GICH_LRs (vcpu 19) mask=0 Sep 15 01:45:08.480784 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.480806 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.480828 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.492766 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.492794 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.492817 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.492839 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.492860 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.492882 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.504780 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.504826 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.504871 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.504911 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.504951 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.504990 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.516787 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.516835 (XEN) No periodic timer Sep 15 01:45:08.516878 (XEN) UNIT20 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.516924 (XEN) VCPU20: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.528808 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.528857 (XEN) GICH_LRs (vcpu 20) mask=0 Sep 15 01:45:08.528900 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.540797 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.540849 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.540891 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.540930 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.540975 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.541017 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.552799 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.552850 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.552892 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.552933 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.552972 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.553011 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.564772 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.564818 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.564858 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.564902 (XEN) No periodic timer Sep 15 01:45:08.564943 (XEN) UNIT21 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.576790 (XEN) VCPU21: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.576843 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.588768 (XEN) GICH_LRs (vcpu 21) mask=0 Sep 15 01:45:08.588794 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.588816 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.588838 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.588860 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.588884 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.600787 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.600833 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.600874 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.600913 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.600952 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.600996 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.612792 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.612839 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.612880 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.612922 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.612964 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.624784 (XEN) No periodic timer Sep 15 01:45:08.624811 (XEN) UNIT22 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.624835 (XEN) VCPU22: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.636762 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.636793 (XEN) GICH_LRs (vcpu 22) mask=0 Sep 15 01:45:08.636817 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.636840 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.636861 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.648761 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.648792 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.648817 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.648839 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.648860 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.648882 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.660735 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.660763 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.660786 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.660808 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.660829 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.660854 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.672784 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.672831 (XEN) No periodic timer Sep 15 01:45:08.672873 (XEN) UNIT23 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.672919 (XEN) VCPU23: CPU34 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.684822 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.684873 (XEN) GICH_LRs (vcpu 23) mask=0 Sep 15 01:45:08.684916 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.696823 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.696879 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.696921 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.696961 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.697001 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.708834 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.708890 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.708932 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.708972 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.709012 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.709053 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.720836 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.720893 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.720935 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.720975 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.721015 (XEN) No periodic timer Sep 15 01:45:08.721056 (XEN) UNIT24 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.732810 (XEN) VCPU24: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.732844 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.744827 (XEN) GICH_LRs (vcpu 24) mask=0 Sep 15 01:45:08.744885 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.744928 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.744990 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.745034 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.745078 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.756799 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.756846 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.756890 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.756932 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.756972 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.757011 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.768842 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.768898 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.768940 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.768980 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.769019 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.780831 (XEN) No periodic timer Sep 15 01:45:08.780887 (XEN) UNIT25 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.780935 (XEN) VCPU25: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.792835 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.792894 (XEN) GICH_LRs (vcpu 25) mask=0 Sep 15 01:45:08.792938 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.792979 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.793019 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.804836 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.804892 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.804934 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.804974 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.805013 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.805052 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.816829 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.816884 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.816926 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.816966 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.817006 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.828837 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.828892 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.828934 (XEN) No periodic timer Sep 15 01:45:08.828976 (XEN) UNIT26 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.840839 (XEN) VCPU26: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.840903 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.840948 (XEN) GICH_LRs (vcpu 26) mask=0 Sep 15 01:45:08.852835 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.852891 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.852933 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.852973 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.853013 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.853053 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.864832 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.864888 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.864930 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.864970 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.865010 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.865049 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.876839 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.876894 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.876936 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.876977 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.877017 (XEN) No periodic timer Sep 15 01:45:08.877058 (XEN) UNIT27 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.888837 (XEN) VCPU27: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.888901 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.900840 (XEN) GICH_LRs (vcpu 27) mask=0 Sep 15 01:45:08.900898 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.900940 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.900979 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.901018 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.912828 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.912884 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.912926 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.912966 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.913006 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.913045 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.924829 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.924886 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.924928 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.924969 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.925008 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.925047 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.936836 (XEN) No periodic timer Sep 15 01:45:08.936893 (XEN) UNIT28 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.936941 (XEN) VCPU28: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.948834 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.948897 (XEN) GICH_LRs (vcpu 28) mask=0 Sep 15 01:45:08.948943 (XEN) VCPU_LR[0]=0 Sep 15 01:45:08.948984 (XEN) VCPU_LR[1]=0 Sep 15 01:45:08.960816 (XEN) VCPU_LR[2]=0 Sep 15 01:45:08.960865 (XEN) VCPU_LR[3]=0 Sep 15 01:45:08.960906 (XEN) VCPU_LR[4]=0 Sep 15 01:45:08.960946 (XEN) VCPU_LR[5]=0 Sep 15 01:45:08.960990 (XEN) VCPU_LR[6]=0 Sep 15 01:45:08.961032 (XEN) VCPU_LR[7]=0 Sep 15 01:45:08.972773 (XEN) VCPU_LR[8]=0 Sep 15 01:45:08.972798 (XEN) VCPU_LR[9]=0 Sep 15 01:45:08.972820 (XEN) VCPU_LR[10]=0 Sep 15 01:45:08.972842 (XEN) VCPU_LR[11]=0 Sep 15 01:45:08.972867 (XEN) VCPU_LR[12]=0 Sep 15 01:45:08.972889 (XEN) VCPU_LR[13]=0 Sep 15 01:45:08.984793 (XEN) VCPU_LR[14]=0 Sep 15 01:45:08.984840 (XEN) VCPU_LR[15]=0 Sep 15 01:45:08.984887 (XEN) No periodic timer Sep 15 01:45:08.984929 (XEN) UNIT29 affinities: hard={0-95} soft={0-95} Sep 15 01:45:08.996737 (XEN) VCPU29: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:08.996767 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:08.996791 (XEN) GICH_LRs (vcpu 29) mask=0 Sep 15 01:45:09.008733 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.008759 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.008781 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.008806 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.008828 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.008852 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.020732 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.020757 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.020779 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.020801 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.020823 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.020845 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.032838 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.032893 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.032936 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.032976 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.033016 (XEN) No periodic timer Sep 15 01:45:09.033056 (XEN) UNIT30 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.044836 (XEN) VCPU30: CPU6 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.044900 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.056834 (XEN) GICH_LRs (vcpu 30) mask=0 Sep 15 01:45:09.056892 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.056935 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.056974 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.057014 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.068830 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.068886 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.068928 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.068969 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.069009 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.069048 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.080859 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.080914 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.080956 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.080996 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.081036 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.092833 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.092889 (XEN) No periodic timer Sep 15 01:45:09.092932 (XEN) UNIT31 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.092978 (XEN) VCPU31: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.104807 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.104839 (XEN) GICH_LRs (vcpu 31) mask=0 Sep 15 01:45:09.104863 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.116758 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.116789 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.116812 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.116835 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.116856 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.116877 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.128835 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.128893 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.128935 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.128975 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.129015 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.129054 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.140794 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.140824 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.140847 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.140879 (XEN) No periodic timer Sep 15 01:45:09.140903 (XEN) UNIT32 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.152826 (XEN) VCPU32: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.152891 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.152937 (XEN) GICH_LRs (vcpu 32) mask=0 Sep 15 01:45:09.164838 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.164897 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.164942 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.164984 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.165024 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.165069 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.176736 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.176762 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.176784 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.176806 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.176828 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.176849 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.188844 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.188901 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.188944 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.188984 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.189024 (XEN) No periodic timer Sep 15 01:45:09.200826 (XEN) UNIT33 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.200887 (XEN) VCPU33: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.212803 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.212861 (XEN) GICH_LRs (vcpu 33) mask=0 Sep 15 01:45:09.212905 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.212946 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.212986 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.224761 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.224791 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.224814 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.224836 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.224858 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.224879 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.236763 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.236793 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.236816 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.236838 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.236860 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.236881 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.248765 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.248795 (XEN) No periodic timer Sep 15 01:45:09.248818 (XEN) UNIT34 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.248843 (XEN) VCPU34: CPU70 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.260788 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.260820 (XEN) GICH_LRs (vcpu 34) mask=0 Sep 15 01:45:09.260846 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.272733 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.272759 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.272781 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.272803 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.272825 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.272847 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.284738 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.284766 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.284788 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.284810 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.284835 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.284857 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.296736 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.296761 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.296784 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.296806 (XEN) No periodic timer Sep 15 01:45:09.296829 (XEN) UNIT35 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.308734 (XEN) VCPU35: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.308764 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.308788 (XEN) GICH_LRs (vcpu 35) mask=0 Sep 15 01:45:09.320742 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.320769 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.320791 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.320813 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.320835 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.332780 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.332819 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.332843 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.332865 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.332890 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.332913 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.344733 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.344769 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.344795 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.344818 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.344843 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.356743 (XEN) No periodic timer Sep 15 01:45:09.356770 (XEN) UNIT36 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.356795 (XEN) VCPU36: CPU7 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.368758 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.368790 (XEN) GICH_LRs (vcpu 36) mask=0 Sep 15 01:45:09.368815 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.368837 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.368859 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.380735 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.380760 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.380783 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.380805 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.380827 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.380849 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.392739 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.392765 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.392788 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.392811 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.392832 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.392854 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.404733 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.404758 (XEN) No periodic timer Sep 15 01:45:09.404784 (XEN) UNIT37 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.404810 (XEN) VCPU37: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.416755 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.416785 (XEN) GICH_LRs (vcpu 37) mask=0 Sep 15 01:45:09.416809 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.428735 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.428760 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.428783 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.428812 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.428835 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.428858 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.440730 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.440756 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.440778 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.440800 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.440822 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.440844 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.452729 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.452754 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.452777 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.452799 (XEN) No periodic timer Sep 15 01:45:09.452821 (XEN) UNIT38 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.464830 (XEN) VCPU38: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.464891 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.476767 (XEN) GICH_LRs (vcpu 38) mask=0 Sep 15 01:45:09.476794 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.476816 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.476839 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.476860 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.488794 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.488820 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.488842 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.488865 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.488886 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.488908 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.500733 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.500758 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.500781 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.500803 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.500824 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.500846 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.512734 (XEN) No periodic timer Sep 15 01:45:09.512760 (XEN) UNIT39 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.512785 (XEN) VCPU39: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.524744 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.524771 (XEN) GICH_LRs (vcpu 39) mask=0 Sep 15 01:45:09.524795 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.524817 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.524838 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.536732 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.536757 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.536779 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.536801 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.536834 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.536858 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.548745 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.548771 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.548793 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.548818 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.548840 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.548864 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.560751 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.560777 (XEN) No periodic timer Sep 15 01:45:09.560800 (XEN) UNIT40 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.560825 (XEN) VCPU40: CPU73 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.572790 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.572839 (XEN) GICH_LRs (vcpu 40) mask=0 Sep 15 01:45:09.572882 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.584722 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.584748 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.584770 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.584792 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.584814 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.596781 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.596827 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.596868 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.596908 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.596948 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.596987 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.608782 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.608829 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.608870 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.608909 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.608949 (XEN) No periodic timer Sep 15 01:45:09.608989 (XEN) UNIT41 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.620808 (XEN) VCPU41: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.620862 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.632768 (XEN) GICH_LRs (vcpu 41) mask=0 Sep 15 01:45:09.632794 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.632816 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.632838 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.632860 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.644732 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.644759 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.644784 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.644806 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.644828 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.644850 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.656784 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.656830 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.656872 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.656912 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.656956 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.656998 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.668739 (XEN) No periodic timer Sep 15 01:45:09.668766 (XEN) UNIT42 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.668791 (XEN) VCPU42: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.680736 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.680765 (XEN) GICH_LRs (vcpu 42) mask=0 Sep 15 01:45:09.680789 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.680811 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.692737 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.692763 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.692786 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.692808 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.692830 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.692851 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.692873 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.704754 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.704785 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.704808 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.704830 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.704852 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.716836 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.716891 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.716933 (XEN) No periodic timer Sep 15 01:45:09.716974 (XEN) UNIT43 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.728808 (XEN) VCPU43: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.728843 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.728868 (XEN) GICH_LRs (vcpu 43) mask=0 Sep 15 01:45:09.740757 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.740787 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.740811 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.740843 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.740867 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.740890 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.752763 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.752793 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.752816 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.752838 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.752860 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.752881 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.764767 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.764798 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.764822 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.764845 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.764867 (XEN) No periodic timer Sep 15 01:45:09.764889 (XEN) UNIT44 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.776739 (XEN) VCPU44: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.776769 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.788767 (XEN) GICH_LRs (vcpu 44) mask=0 Sep 15 01:45:09.788816 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.788861 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.788901 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.788941 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.800767 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.800792 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.800814 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.800836 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.800858 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.800879 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.812731 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.812756 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.812779 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.812801 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.812823 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.812844 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.824804 (XEN) No periodic timer Sep 15 01:45:09.824855 (XEN) UNIT45 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.824905 (XEN) VCPU45: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.836764 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.836791 (XEN) GICH_LRs (vcpu 45) mask=0 Sep 15 01:45:09.836814 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.848747 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.848773 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.848795 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.848817 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.848839 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.848860 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.860732 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.860759 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.860781 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.860803 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.860825 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.860849 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.872737 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.872763 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.872785 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.872807 (XEN) No periodic timer Sep 15 01:45:09.872829 (XEN) UNIT46 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.884731 (XEN) VCPU46: CPU89 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.884761 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.884784 (XEN) GICH_LRs (vcpu 46) mask=0 Sep 15 01:45:09.896736 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.896762 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.896786 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.896808 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.896832 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.896854 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.908793 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.908819 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.908843 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.908865 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.908887 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.908911 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.920731 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.920756 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.920779 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.920801 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.920823 (XEN) No periodic timer Sep 15 01:45:09.932732 (XEN) UNIT47 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.932760 (XEN) VCPU47: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.932788 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.944742 (XEN) GICH_LRs (vcpu 47) mask=0 Sep 15 01:45:09.944769 (XEN) VCPU_LR[0]=0 Sep 15 01:45:09.944792 (XEN) VCPU_LR[1]=0 Sep 15 01:45:09.944813 (XEN) VCPU_LR[2]=0 Sep 15 01:45:09.944834 (XEN) VCPU_LR[3]=0 Sep 15 01:45:09.956793 (XEN) VCPU_LR[4]=0 Sep 15 01:45:09.956840 (XEN) VCPU_LR[5]=0 Sep 15 01:45:09.956880 (XEN) VCPU_LR[6]=0 Sep 15 01:45:09.956920 (XEN) VCPU_LR[7]=0 Sep 15 01:45:09.956960 (XEN) VCPU_LR[8]=0 Sep 15 01:45:09.956999 (XEN) VCPU_LR[9]=0 Sep 15 01:45:09.968767 (XEN) VCPU_LR[10]=0 Sep 15 01:45:09.968793 (XEN) VCPU_LR[11]=0 Sep 15 01:45:09.968815 (XEN) VCPU_LR[12]=0 Sep 15 01:45:09.968837 (XEN) VCPU_LR[13]=0 Sep 15 01:45:09.968859 (XEN) VCPU_LR[14]=0 Sep 15 01:45:09.980738 (XEN) VCPU_LR[15]=0 Sep 15 01:45:09.980763 (XEN) No periodic timer Sep 15 01:45:09.980786 (XEN) UNIT48 affinities: hard={0-95} soft={0-95} Sep 15 01:45:09.980810 (XEN) VCPU48: CPU9 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:09.992801 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:09.992854 (XEN) GICH_LRs (vcpu 48) mask=0 Sep 15 01:45:09.992901 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.004755 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.004780 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.004803 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.004824 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.004846 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.004871 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.016734 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.016760 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.016782 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.016804 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.016825 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.016847 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.028738 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.028764 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.028786 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.028808 (XEN) No periodic timer Sep 15 01:45:10.028830 (XEN) UNIT49 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.040771 (XEN) VCPU49: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.040806 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.040830 (XEN) GICH_LRs (vcpu 49) mask=0 Sep 15 01:45:10.052762 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.052792 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.052815 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.052837 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.052858 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.064851 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.064908 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.064950 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.064989 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.065030 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.065070 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.076754 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.076785 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.076808 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.076830 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.076852 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.076874 (XEN) No periodic timer Sep 15 01:45:10.088728 (XEN) UNIT50 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.088757 (XEN) VCPU50: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.100785 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.100834 (XEN) GICH_LRs (vcpu 50) mask=0 Sep 15 01:45:10.100877 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.100916 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.100955 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.112775 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.112800 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.112822 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.112844 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.112866 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.112887 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.124761 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.124813 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.124854 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.124900 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.124940 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.124985 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.136784 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.136830 (XEN) No periodic timer Sep 15 01:45:10.136889 (XEN) UNIT51 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.136937 (XEN) VCPU51: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.148793 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.148842 (XEN) GICH_LRs (vcpu 51) mask=0 Sep 15 01:45:10.148884 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.160733 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.160758 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.160784 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.160806 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.160827 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.160848 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.172775 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.172801 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.172825 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.172848 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.172869 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.172891 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.184804 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.184865 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.184905 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.184945 (XEN) No periodic timer Sep 15 01:45:10.184985 (XEN) UNIT52 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.196837 (XEN) VCPU52: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.196901 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.196946 (XEN) GICH_LRs (vcpu 52) mask=0 Sep 15 01:45:10.208849 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.208904 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.208945 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.208985 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.209025 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.220821 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.220877 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.220919 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.220960 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.221000 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.232759 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.232790 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.232813 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.232835 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.232856 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.232878 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.244832 (XEN) No periodic timer Sep 15 01:45:10.244889 (XEN) UNIT53 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.244935 (XEN) VCPU53: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.256761 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.256792 (XEN) GICH_LRs (vcpu 53) mask=0 Sep 15 01:45:10.256817 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.256839 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.256860 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.268802 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.268857 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.268899 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.268939 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.268979 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.269018 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.280754 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.280784 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.280807 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.280829 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.280851 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.292735 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.292761 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.292783 (XEN) No periodic timer Sep 15 01:45:10.292806 (XEN) UNIT54 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.292834 (XEN) VCPU54: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.304804 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.304857 (XEN) GICH_LRs (vcpu 54) mask=0 Sep 15 01:45:10.304903 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.316731 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.316756 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.316779 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.316801 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.316822 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.316844 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.328780 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.328826 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.328866 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.328907 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.328947 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.329004 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.340753 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.340781 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.340804 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.340827 (XEN) No periodic timer Sep 15 01:45:10.340849 (XEN) UNIT55 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.352778 (XEN) VCPU55: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.352832 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.364791 (XEN) GICH_LRs (vcpu 55) mask=0 Sep 15 01:45:10.364840 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.364885 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.364926 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.364968 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.376797 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.376845 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.376889 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.376930 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.376970 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.377015 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.388731 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.388756 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.388778 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.388800 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.388822 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.388843 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.400766 (XEN) No periodic timer Sep 15 01:45:10.400792 (XEN) UNIT56 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.400816 (XEN) VCPU56: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.412780 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.412829 (XEN) GICH_LRs (vcpu 56) mask=0 Sep 15 01:45:10.412871 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.412911 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.424782 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.424832 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.424874 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.424913 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.424956 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.424996 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.436729 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.436755 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.436776 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.436798 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.436820 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.436842 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.448735 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.448760 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.448784 (XEN) No periodic timer Sep 15 01:45:10.448807 (XEN) UNIT57 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.448831 (XEN) VCPU57: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.460742 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.460770 (XEN) GICH_LRs (vcpu 57) mask=0 Sep 15 01:45:10.460793 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.472773 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.472819 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.472860 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.472900 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.472939 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.484811 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.484859 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.484900 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.484940 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.484980 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.485019 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.496779 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.496804 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.496826 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.496848 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.496869 (XEN) No periodic timer Sep 15 01:45:10.508757 (XEN) UNIT58 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.508809 (XEN) VCPU58: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.508856 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.520785 (XEN) GICH_LRs (vcpu 58) mask=0 Sep 15 01:45:10.520838 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.520878 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.520922 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.520962 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.532768 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.532793 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.532815 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.532837 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.532868 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.532891 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.544775 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.544801 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.544823 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.544845 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.544867 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.544888 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.556764 (XEN) No periodic timer Sep 15 01:45:10.556790 (XEN) UNIT59 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.556815 (XEN) VCPU59: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.568786 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.568838 (XEN) GICH_LRs (vcpu 59) mask=0 Sep 15 01:45:10.568881 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.568924 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.580792 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.580843 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.580885 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.580929 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.580969 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.581012 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.592763 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.592788 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.592810 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.592832 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.592853 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.592875 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.604770 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.604795 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.604817 (XEN) No periodic timer Sep 15 01:45:10.604839 (XEN) UNIT60 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.616779 (XEN) VCPU60: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.616832 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.616876 (XEN) GICH_LRs (vcpu 60) mask=0 Sep 15 01:45:10.628761 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.628787 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.628809 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.628831 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.628853 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.628874 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.640806 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.640854 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.640895 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.640935 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.640975 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.652805 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.652836 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.652859 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.652881 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.652903 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.652924 (XEN) No periodic timer Sep 15 01:45:10.664803 (XEN) UNIT61 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.664837 (XEN) VCPU61: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.664864 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.676838 (XEN) GICH_LRs (vcpu 61) mask=0 Sep 15 01:45:10.676895 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.676941 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.676983 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.677024 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.688807 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.688838 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.688860 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.688882 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.688904 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.688925 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.700843 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.700899 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.700940 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.700980 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.701020 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.701059 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.712767 (XEN) No periodic timer Sep 15 01:45:10.712797 (XEN) UNIT62 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.712822 (XEN) VCPU62: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.724754 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.724786 (XEN) GICH_LRs (vcpu 62) mask=0 Sep 15 01:45:10.724809 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.736833 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.736888 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.736948 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.736993 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.737032 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.737072 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.748848 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.748904 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.748946 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.748986 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.749025 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.749064 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.760803 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.760834 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.760856 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.760878 (XEN) No periodic timer Sep 15 01:45:10.760900 (XEN) UNIT63 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.772763 (XEN) VCPU63: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.772798 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.772822 (XEN) GICH_LRs (vcpu 63) mask=0 Sep 15 01:45:10.784826 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.784885 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.784930 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.784972 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.785016 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.796788 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.796835 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.796875 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.796914 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.796953 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.796992 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.808732 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.808760 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.808783 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.808805 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.808826 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.808847 (XEN) No periodic timer Sep 15 01:45:10.820770 (XEN) UNIT64 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.820822 (XEN) VCPU64: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.820875 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.832785 (XEN) GICH_LRs (vcpu 64) mask=0 Sep 15 01:45:10.832834 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.832875 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.832915 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.832954 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.844753 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.844779 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.844801 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.844823 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.844844 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.844865 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.856752 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.856782 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.856805 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.856827 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.856849 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.868845 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.868900 (XEN) No periodic timer Sep 15 01:45:10.868943 (XEN) UNIT65 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.868988 (XEN) VCPU65: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.880766 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.880797 (XEN) GICH_LRs (vcpu 65) mask=0 Sep 15 01:45:10.880821 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.892813 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.892844 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.892866 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.892888 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.892909 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.892930 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.904745 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.904778 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.904801 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.904823 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.904845 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.904867 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.916816 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.916866 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.916911 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.916955 (XEN) No periodic timer Sep 15 01:45:10.917000 (XEN) UNIT66 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.928781 (XEN) VCPU66: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.928836 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.928911 (XEN) GICH_LRs (vcpu 66) mask=0 Sep 15 01:45:10.940734 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.940759 (XEN) VCPU_LR[1]=0 Sep 15 01:45:10.940781 (XEN) VCPU_LR[2]=0 Sep 15 01:45:10.940803 (XEN) VCPU_LR[3]=0 Sep 15 01:45:10.940824 (XEN) VCPU_LR[4]=0 Sep 15 01:45:10.952780 (XEN) VCPU_LR[5]=0 Sep 15 01:45:10.952827 (XEN) VCPU_LR[6]=0 Sep 15 01:45:10.952868 (XEN) VCPU_LR[7]=0 Sep 15 01:45:10.952907 (XEN) VCPU_LR[8]=0 Sep 15 01:45:10.952946 (XEN) VCPU_LR[9]=0 Sep 15 01:45:10.952985 (XEN) VCPU_LR[10]=0 Sep 15 01:45:10.964803 (XEN) VCPU_LR[11]=0 Sep 15 01:45:10.964850 (XEN) VCPU_LR[12]=0 Sep 15 01:45:10.964897 (XEN) VCPU_LR[13]=0 Sep 15 01:45:10.964938 (XEN) VCPU_LR[14]=0 Sep 15 01:45:10.964977 (XEN) VCPU_LR[15]=0 Sep 15 01:45:10.965018 (XEN) No periodic timer Sep 15 01:45:10.976720 (XEN) UNIT67 affinities: hard={0-95} soft={0-95} Sep 15 01:45:10.976748 (XEN) VCPU67: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:10.988741 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:10.988769 (XEN) GICH_LRs (vcpu 67) mask=0 Sep 15 01:45:10.988793 (XEN) VCPU_LR[0]=0 Sep 15 01:45:10.988814 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.000788 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.000835 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.000876 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.000916 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.000955 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.000994 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.012756 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.012803 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.012843 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.012883 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.012923 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.012963 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.024737 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.024763 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.024785 (XEN) No periodic timer Sep 15 01:45:11.024807 (XEN) UNIT68 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.024831 (XEN) VCPU68: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.036845 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.036903 (XEN) GICH_LRs (vcpu 68) mask=0 Sep 15 01:45:11.036947 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.048810 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.048840 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.048863 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.048885 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.048906 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.048927 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.060839 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.060895 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.060941 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.060982 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.061022 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.061061 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.072808 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.072837 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.072860 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.072882 (XEN) No periodic timer Sep 15 01:45:11.072904 (XEN) UNIT69 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.084763 (XEN) VCPU69: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.084797 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.096749 (XEN) GICH_LRs (vcpu 69) mask=0 Sep 15 01:45:11.096781 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.096804 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.096826 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.096847 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.096868 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.108724 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.108750 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.108772 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.108794 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.108815 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.120838 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.120893 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.120935 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.120975 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.121014 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.121053 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.132761 (XEN) No periodic timer Sep 15 01:45:11.132801 (XEN) UNIT70 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.132829 (XEN) VCPU70: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.144813 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.144844 (XEN) GICH_LRs (vcpu 70) mask=0 Sep 15 01:45:11.144868 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.144890 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.156833 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.156889 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.156930 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.156970 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.157009 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.157048 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.168835 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.168891 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.168933 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.168974 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.169014 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.169053 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.180832 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.180888 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.180930 (XEN) No periodic timer Sep 15 01:45:11.180972 (XEN) UNIT71 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.181017 (XEN) VCPU71: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.192865 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.192927 (XEN) GICH_LRs (vcpu 71) mask=0 Sep 15 01:45:11.204767 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.204816 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.204857 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.204902 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.204946 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.204987 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.216760 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.216807 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.216848 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.216887 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.216927 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.216966 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.228793 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.228840 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.228881 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.228920 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.228960 (XEN) No periodic timer Sep 15 01:45:11.229004 (XEN) UNIT72 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.240793 (XEN) VCPU72: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.240850 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.252764 (XEN) GICH_LRs (vcpu 72) mask=0 Sep 15 01:45:11.252813 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.252853 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.252893 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.252932 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.264768 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.264794 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.264816 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.264837 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.264859 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.264880 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.276749 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.276775 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.276797 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.276818 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.276840 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.276861 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.288769 (XEN) No periodic timer Sep 15 01:45:11.288795 (XEN) UNIT73 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.288820 (XEN) VCPU73: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.300803 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.300854 (XEN) GICH_LRs (vcpu 73) mask=0 Sep 15 01:45:11.300896 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.300936 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.312733 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.312758 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.312781 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.312803 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.312829 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.312852 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.324729 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.324754 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.324776 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.324798 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.324819 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.324851 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.336765 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.336791 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.336813 (XEN) No periodic timer Sep 15 01:45:11.336835 (XEN) UNIT74 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.348731 (XEN) VCPU74: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.348760 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.348785 (XEN) GICH_LRs (vcpu 74) mask=0 Sep 15 01:45:11.360721 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.360746 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.360768 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.360790 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.360812 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.372734 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.372760 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.372783 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.372804 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.372828 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.372851 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.384730 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.384755 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.384778 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.384800 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.384822 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.384843 (XEN) No periodic timer Sep 15 01:45:11.396734 (XEN) UNIT75 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.396763 (XEN) VCPU75: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.396791 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.408787 (XEN) GICH_LRs (vcpu 75) mask=0 Sep 15 01:45:11.408835 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.408875 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.408916 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.408956 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.420738 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.420765 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.420788 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.420813 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.420834 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.420856 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.432775 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.432800 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.432822 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.432844 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.432868 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.444728 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.444753 (XEN) No periodic timer Sep 15 01:45:11.444775 (XEN) UNIT76 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.444800 (XEN) VCPU76: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.456741 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.456768 (XEN) GICH_LRs (vcpu 76) mask=0 Sep 15 01:45:11.456792 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.456813 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.468761 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.468821 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.468861 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.468901 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.468940 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.468979 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.480768 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.480794 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.480816 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.480837 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.480859 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.480880 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.492802 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.492836 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.492860 (XEN) No periodic timer Sep 15 01:45:11.492885 (XEN) UNIT77 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.504791 (XEN) VCPU77: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.504848 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.504892 (XEN) GICH_LRs (vcpu 77) mask=0 Sep 15 01:45:11.516758 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.516784 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.516806 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.516827 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.516849 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.528773 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.528835 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.528880 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.528938 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.528983 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.529024 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.540797 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.540843 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.540884 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.540924 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.540964 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.541003 (XEN) No periodic timer Sep 15 01:45:11.552731 (XEN) UNIT78 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.552761 (XEN) VCPU78: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.564768 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.564795 (XEN) GICH_LRs (vcpu 78) mask=0 Sep 15 01:45:11.564821 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.564843 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.564865 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.576778 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.576803 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.576825 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.576847 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.576868 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.576890 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.588767 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.588813 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.588853 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.588893 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.588932 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.588971 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.600822 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.600873 (XEN) No periodic timer Sep 15 01:45:11.600920 (XEN) UNIT79 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.600970 (XEN) VCPU79: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.612758 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.612785 (XEN) GICH_LRs (vcpu 79) mask=0 Sep 15 01:45:11.612808 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.624785 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.624831 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.624878 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.624918 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.624961 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.625002 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.636784 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.636810 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.636833 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.636855 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.636876 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.636898 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.648767 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.648797 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.648819 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.648841 (XEN) No periodic timer Sep 15 01:45:11.648863 (XEN) UNIT80 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.660809 (XEN) VCPU80: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.660873 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.672794 (XEN) GICH_LRs (vcpu 80) mask=0 Sep 15 01:45:11.672826 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.672849 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.672871 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.672892 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.672913 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.684805 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.684835 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.684858 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.684880 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.684902 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.684923 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.696818 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.696861 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.696894 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.696917 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.696939 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.696961 (XEN) No periodic timer Sep 15 01:45:11.708835 (XEN) UNIT81 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.708896 (XEN) VCPU81: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.720784 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.720834 (XEN) GICH_LRs (vcpu 81) mask=0 Sep 15 01:45:11.720877 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.720917 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.720956 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.732771 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.732797 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.732819 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.732841 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.732863 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.732884 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.744798 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.744849 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.744891 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.744931 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.744971 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.756781 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.756827 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.756868 (XEN) No periodic timer Sep 15 01:45:11.756908 (XEN) UNIT82 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.756952 (XEN) VCPU82: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.768766 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.768818 (XEN) GICH_LRs (vcpu 82) mask=0 Sep 15 01:45:11.768862 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.780766 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.780814 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.780857 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.780897 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.780941 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.780982 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.792771 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.792797 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.792819 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.792841 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.792862 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.804790 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.804838 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.804879 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.804920 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.804959 (XEN) No periodic timer Sep 15 01:45:11.804999 (XEN) UNIT83 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.816792 (XEN) VCPU83: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.816849 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.828769 (XEN) GICH_LRs (vcpu 83) mask=0 Sep 15 01:45:11.828800 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.828823 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.828847 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.828869 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.828893 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.840765 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.840791 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.840813 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.840835 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.840857 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.840878 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.852735 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.852761 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.852783 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.852805 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.852830 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.864763 (XEN) No periodic timer Sep 15 01:45:11.864792 (XEN) UNIT84 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.864817 (XEN) VCPU84: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.876731 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.876759 (XEN) GICH_LRs (vcpu 84) mask=0 Sep 15 01:45:11.876783 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.876807 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.888732 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.888759 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.888782 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.888803 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.888827 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.888849 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.900802 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.900834 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.900856 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.900878 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.900899 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.900921 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.912786 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.912832 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.912873 (XEN) No periodic timer Sep 15 01:45:11.912913 (XEN) UNIT85 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.912958 (XEN) VCPU85: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.924769 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.924808 (XEN) GICH_LRs (vcpu 85) mask=0 Sep 15 01:45:11.936734 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.936759 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.936781 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.936803 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.936825 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.936846 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.948796 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.948842 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.948882 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.948922 (XEN) VCPU_LR[9]=0 Sep 15 01:45:11.948961 (XEN) VCPU_LR[10]=0 Sep 15 01:45:11.949000 (XEN) VCPU_LR[11]=0 Sep 15 01:45:11.960821 (XEN) VCPU_LR[12]=0 Sep 15 01:45:11.960868 (XEN) VCPU_LR[13]=0 Sep 15 01:45:11.960912 (XEN) VCPU_LR[14]=0 Sep 15 01:45:11.960954 (XEN) VCPU_LR[15]=0 Sep 15 01:45:11.960995 (XEN) No periodic timer Sep 15 01:45:11.961038 (XEN) UNIT86 affinities: hard={0-95} soft={0-95} Sep 15 01:45:11.972789 (XEN) VCPU86: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:11.972844 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:11.984734 (XEN) GICH_LRs (vcpu 86) mask=0 Sep 15 01:45:11.984760 (XEN) VCPU_LR[0]=0 Sep 15 01:45:11.984783 (XEN) VCPU_LR[1]=0 Sep 15 01:45:11.984804 (XEN) VCPU_LR[2]=0 Sep 15 01:45:11.984826 (XEN) VCPU_LR[3]=0 Sep 15 01:45:11.984847 (XEN) VCPU_LR[4]=0 Sep 15 01:45:11.996785 (XEN) VCPU_LR[5]=0 Sep 15 01:45:11.996836 (XEN) VCPU_LR[6]=0 Sep 15 01:45:11.996881 (XEN) VCPU_LR[7]=0 Sep 15 01:45:11.996925 (XEN) VCPU_LR[8]=0 Sep 15 01:45:11.996968 (XEN) VCPU_LR[9]=0 Sep 15 01:45:12.008796 (XEN) VCPU_LR[10]=0 Sep 15 01:45:12.008844 (XEN) VCPU_LR[11]=0 Sep 15 01:45:12.008885 (XEN) VCPU_LR[12]=0 Sep 15 01:45:12.008924 (XEN) VCPU_LR[13]=0 Sep 15 01:45:12.008964 (XEN) VCPU_LR[14]=0 Sep 15 01:45:12.020732 (XEN) VCPU_LR[15]=0 Sep 15 01:45:12.020758 (XEN) No periodic timer Sep 15 01:45:12.020780 (XEN) UNIT87 affinities: hard={0-95} soft={0-95} Sep 15 01:45:12.020804 (XEN) VCPU87: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:12.032847 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:12.032905 (XEN) GICH_LRs (vcpu 87) mask=0 Sep 15 01:45:12.032950 (XEN) VCPU_LR[0]=0 Sep 15 01:45:12.032994 (XEN) VCPU_LR[1]=0 Sep 15 01:45:12.044856 (XEN) VCPU_LR[2]=0 Sep 15 01:45:12.044912 (XEN) VCPU_LR[3]=0 Sep 15 01:45:12.044955 (XEN) VCPU_LR[4]=0 Sep 15 01:45:12.044995 (XEN) VCPU_LR[5]=0 Sep 15 01:45:12.045034 (XEN) VCPU_LR[6]=0 Sep 15 01:45:12.045073 (XEN) VCPU_LR[7]=0 Sep 15 01:45:12.056771 (XEN) VCPU_LR[8]=0 Sep 15 01:45:12.056801 (XEN) VCPU_LR[9]=0 Sep 15 01:45:12.056824 (XEN) VCPU_LR[10]=0 Sep 15 01:45:12.056846 (XEN) VCPU_LR[11]=0 Sep 15 01:45:12.056867 (XEN) VCPU_LR[12]=0 Sep 15 01:45:12.056889 (XEN) VCPU_LR[13]=0 Sep 15 01:45:12.068762 (XEN) VCPU_LR[14]=0 Sep 15 01:45:12.068792 (XEN) VCPU_LR[15]=0 Sep 15 01:45:12.068815 (XEN) No periodic timer Sep 15 01:45:12.068837 (XEN) UNIT88 affinities: hard={0-95} soft={0-95} Sep 15 01:45:12.080761 (XEN) VCPU88: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:12.080798 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:12.080822 (XEN) GICH_LRs (vcpu 88) mask=0 Sep 15 01:45:12.092810 (XEN) VCPU_LR[0]=0 Sep 15 01:45:12.092840 (XEN) VCPU_LR[1]=0 Sep 15 01:45:12.092863 (XEN) VCPU_LR[2]=0 Sep 15 01:45:12.092884 (XEN) VCPU_LR[3]=0 Sep 15 01:45:12.092906 (XEN) VCPU_LR[4]=0 Sep 15 01:45:12.092927 (XEN) VCPU_LR[5]=0 Sep 15 01:45:12.104760 (XEN) VCPU_LR[6]=0 Sep 15 01:45:12.104795 (XEN) VCPU_LR[7]=0 Sep 15 01:45:12.104830 (XEN) VCPU_LR[8]=0 Sep 15 01:45:12.104866 (XEN) VCPU_LR[9]=0 Sep 15 01:45:12.104900 (XEN) VCPU_LR[10]=0 Sep 15 01:45:12.104925 (XEN) VCPU_LR[11]=0 Sep 15 01:45:12.116781 (XEN) VCPU_LR[12]=0 Sep 15 01:45:12.116829 (XEN) VCPU_LR[13]=0 Sep 15 01:45:12.116870 (XEN) VCPU_LR[14]=0 Sep 15 01:45:12.116910 (XEN) VCPU_LR[15]=0 Sep 15 01:45:12.116949 (XEN) No periodic timer Sep 15 01:45:12.117008 (XEN) UNIT89 affinities: hard={0-95} soft={0-95} Sep 15 01:45:12.128770 (XEN) VCPU89: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:12.128826 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:12.140733 (XEN) GICH_LRs (vcpu 89) mask=0 Sep 15 01:45:12.140759 (XEN) VCPU_LR[0]=0 Sep 15 01:45:12.140782 (XEN) VCPU_LR[1]=0 Sep 15 01:45:12.140804 (XEN) VCPU_LR[2]=0 Sep 15 01:45:12.152734 (XEN) VCPU_LR[3]=0 Sep 15 01:45:12.152762 (XEN) VCPU_LR[4]=0 Sep 15 01:45:12.152785 (XEN) VCPU_LR[5]=0 Sep 15 01:45:12.152808 (XEN) VCPU_LR[6]=0 Sep 15 01:45:12.152831 (XEN) VCPU_LR[7]=0 Sep 15 01:45:12.152856 (XEN) VCPU_LR[8]=0 Sep 15 01:45:12.164729 (XEN) VCPU_LR[9]=0 Sep 15 01:45:12.164754 (XEN) VCPU_LR[10]=0 Sep 15 01:45:12.164776 (XEN) VCPU_LR[11]=0 Sep 15 01:45:12.164798 (XEN) VCPU_LR[12]=0 Sep 15 01:45:12.164820 (XEN) VCPU_LR[13]=0 Sep 15 01:45:12.164841 (XEN) VCPU_LR[14]=0 Sep 15 01:45:12.176742 (XEN) VCPU_LR[15]=0 Sep 15 01:45:12.176768 (XEN) No periodic timer Sep 15 01:45:12.176791 (XEN) UNIT90 affinities: hard={0-95} soft={0-95} Sep 15 01:45:12.176816 (XEN) VCPU90: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:12.188741 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:12.188769 (XEN) GICH_LRs (vcpu 90) mask=0 Sep 15 01:45:12.188792 (XEN) VCPU_LR[0]=0 Sep 15 01:45:12.188814 (XEN) VCPU_LR[1]=0 Sep 15 01:45:12.200817 (XEN) VCPU_LR[2]=0 Sep 15 01:45:12.200855 (XEN) VCPU_LR[3]=0 Sep 15 01:45:12.200880 (XEN) VCPU_LR[4]=0 Sep 15 01:45:12.200902 (XEN) VCPU_LR[5]=0 Sep 15 01:45:12.200924 (XEN) VCPU_LR[6]=0 Sep 15 01:45:12.200945 (XEN) VCPU_LR[7]=0 Sep 15 01:45:12.212803 (XEN) VCPU_LR[8]=0 Sep 15 01:45:12.212833 (XEN) VCPU_LR[9]=0 Sep 15 01:45:12.212855 (XEN) VCPU_LR[10]=0 Sep 15 01:45:12.212877 (XEN) VCPU_LR[11]=0 Sep 15 01:45:12.212898 (XEN) VCPU_LR[12]=0 Sep 15 01:45:12.212919 (XEN) VCPU_LR[13]=0 Sep 15 01:45:12.224789 (XEN) VCPU_LR[14]=0 Sep 15 01:45:12.224835 (XEN) VCPU_LR[15]=0 Sep 15 01:45:12.224876 (XEN) No periodic timer Sep 15 01:45:12.224917 (XEN) UNIT91 affinities: hard={0-95} soft={0-95} Sep 15 01:45:12.236732 (XEN) VCPU91: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:12.236762 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:12.236786 (XEN) GICH_LRs (vcpu 91) mask=0 Sep 15 01:45:12.248760 (XEN) VCPU_LR[0]=0 Sep 15 01:45:12.248786 (XEN) VCPU_LR[1]=0 Sep 15 01:45:12.248809 (XEN) VCPU_LR[2]=0 Sep 15 01:45:12.248830 (XEN) VCPU_LR[3]=0 Sep 15 01:45:12.248851 (XEN) VCPU_LR[4]=0 Sep 15 01:45:12.260773 (XEN) VCPU_LR[5]=0 Sep 15 01:45:12.260820 (XEN) VCPU_LR[6]=0 Sep 15 01:45:12.260864 (XEN) VCPU_LR[7]=0 Sep 15 01:45:12.260905 (XEN) VCPU_LR[8]=0 Sep 15 01:45:12.260945 (XEN) VCPU_LR[9]=0 Sep 15 01:45:12.260990 (XEN) VCPU_LR[10]=0 Sep 15 01:45:12.272734 (XEN) VCPU_LR[11]=0 Sep 15 01:45:12.272759 (XEN) VCPU_LR[12]=0 Sep 15 01:45:12.272782 (XEN) VCPU_LR[13]=0 Sep 15 01:45:12.272806 (XEN) VCPU_LR[14]=0 Sep 15 01:45:12.272828 (XEN) VCPU_LR[15]=0 Sep 15 01:45:12.272850 (XEN) No periodic timer Sep 15 01:45:12.284764 (XEN) UNIT92 affinities: hard={0-95} soft={0-95} Sep 15 01:45:12.284792 (XEN) VCPU92: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:12.296739 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:12.296784 (XEN) GICH_LRs (vcpu 92) mask=0 Sep 15 01:45:12.296832 (XEN) VCPU_LR[0]=0 Sep 15 01:45:12.296874 (XEN) VCPU_LR[1]=0 Sep 15 01:45:12.296917 (XEN) VCPU_LR[2]=0 Sep 15 01:45:12.308792 (XEN) VCPU_LR[3]=0 Sep 15 01:45:12.308818 (XEN) VCPU_LR[4]=0 Sep 15 01:45:12.308841 (XEN) VCPU_LR[5]=0 Sep 15 01:45:12.308864 (XEN) VCPU_LR[6]=0 Sep 15 01:45:12.308885 (XEN) VCPU_LR[7]=0 Sep 15 01:45:12.308907 (XEN) VCPU_LR[8]=0 Sep 15 01:45:12.320766 (XEN) VCPU_LR[9]=0 Sep 15 01:45:12.320791 (XEN) VCPU_LR[10]=0 Sep 15 01:45:12.320813 (XEN) VCPU_LR[11]=0 Sep 15 01:45:12.320835 (XEN) VCPU_LR[12]=0 Sep 15 01:45:12.320867 (XEN) VCPU_LR[13]=0 Sep 15 01:45:12.320890 (XEN) VCPU_LR[14]=0 Sep 15 01:45:12.332731 (XEN) VCPU_LR[15]=0 Sep 15 01:45:12.332756 (XEN) No periodic timer Sep 15 01:45:12.332781 (XEN) UNIT93 affinities: hard={0-95} soft={0-95} Sep 15 01:45:12.332806 (XEN) VCPU93: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:12.344779 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:12.344806 (XEN) GICH_LRs (vcpu 93) mask=0 Sep 15 01:45:12.344830 (XEN) VCPU_LR[0]=0 Sep 15 01:45:12.356735 (XEN) VCPU_LR[1]=0 Sep 15 01:45:12.356761 (XEN) VCPU_LR[2]=0 Sep 15 01:45:12.356783 (XEN) VCPU_LR[3]=0 Sep 15 01:45:12.356805 (XEN) VCPU_LR[4]=0 Sep 15 01:45:12.356826 (XEN) VCPU_LR[5]=0 Sep 15 01:45:12.356847 (XEN) VCPU_LR[6]=0 Sep 15 01:45:12.368734 (XEN) VCPU_LR[7]=0 Sep 15 01:45:12.368760 (XEN) VCPU_LR[8]=0 Sep 15 01:45:12.368782 (XEN) VCPU_LR[9]=0 Sep 15 01:45:12.368803 (XEN) VCPU_LR[10]=0 Sep 15 01:45:12.368825 (XEN) VCPU_LR[11]=0 Sep 15 01:45:12.368846 (XEN) VCPU_LR[12]=0 Sep 15 01:45:12.380722 (XEN) VCPU_LR[13]=0 Sep 15 01:45:12.380748 (XEN) VCPU_LR[14]=0 Sep 15 01:45:12.380770 (XEN) VCPU_LR[15]=0 Sep 15 01:45:12.380792 (XEN) No periodic timer Sep 15 01:45:12.380815 (XEN) UNIT94 affinities: hard={0-95} soft={0-95} Sep 15 01:45:12.392732 (XEN) VCPU94: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:12.392761 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:12.404737 (XEN) GICH_LRs (vcpu 94) mask=0 Sep 15 01:45:12.404765 (XEN) VCPU_LR[0]=0 Sep 15 01:45:12.404788 (XEN) VCPU_LR[1]=0 Sep 15 01:45:12.404810 (XEN) VCPU_LR[2]=0 Sep 15 01:45:12.404834 (XEN) VCPU_LR[3]=0 Sep 15 01:45:12.404856 (XEN) VCPU_LR[4]=0 Sep 15 01:45:12.416740 (XEN) VCPU_LR[5]=0 Sep 15 01:45:12.416769 (XEN) VCPU_LR[6]=0 Sep 15 01:45:12.416791 (XEN) VCPU_LR[7]=0 Sep 15 01:45:12.416813 (XEN) VCPU_LR[8]=0 Sep 15 01:45:12.416834 (XEN) VCPU_LR[9]=0 Sep 15 01:45:12.416858 (XEN) VCPU_LR[10]=0 Sep 15 01:45:12.428783 (XEN) VCPU_LR[11]=0 Sep 15 01:45:12.428829 (XEN) VCPU_LR[12]=0 Sep 15 01:45:12.428870 (XEN) VCPU_LR[13]=0 Sep 15 01:45:12.428914 (XEN) VCPU_LR[14]=0 Sep 15 01:45:12.428955 (XEN) VCPU_LR[15]=0 Sep 15 01:45:12.428995 (XEN) No periodic timer Sep 15 01:45:12.440787 (XEN) UNIT95 affinities: hard={0-95} soft={0-95} Sep 15 01:45:12.440843 (XEN) VCPU95: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 15 01:45:12.452774 (XEN) pause_count=0 pause_flags=1 Sep 15 01:45:12.452801 (XEN) GICH_LRs (vcpu 95) mask=0 Sep 15 01:45:12.452826 (XEN) VCPU_LR[0]=0 Sep 15 01:45:12.452849 (XEN) VCPU_LR[1]=0 Sep 15 01:45:12.452871 (XEN) VCPU_LR[2]=0 Sep 15 01:45:12.464741 (XEN) VCPU_LR[3]=0 Sep 15 01:45:12.464767 (XEN) VCPU_LR[4]=0 Sep 15 01:45:12.464789 (XEN) VCPU_LR[5]=0 Sep 15 01:45:12.464811 (XEN) VCPU_LR[6]=0 Sep 15 01:45:12.464832 (XEN) VCPU_LR[7]=0 Sep 15 01:45:12.464854 (XEN) VCPU_LR[8]=0 Sep 15 01:45:12.476782 (XEN) VCPU_LR[9]=0 Sep 15 01:45:12.476807 (XEN) VCPU_LR[10]=0 Sep 15 01:45:12.476831 (XEN) VCPU_LR[11]=0 Sep 15 01:45:12.476854 (XEN) VCPU_LR[12]=0 Sep 15 01:45:12.476877 (XEN) VCPU_LR[13]=0 Sep 15 01:45:12.476900 (XEN) VCPU_LR[14]=0 Sep 15 01:45:12.488734 (XEN) VCPU_LR[15]=0 Sep 15 01:45:12.488760 (XEN) No periodic timer Sep 15 01:45:12.488783 (XEN) Notifying guest 0:0 (virq 1, port 0) Sep 15 01:45:12.488806 (XEN) Notifying guest 0:1 (virq 1, port 0) Sep 15 01:45:12.500756 (XEN) Notifying guest 0:2 (virq 1, port 0) Sep 15 01:45:12.500784 (XEN) Notifying guest 0:3 (virq 1, port 0) Sep 15 01:45:12.500810 (XEN) Notifying guest 0:4 (virq 1, port 0) Sep 15 01:45:12.512764 (XEN) Notifying guest 0:5 (virq 1, port 0) Sep 15 01:45:12.512804 (XEN) Notifying guest 0:6 (virq 1, port 0) Sep 15 01:45:12.512839 (XEN) Notifying guest 0:7 (virq 1, port 0) Sep 15 01:45:12.524802 (XEN) Notifying guest 0:8 (virq 1, port 0) Sep 15 01:45:12.524852 (XEN) Notifying guest 0:9 (virq 1, port 0) Sep 15 01:45:12.524913 (XEN) Notifying guest 0:10 (virq 1, port 0) Sep 15 01:45:12.536732 (XEN) Notifying guest 0:11 (virq 1, port 0) Sep 15 01:45:12.536759 (XEN) Notifying guest 0:12 (virq 1, port 0) Sep 15 01:45:12.536782 (XEN) Notifying guest 0:13 (virq 1, port 0) Sep 15 01:45:12.548856 (XEN) Notifying guest 0:14 (virq 1, port 0) Sep 15 01:45:12.548916 (XEN) Notifying guest 0:15 (virq 1, port 0) Sep 15 01:45:12.548961 (XEN) Notifying guest 0:16 (virq 1, port 0) Sep 15 01:45:12.560735 (XEN) Notifying guest 0:17 (virq 1, port 0) Sep 15 01:45:12.560762 (XEN) Notifying guest 0:18 (virq 1, port 0) Sep 15 01:45:12.560786 (XEN) Notifying guest 0:19 (virq 1, port 0) Sep 15 01:45:12.572806 (XEN) Notifying guest 0:20 (virq 1, port 0) Sep 15 01:45:12.572838 (XEN) Notifying guest 0:21 (virq 1, port 0) Sep 15 01:45:12.572863 (XEN) Notifying guest 0:22 (virq 1, port 0) Sep 15 01:45:12.584802 (XEN) Notifying guest 0:23 (virq 1, port 0) Sep 15 01:45:12.584852 (XEN) Notifying guest 0:24 (virq 1, port 0) Sep 15 01:45:12.584896 (XEN) Notifying guest 0:25 (virq 1, port 0) Sep 15 01:45:12.584940 (XEN) Notifying guest 0:26 (virq 1, port 0) Sep 15 01:45:12.596736 (XEN) Notifying guest 0:27 (virq 1, port 0) Sep 15 01:45:12.596763 (XEN) Notifying guest 0:28 (virq 1, port 0) Sep 15 01:45:12.596787 (XEN) Notifying guest 0:29 (virq 1, port 0) Sep 15 01:45:12.608802 (XEN) Notifying guest 0:30 (virq 1, port 0) Sep 15 01:45:12.608855 (XEN) Notifying guest 0:31 (virq 1, port 0) Sep 15 01:45:12.608902 (XEN) Notifying guest 0:32 (virq 1, port 0) Sep 15 01:45:12.620739 (XEN) Notifying guest 0:33 (virq 1, port 0) Sep 15 01:45:12.620767 (XEN) Notifying guest 0:34 (virq 1, port 0) Sep 15 01:45:12.620790 (XEN) Notifying guest 0:35 (virq 1, port 0) Sep 15 01:45:12.632765 (XEN) Notifying guest 0:36 (virq 1, port 0) Sep 15 01:45:12.632792 (XEN) Notifying guest 0:37 (virq 1, port 0) Sep 15 01:45:12.644766 (XEN) Notifying guest 0:38 (virq 1, port 0) Sep 15 01:45:12.644793 (XEN) Notifying guest 0:39 (virq 1, port 0) Sep 15 01:45:12.644816 (XEN) Notifying guest 0:40 (virq 1, port 0) Sep 15 01:45:12.656770 (XEN) Notifying guest 0:41 (virq 1, port 0) Sep 15 01:45:12.656798 (XEN) Notifying guest 0:42 (virq 1, port 0) Sep 15 01:45:12.656821 (XEN) Notifying guest 0:43 (virq 1, port 0) Sep 15 01:45:12.668735 (XEN) Notifying guest 0:44 (virq 1, port 0) Sep 15 01:45:12.668762 (XEN) Notifying guest 0:45 (virq 1, port 0) Sep 15 01:45:12.668786 (XEN) Notifying guest 0:46 (virq 1, port 0) Sep 15 01:45:12.668812 (XEN) Notifying guest 0:47 (virq 1, port 0) Sep 15 01:45:12.680739 (XEN) Notifying guest 0:48 (virq 1, port 0) Sep 15 01:45:12.680766 (XEN) Notifying guest 0:49 (virq 1, port 0) Sep 15 01:45:12.680789 (XEN) Notifying guest 0:50 (virq 1, port 0) Sep 15 01:45:12.692740 (XEN) Notifying guest 0:51 (virq 1, port 0) Sep 15 01:45:12.692768 (XEN) Notifying guest 0:52 (virq 1, port 0) Sep 15 01:45:12.692792 (XEN) Notifying guest 0:53 (virq 1, port 0) Sep 15 01:45:12.704804 (XEN) Notifying guest 0:54 (virq 1, port 0) Sep 15 01:45:12.704862 (XEN) Notifying guest 0:55 (virq 1, port 0) Sep 15 01:45:12.704907 (XEN) Notifying guest 0:56 (virq 1, port 0) Sep 15 01:45:12.716869 (XEN) Notifying guest 0:57 (virq 1, port 0) Sep 15 01:45:12.716951 (XEN) Notifying guest 0:58 (virq 1, port 0) Sep 15 01:45:12.717001 (XEN) Notifying guest 0:59 (virq 1, port 0) Sep 15 01:45:12.728760 (XEN) Notifying guest 0:60 (virq 1, port 0) Sep 15 01:45:12.728792 (XEN) Notifying guest 0:61 (virq 1, port 0) Sep 15 01:45:12.728817 (XEN) Notifying guest 0:62 (virq 1, port 0) Sep 15 01:45:12.740796 (XEN) Notifying guest 0:63 (virq 1, port 0) Sep 15 01:45:12.740846 (XEN) Notifying guest 0:64 (virq 1, port 0) Sep 15 01:45:12.740890 (XEN) Notifying guest 0:65 (virq 1, port 0) Sep 15 01:45:12.752732 (XEN) Notifying guest 0:66 (virq 1, port 0) Sep 15 01:45:12.752759 (XEN) Notifying guest 0:67 (virq 1, port 0) Sep 15 01:45:12.752783 (XEN) Notifying guest 0:68 (virq 1, port 0) Sep 15 01:45:12.764721 (XEN) Notifying guest 0:69 (virq 1, port 0) Sep 15 01:45:12.764761 (XEN) Notifying guest 0:70 (virq 1, port 0) Sep 15 01:45:12.764786 (XEN) Notifying guest 0:71 (virq 1, port 0) Sep 15 01:45:12.776789 (XEN) Notifying guest 0:72 (virq 1, port 0) Sep 15 01:45:12.776838 (XEN) Notifying guest 0:73 (virq 1, port 0) Sep 15 01:45:12.776882 (XEN) Notifying guest 0:74 (virq 1, port 0) Sep 15 01:45:12.788748 (XEN) Notifying guest 0:75 (virq 1, port 0) Sep 15 01:45:12.788775 (XEN) Notifying guest 0:76 (virq 1, port 0) Sep 15 01:45:12.788799 (XEN) Notifying guest 0:77 (virq 1, port 0) Sep 15 01:45:12.800733 (XEN) Notifying guest 0:78 (virq 1, port 0) Sep 15 01:45:12.800762 (XEN) Notifying guest 0:79 (virq 1, port 0) Sep 15 01:45:12.800786 (XEN) Notifying guest 0:80 (virq 1, port 0) Sep 15 01:45:12.812732 (XEN) Notifying guest 0:81 (virq 1, port 0) Sep 15 01:45:12.812759 (XEN) Notifying guest 0:82 (virq 1, port 0) Sep 15 01:45:12.812782 (XEN) Notifying guest 0:83 (virq 1, port 0) Sep 15 01:45:12.824793 (XEN) Notifying guest 0:84 (virq 1, port 0) Sep 15 01:45:12.824825 (XEN) Notifying guest 0:85 (virq 1, port 0) Sep 15 01:45:12.824850 (XEN) Notifying guest 0:86 (virq 1, port 0) Sep 15 01:45:12.836835 (XEN) Notifying guest 0:87 (virq 1, port 0) Sep 15 01:45:12.836870 (XEN) Notifying guest 0:88 (virq 1, port 0) Sep 15 01:45:12.836895 (XEN) Notifying guest 0:89 (virq 1, port 0) Sep 15 01:45:12.848736 (XEN) Notifying guest 0:90 (virq 1, port 0) Sep 15 01:45:12.848763 (XEN) Notifying guest 0:91 (virq 1, port 0) Sep 15 01:45:12.848787 (XEN) Notifying guest 0:92 (virq 1, port 0) Sep 15 01:45:12.860799 (XEN) Notifying guest 0:93 (virq 1, port 0) Sep 15 01:45:12.860827 (XEN) Notifying guest 0:94 (virq 1, port 0) Sep 15 01:45:12.860850 (XEN) Notifying guest 0:95 (virq 1, port 0) Sep 15 01:45:12.872682 Sep 15 01:45:19.386680 (XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input) Sep 15 01:45:19.400755 Sep 15 01:45:19.401504