Sep 19 15:43:20.386939 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.387241 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.387316 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.396718 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.396718 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.396718 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.396718 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.396718 (XEN) No periodic timer
Sep 19 15:43:20.396718 (XEN)   UNIT55 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.408664 (XEN)     VCPU55: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.408664 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.420709 (XEN) GICH_LRs (vcpu 55) mask=0
Sep 19 15:43:20.420709 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.420709 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.420709 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.420709 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.432672 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:20.432672 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:20.432672 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:20.432672 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:20.432672 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:20.432672 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.444667 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.444667 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.444667 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.444667 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.444667 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.444667 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.456668 (XEN) No periodic timer
Sep 19 15:43:20.456668 (XEN)   UNIT56 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.456668 (XEN)     VCPU56: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.468668 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.468668 (XEN) GICH_LRs (vcpu 56) mask=0
Sep 19 15:43:20.468668 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.468668 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.480668 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.480668 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.480668 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:20.480668 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:20.480668 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:20.480668 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:20.492669 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:20.492669 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.492669 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.492669 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.492669 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.492669 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.504671 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.504671 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.504671 (XEN) No periodic timer
Sep 19 15:43:20.504671 (XEN)   UNIT57 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.516667 (XEN)     VCPU57: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.516667 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.516667 (XEN) GICH_LRs (vcpu 57) mask=0
Sep 19 15:43:20.528659 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.528659 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.528659 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.528659 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.528659 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:20.540755 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:20.540755 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:20.540755 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:20.540755 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:20.540755 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.540755 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.552669 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.552669 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.552669 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.552669 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.552669 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.552669 (XEN) No periodic timer
Sep 19 15:43:20.564670 (XEN)   UNIT58 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.564670 (XEN)     VCPU58: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.564670 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.576672 (XEN) GICH_LRs (vcpu 58) mask=0
Sep 19 15:43:20.576672 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.576672 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.576672 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.576672 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.588666 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:20.588666 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:20.588666 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:20.588666 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:20.588666 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:20.588666 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.600668 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.600668 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.600668 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.600668 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.600668 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.612668 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.612668 (XEN) No periodic timer
Sep 19 15:43:20.612668 (XEN)   UNIT59 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.612668 (XEN)     VCPU59: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.624667 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.624667 (XEN) GICH_LRs (vcpu 59) mask=0
Sep 19 15:43:20.624667 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.624667 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.636931 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.636994 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.637036 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:20.637099 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:20.637140 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:20.637180 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:20.648912 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:20.648967 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.649032 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.649074 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.649114 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.649154 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.660918 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.660995 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.661038 (XEN) No periodic timer
Sep 19 15:43:20.661080 (XEN)   UNIT60 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.672926 (XEN)     VCPU60: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.672990 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.673058 (XEN) GICH_LRs (vcpu 60) mask=0
Sep 19 15:43:20.684930 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.684984 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.685027 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.685069 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.685133 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:20.696925 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:20.696981 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:20.697023 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:20.697063 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:20.697126 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.697168 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.708924 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.708980 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.709024 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.709088 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.709129 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.709170 (XEN) No periodic timer
Sep 19 15:43:20.720916 (XEN)   UNIT61 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.720977 (XEN)     VCPU61: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.721050 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.732933 (XEN) GICH_LRs (vcpu 61) mask=0
Sep 19 15:43:20.732990 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.733033 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.733074 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.744925 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.744981 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:20.745024 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:20.745065 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:20.745105 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:20.745167 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:20.756946 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.757003 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.757057 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.757101 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.757166 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.757209 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.768917 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.768973 (XEN) No periodic timer
Sep 19 15:43:20.769017 (XEN)   UNIT62 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.769086 (XEN)     VCPU62: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.780929 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.780987 (XEN) GICH_LRs (vcpu 62) mask=0
Sep 19 15:43:20.781049 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.792914 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.792971 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.793036 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.793079 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:20.793121 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:20.793162 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:20.804933 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:20.805012 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:20.805056 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.805097 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.805137 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.805178 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.816904 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.816959 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.817001 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.817043 (XEN) No periodic timer
Sep 19 15:43:20.817084 (XEN)   UNIT63 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.828926 (XEN)     VCPU63: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.828990 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.840921 (XEN) GICH_LRs (vcpu 63) mask=0
Sep 19 15:43:20.840981 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.841023 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.841086 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.841128 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.841170 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:20.852922 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:20.852978 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:20.853043 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:20.853085 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:20.853126 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.853167 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.864940 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.865016 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.865061 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.865103 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.865144 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.865185 (XEN) No periodic timer
Sep 19 15:43:20.876927 (XEN)   UNIT64 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.876989 (XEN)     VCPU64: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.888906 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.888966 (XEN) GICH_LRs (vcpu 64) mask=0
Sep 19 15:43:20.889011 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.889052 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.889092 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.900936 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.900992 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:20.901035 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:20.901075 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:20.901116 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:20.901156 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:20.912916 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.912972 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.913015 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.913056 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.913096 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.924928 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.924984 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.925027 (XEN) No periodic timer
Sep 19 15:43:20.925069 (XEN)   UNIT65 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.925115 (XEN)     VCPU65: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.936938 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.936996 (XEN) GICH_LRs (vcpu 65) mask=0
Sep 19 15:43:20.937041 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.948891 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.948946 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.948987 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.949028 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:20.949069 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:20.949109 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:20.960925 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:20.960981 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:20.961023 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:20.961064 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:20.961105 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:20.972921 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:20.972979 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:20.973022 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:20.973063 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:20.973103 (XEN) No periodic timer
Sep 19 15:43:20.973145 (XEN)   UNIT66 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:20.984949 (XEN)     VCPU66: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:20.985014 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:20.996938 (XEN) GICH_LRs (vcpu 66) mask=0
Sep 19 15:43:20.996996 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:20.997039 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:20.997080 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:20.997120 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:20.997161 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.008924 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.008979 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.009021 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.009062 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.009103 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.009144 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.020922 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.020978 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.021021 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.021062 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.021102 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.021143 (XEN) No periodic timer
Sep 19 15:43:21.032922 (XEN)   UNIT67 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.032983 (XEN)     VCPU67: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.044907 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.044967 (XEN) GICH_LRs (vcpu 67) mask=0
Sep 19 15:43:21.045012 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.045053 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.056931 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.056987 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.057029 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.057070 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.057110 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.057151 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.068939 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.068995 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.069038 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.069080 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.069121 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.069161 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.080927 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.080983 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.081026 (XEN) No periodic timer
Sep 19 15:43:21.081068 (XEN)   UNIT68 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.081114 (XEN)     VCPU68: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.092948 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.093007 (XEN) GICH_LRs (vcpu 68) mask=0
Sep 19 15:43:21.104935 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.104991 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.105033 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.105074 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.105114 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.105155 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.116937 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.116993 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.117036 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.117076 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.117117 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.117158 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.128892 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.128948 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.128991 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.129032 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.129072 (XEN) No periodic timer
Sep 19 15:43:21.129113 (XEN)   UNIT69 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.140939 (XEN)     VCPU69: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.141003 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.152933 (XEN) GICH_LRs (vcpu 69) mask=0
Sep 19 15:43:21.152991 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.153034 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.153074 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.153114 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.153154 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.164928 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.164982 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.165024 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.165064 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.165104 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.176925 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.176981 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.177023 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.177063 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.177121 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.177165 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.188928 (XEN) No periodic timer
Sep 19 15:43:21.188984 (XEN)   UNIT70 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.189031 (XEN)     VCPU70: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.200931 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.200989 (XEN) GICH_LRs (vcpu 70) mask=0
Sep 19 15:43:21.201033 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.201074 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.212926 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.212981 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.213023 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.213063 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.213103 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.213143 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.224920 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.224975 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.225017 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.225058 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.225098 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.225138 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.236924 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.236979 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.237021 (XEN) No periodic timer
Sep 19 15:43:21.237062 (XEN)   UNIT71 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.248926 (XEN)     VCPU71: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.248990 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.249035 (XEN) GICH_LRs (vcpu 71) mask=0
Sep 19 15:43:21.260923 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.260978 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.261020 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.261061 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.261101 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.261141 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.272919 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.272974 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.273016 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.273056 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.273096 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.273136 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.284935 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.284991 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.285033 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.285073 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.285114 (XEN) No periodic timer
Sep 19 15:43:21.285155 (XEN)   UNIT72 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.296917 (XEN)     VCPU72: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.296980 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.308938 (XEN) GICH_LRs (vcpu 72) mask=0
Sep 19 15:43:21.308995 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.309037 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.309078 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.309119 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.320929 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.320984 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.321026 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.321066 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.321106 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.321145 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.332929 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.332984 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.333025 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.333066 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.333106 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.344924 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.344980 (XEN) No periodic timer
Sep 19 15:43:21.345022 (XEN)   UNIT73 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.345068 (XEN)     VCPU73: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.356910 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.356967 (XEN) GICH_LRs (vcpu 73) mask=0
Sep 19 15:43:21.357012 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.357052 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.368938 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.368993 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.369035 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.369075 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.369114 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.369154 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.380939 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.380994 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.381053 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.381097 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.381137 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.381177 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.392923 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.392978 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.393019 (XEN) No periodic timer
Sep 19 15:43:21.393061 (XEN)   UNIT74 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.404925 (XEN)     VCPU74: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.404989 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.405034 (XEN) GICH_LRs (vcpu 74) mask=0
Sep 19 15:43:21.416926 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.416981 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.417023 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.417063 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.417103 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.417142 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.428919 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.428974 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.429016 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.429056 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.429097 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.440927 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.440983 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.441025 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.441065 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.441105 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.441146 (XEN) No periodic timer
Sep 19 15:43:21.452929 (XEN)   UNIT75 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.452990 (XEN)     VCPU75: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.464936 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.464995 (XEN) GICH_LRs (vcpu 75) mask=0
Sep 19 15:43:21.465039 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.465080 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.465120 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.476920 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.476976 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.477018 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.477058 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.477098 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.477137 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.488922 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.488977 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.489020 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.489060 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.489100 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.489140 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.500927 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.500983 (XEN) No periodic timer
Sep 19 15:43:21.501025 (XEN)   UNIT76 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.501072 (XEN)     VCPU76: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.512934 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.512991 (XEN) GICH_LRs (vcpu 76) mask=0
Sep 19 15:43:21.513035 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.513075 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.524877 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.524932 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.524974 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.525014 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.525054 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.525094 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.536924 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.536979 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.537021 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.537061 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.537101 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.548887 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.548945 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.548988 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.549029 (XEN) No periodic timer
Sep 19 15:43:21.549071 (XEN)   UNIT77 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.560783 (XEN)     VCPU77: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.560783 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.572785 (XEN) GICH_LRs (vcpu 77) mask=0
Sep 19 15:43:21.572785 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.572785 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.572785 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.572785 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.572785 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.584784 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.584784 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.584784 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.584784 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.584784 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.584784 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.596723 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.596723 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.596723 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.596723 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.596723 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.596723 (XEN) No periodic timer
Sep 19 15:43:21.608724 (XEN)   UNIT78 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.608724 (XEN)     VCPU78: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.620725 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.620725 (XEN) GICH_LRs (vcpu 78) mask=0
Sep 19 15:43:21.620725 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.620725 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.620725 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.632725 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.632725 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.632725 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.632725 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.632725 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.632725 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.644724 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.644724 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.644724 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.644724 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.644724 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.644724 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.656723 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.656723 (XEN) No periodic timer
Sep 19 15:43:21.656723 (XEN)   UNIT79 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.656723 (XEN)     VCPU79: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.668782 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.668782 (XEN) GICH_LRs (vcpu 79) mask=0
Sep 19 15:43:21.668782 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.680772 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.680772 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.680772 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.680772 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.680772 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.680772 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.692780 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.692780 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.692780 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.692780 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.692780 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.704781 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.704781 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.704781 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.704781 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.704781 (XEN) No periodic timer
Sep 19 15:43:21.704781 (XEN)   UNIT80 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.716784 (XEN)     VCPU80: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.716784 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.728779 (XEN) GICH_LRs (vcpu 80) mask=0
Sep 19 15:43:21.728779 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.728779 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.728779 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.728779 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.728779 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.740780 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.740780 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.740780 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.740780 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.740780 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.740780 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.752775 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.752775 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.752775 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.752914 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.752917 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.752917 (XEN) No periodic timer
Sep 19 15:43:21.764782 (XEN)   UNIT81 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.764782 (XEN)     VCPU81: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.776781 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.776781 (XEN) GICH_LRs (vcpu 81) mask=0
Sep 19 15:43:21.776781 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.776781 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.776781 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.788779 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.788779 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.788779 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.788779 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.788779 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.788779 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.800772 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.800772 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.800772 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.800772 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.800772 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.812784 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.812784 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.812784 (XEN) No periodic timer
Sep 19 15:43:21.812784 (XEN)   UNIT82 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.812784 (XEN)     VCPU82: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.824780 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.824780 (XEN) GICH_LRs (vcpu 82) mask=0
Sep 19 15:43:21.836781 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.836781 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.836781 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.836781 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.836781 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.836781 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.848913 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.848974 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.849017 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.849058 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.849097 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.849137 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.860779 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.860779 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.860779 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.860779 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.860779 (XEN) No periodic timer
Sep 19 15:43:21.860779 (XEN)   UNIT83 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.872786 (XEN)     VCPU83: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.872786 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.884782 (XEN) GICH_LRs (vcpu 83) mask=0
Sep 19 15:43:21.884782 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.884782 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.884782 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.884782 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.884782 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.896781 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.896781 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.896934 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.896939 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.896976 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.896999 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.908784 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.908784 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.908784 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.908784 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.908784 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.920783 (XEN) No periodic timer
Sep 19 15:43:21.920783 (XEN)   UNIT84 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.920783 (XEN)     VCPU84: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.932735 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.932735 (XEN) GICH_LRs (vcpu 84) mask=0
Sep 19 15:43:21.932735 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.932735 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.944783 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.944783 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.944783 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.944783 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:21.944783 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:21.944783 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:21.956783 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:21.956783 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:21.956783 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:21.956783 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:21.956783 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:21.956783 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:21.968783 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:21.968783 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:21.968783 (XEN) No periodic timer
Sep 19 15:43:21.968783 (XEN)   UNIT85 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:21.980784 (XEN)     VCPU85: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:21.980784 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:21.980784 (XEN) GICH_LRs (vcpu 85) mask=0
Sep 19 15:43:21.992785 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:21.992785 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:21.992785 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:21.992785 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:21.992785 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:21.992785 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:22.004788 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:22.004788 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:22.004788 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:22.004788 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:22.004788 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:22.004788 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:22.016787 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:22.016787 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:22.016787 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:22.016787 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:22.016787 (XEN) No periodic timer
Sep 19 15:43:22.016787 (XEN)   UNIT86 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:22.028782 (XEN)     VCPU86: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:22.028782 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:22.040785 (XEN) GICH_LRs (vcpu 86) mask=0
Sep 19 15:43:22.040785 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:22.040785 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:22.040785 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:22.040785 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:22.052777 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:22.052777 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:22.052777 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:22.052777 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:22.052777 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:22.052777 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:22.064785 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:22.064785 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:22.064785 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:22.064785 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:22.064785 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:22.076783 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:22.076783 (XEN) No periodic timer
Sep 19 15:43:22.076783 (XEN)   UNIT87 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:22.076783 (XEN)     VCPU87: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:22.088783 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:22.088783 (XEN) GICH_LRs (vcpu 87) mask=0
Sep 19 15:43:22.088783 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:22.088783 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:22.100783 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:22.100783 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:22.100783 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:22.100783 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:22.100783 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:22.100783 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:22.112787 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:22.112787 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:22.112787 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:22.112787 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:22.112787 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:22.112787 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:22.124783 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:22.124783 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:22.124783 (XEN) No periodic timer
Sep 19 15:43:22.124783 (XEN)   UNIT88 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:22.136791 (XEN)     VCPU88: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:22.136791 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:22.136791 (XEN) GICH_LRs (vcpu 88) mask=0
Sep 19 15:43:22.148781 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:22.148781 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:22.148781 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:22.148781 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:22.148781 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:22.148781 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:22.160768 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:22.160768 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:22.160768 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:22.160768 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:22.160768 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:22.160768 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:22.172784 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:22.172784 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:22.172784 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:22.172784 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:22.172784 (XEN) No periodic timer
Sep 19 15:43:22.172784 (XEN)   UNIT89 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:22.184775 (XEN)     VCPU89: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:22.196784 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:22.196784 (XEN) GICH_LRs (vcpu 89) mask=0
Sep 19 15:43:22.196784 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:22.196784 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:22.196784 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:22.208782 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:22.208782 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:22.208782 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:22.208782 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:22.208782 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:22.208782 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:22.220782 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:22.220782 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:22.220782 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:22.220782 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:22.220782 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:22.220782 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:22.232783 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:22.232783 (XEN) No periodic timer
Sep 19 15:43:22.232783 (XEN)   UNIT90 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:22.232783 (XEN)     VCPU90: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:22.244786 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:22.244786 (XEN) GICH_LRs (vcpu 90) mask=0
Sep 19 15:43:22.244786 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:22.244786 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:22.256789 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:22.256789 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:22.256789 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:22.256789 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:22.256789 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:22.256789 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:22.268999 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:22.269059 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:22.269101 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:22.269142 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:22.269183 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:22.280917 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:22.280973 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:22.281016 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:22.281057 (XEN) No periodic timer
Sep 19 15:43:22.281099 (XEN)   UNIT91 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:22.292922 (XEN)     VCPU91: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:22.292986 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:22.293031 (XEN) GICH_LRs (vcpu 91) mask=0
Sep 19 15:43:22.304923 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:22.304978 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:22.305020 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:22.305061 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:22.305102 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:22.305143 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:22.316929 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:22.316985 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:22.317027 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:22.317067 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:22.317107 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:22.328920 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:22.328976 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:22.329019 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:22.329059 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:22.329100 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:22.329141 (XEN) No periodic timer
Sep 19 15:43:22.340926 (XEN)   UNIT92 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:22.340986 (XEN)     VCPU92: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:22.352930 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:22.352988 (XEN) GICH_LRs (vcpu 92) mask=0
Sep 19 15:43:22.353033 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:22.353073 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:22.353113 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:22.364948 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:22.365004 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:22.365048 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:22.365089 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:22.365130 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:22.365171 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:22.376936 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:22.377010 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:22.377056 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:22.377098 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:22.377138 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:22.377179 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:22.388930 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:22.388985 (XEN) No periodic timer
Sep 19 15:43:22.389028 (XEN)   UNIT93 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:22.389075 (XEN)     VCPU93: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:22.400940 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:22.400998 (XEN) GICH_LRs (vcpu 93) mask=0
Sep 19 15:43:22.401043 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:22.412930 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:22.412986 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:22.413028 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:22.413069 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:22.413109 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:22.413149 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:22.424935 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:22.424991 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:22.425033 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:22.425074 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:22.425115 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:22.425155 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:22.436925 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:22.436981 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:22.437023 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:22.437064 (XEN) No periodic timer
Sep 19 15:43:22.437105 (XEN)   UNIT94 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:22.448939 (XEN)     VCPU94: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:22.449002 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:22.460925 (XEN) GICH_LRs (vcpu 94) mask=0
Sep 19 15:43:22.460983 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:22.461026 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:22.461066 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:22.461106 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:22.461146 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:22.472926 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:22.472981 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:22.473023 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:22.473064 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:22.473105 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:22.473145 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:22.484918 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:22.484973 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:22.485015 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:22.485055 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:22.485095 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:22.496925 (XEN) No periodic timer
Sep 19 15:43:22.496982 (XEN)   UNIT95 affinities: hard={0-95} soft={0-95}
Sep 19 15:43:22.497029 (XEN)     VCPU95: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 19 15:43:22.508919 (XEN)     pause_count=0 pause_flags=1
Sep 19 15:43:22.508978 (XEN) GICH_LRs (vcpu 95) mask=0
Sep 19 15:43:22.509022 (XEN)    VCPU_LR[0]=0
Sep 19 15:43:22.509063 (XEN)    VCPU_LR[1]=0
Sep 19 15:43:22.509104 (XEN)    VCPU_LR[2]=0
Sep 19 15:43:22.524975 (XEN)    VCPU_LR[3]=0
Sep 19 15:43:22.525031 (XEN)    VCPU_LR[4]=0
Sep 19 15:43:22.525073 (XEN)    VCPU_LR[5]=0
Sep 19 15:43:22.525113 (XEN)    VCPU_LR[6]=0
Sep 19 15:43:22.525153 (XEN)    VCPU_LR[7]=0
Sep 19 15:43:22.525194 (XEN)    VCPU_LR[8]=0
Sep 19 15:43:22.525234 (XEN)    VCPU_LR[9]=0
Sep 19 15:43:22.525274 (XEN)    VCPU_LR[10]=0
Sep 19 15:43:22.532904 (XEN)    VCPU_LR[11]=0
Sep 19 15:43:22.532960 (XEN)    VCPU_LR[12]=0
Sep 19 15:43:22.533003 (XEN)    VCPU_LR[13]=0
Sep 19 15:43:22.533044 (XEN)    VCPU_LR[14]=0
Sep 19 15:43:22.545023 (XEN)    VCPU_LR[15]=0
Sep 19 15:43:22.545079 (XEN) No periodic timer
Sep 19 15:43:22.545122 (XEN) Notifying guest 0:0 (virq 1, port 0)
Sep 19 15:43:22.545167 (XEN) Notifying guest 0:1 (virq 1, port 0)
Sep 19 15:43:22.556904 (XEN) Notifying guest 0:2 (virq 1, port 0)
Sep 19 15:43:22.556965 (XEN) Notifying guest 0:3 (virq 1, port 0)
Sep 19 15:43:22.557011 (XEN) Notifying guest 0:4 (virq 1, port 0)
Sep 19 15:43:22.568773 (XEN) Notifying guest 0:5 (virq 1, port 0)
Sep 19 15:43:22.568773 (XEN) Notifying guest 0:6 (virq 1, port 0)
Sep 19 15:43:22.568773 (XEN) Notifying guest 0:7 (virq 1, port 0)
Sep 19 15:43:22.580782 (XEN) Notifying guest 0:8 (virq 1, port 0)
Sep 19 15:43:22.580782 (XEN) Notifying guest 0:9 (virq 1, port 0)
Sep 19 15:43:22.580782 (XEN) Notifying guest 0:10 (virq 1, port 0)
Sep 19 15:43:22.592785 (XEN) Notifying guest 0:11 (virq 1, port 0)
Sep 19 15:43:22.592785 (XEN) Notifying guest 0:12 (virq 1, port 0)
Sep 19 15:43:22.592785 (XEN) Notifying guest 0:13 (virq 1, port 0)
Sep 19 15:43:22.604786 (XEN) Notifying guest 0:14 (virq 1, port 0)
Sep 19 15:43:22.604786 (XEN) Notifying guest 0:15 (virq 1, port 0)
Sep 19 15:43:22.604786 (XEN) Notifying guest 0:16 (virq 1, port 0)
Sep 19 15:43:22.616786 (XEN) Notifying guest 0:17 (virq 1, port 0)
Sep 19 15:43:22.616786 (XEN) Notifying guest 0:18 (virq 1, port 0)
Sep 19 15:43:22.616786 (XEN) Notifying guest 0:19 (virq 1, port 0)
Sep 19 15:43:22.628781 (XEN) Notifying guest 0:20 (virq 1, port 0)
Sep 19 15:43:22.628781 (XEN) Notifying guest 0:21 (virq 1, port 0)
Sep 19 15:43:22.628781 (XEN) Notifying guest 0:22 (virq 1, port 0)
Sep 19 15:43:22.640781 (XEN) Notifying guest 0:23 (virq 1, port 0)
Sep 19 15:43:22.640781 (XEN) Notifying guest 0:24 (virq 1, port 0)
Sep 19 15:43:22.640781 (XEN) Notifying guest 0:25 (virq 1, port 0)
Sep 19 15:43:22.652784 (XEN) Notifying guest 0:26 (virq 1, port 0)
Sep 19 15:43:22.652784 (XEN) Notifying guest 0:27 (virq 1, port 0)
Sep 19 15:43:22.652784 (XEN) Notifying guest 0:28 (virq 1, port 0)
Sep 19 15:43:22.664784 (XEN) Notifying guest 0:29 (virq 1, port 0)
Sep 19 15:43:22.664784 (XEN) Notifying guest 0:30 (virq 1, port 0)
Sep 19 15:43:22.664784 (XEN) Notifying guest 0:31 (virq 1, port 0)
Sep 19 15:43:22.664784 (XEN) Notifying guest 0:32 (virq 1, port 0)
Sep 19 15:43:22.676783 (XEN) Notifying guest 0:33 (virq 1, port 0)
Sep 19 15:43:22.676783 (XEN) Notifying guest 0:34 (virq 1, port 0)
Sep 19 15:43:22.676783 (XEN) Notifying guest 0:35 (virq 1, port 0)
Sep 19 15:43:22.688775 (XEN) Notifying guest 0:36 (virq 1, port 0)
Sep 19 15:43:22.688775 (XEN) Notifying guest 0:37 (virq 1, port 0)
Sep 19 15:43:22.700783 (XEN) Notifying guest 0:38 (virq 1, port 0)
Sep 19 15:43:22.700783 (XEN) Notifying guest 0:39 (virq 1, port 0)
Sep 19 15:43:22.700783 (XEN) Notifying guest 0:40 (virq 1, port 0)
Sep 19 15:43:22.712767 (XEN) Notifying guest 0:41 (virq 1, port 0)
Sep 19 15:43:22.712767 (XEN) Notifying guest 0:42 (virq 1, port 0)
Sep 19 15:43:22.712767 (XEN) Notifying guest 0:43 (virq 1, port 0)
Sep 19 15:43:22.724782 (XEN) Notifying guest 0:44 (virq 1, port 0)
Sep 19 15:43:22.724782 (XEN) Notifying guest 0:45 (virq 1, port 0)
Sep 19 15:43:22.724782 (XEN) Notifying guest 0:46 (virq 1, port 0)
Sep 19 15:43:22.736783 (XEN) Notifying guest 0:47 (virq 1, port 0)
Sep 19 15:43:22.736783 (XEN) Notifying guest 0:48 (virq 1, port 0)
Sep 19 15:43:22.736783 (XEN) Notifying guest 0:49 (virq 1, port 0)
Sep 19 15:43:22.736783 (XEN) Notifying guest 0:50 (virq 1, port 0)
Sep 19 15:43:22.748777 (XEN) Notifying guest 0:51 (virq 1, port 0)
Sep 19 15:43:22.748777 (XEN) Notifying guest 0:52 (virq 1, port 0)
Sep 19 15:43:22.748777 (XEN) Notifying guest 0:53 (virq 1, port 0)
Sep 19 15:43:22.760782 (XEN) Notifying guest 0:54 (virq 1, port 0)
Sep 19 15:43:22.760782 (XEN) Notifying guest 0:55 (virq 1, port 0)
Sep 19 15:43:22.760782 (XEN) Notifying guest 0:56 (virq 1, port 0)
Sep 19 15:43:22.772788 (XEN) Notifying guest 0:57 (virq 1, port 0)
Sep 19 15:43:22.772788 (XEN) Notifying guest 0:58 (virq 1, port 0)
Sep 19 15:43:22.772788 (XEN) Notifying guest 0:59 (virq 1, port 0)
Sep 19 15:43:22.784783 (XEN) Notifying guest 0:60 (virq 1, port 0)
Sep 19 15:43:22.784783 (XEN) Notifying guest 0:61 (virq 1, port 0)
Sep 19 15:43:22.784783 (XEN) Notifying guest 0:62 (virq 1, port 0)
Sep 19 15:43:22.796783 (XEN) Notifying guest 0:63 (virq 1, port 0)
Sep 19 15:43:22.796783 (XEN) Notifying guest 0:64 (virq 1, port 0)
Sep 19 15:43:22.796783 (XEN) Notifying guest 0:65 (virq 1, port 0)
Sep 19 15:43:22.808776 (XEN) Notifying guest 0:66 (virq 1, port 0)
Sep 19 15:43:22.808776 (XEN) Notifying guest 0:67 (virq 1, port 0)
Sep 19 15:43:22.808776 (XEN) Notifying guest 0:68 (virq 1, port 0)
Sep 19 15:43:22.820774 (XEN) Notifying guest 0:69 (virq 1, port 0)
Sep 19 15:43:22.820774 (XEN) Notifying guest 0:70 (virq 1, port 0)
Sep 19 15:43:22.820774 (XEN) Notifying guest 0:71 (virq 1, port 0)
Sep 19 15:43:22.832782 (XEN) Notifying guest 0:72 (virq 1, port 0)
Sep 19 15:43:22.832782 (XEN) Notifying guest 0:73 (virq 1, port 0)
Sep 19 15:43:22.832782 (XEN) Notifying guest 0:74 (virq 1, port 0)
Sep 19 15:43:22.844805 (XEN) Notifying guest 0:75 (virq 1, port 0)
Sep 19 15:43:22.844805 (XEN) Notifying guest 0:76 (virq 1, port 0)
Sep 19 15:43:22.844805 (XEN) Notifying guest 0:77 (virq 1, port 0)
Sep 19 15:43:22.856770 (XEN) Notifying guest 0:78 (virq 1, port 0)
Sep 19 15:43:22.856770 (XEN) Notifying guest 0:79 (virq 1, port 0)
Sep 19 15:43:22.856770 (XEN) Notifying guest 0:80 (virq 1, port 0)
Sep 19 15:43:22.868782 (XEN) Notifying guest 0:81 (virq 1, port 0)
Sep 19 15:43:22.868782 (XEN) Notifying guest 0:82 (virq 1, port 0)
Sep 19 15:43:22.868782 (XEN) Notifying guest 0:83 (virq 1, port 0)
Sep 19 15:43:22.880781 (XEN) Notifying guest 0:84 (virq 1, port 0)
Sep 19 15:43:22.880781 (XEN) Notifying guest 0:85 (virq 1, port 0)
Sep 19 15:43:22.880781 (XEN) Notifying guest 0:86 (virq 1, port 0)
Sep 19 15:43:22.892778 (XEN) Notifying guest 0:87 (virq 1, port 0)
Sep 19 15:43:22.892778 (XEN) Notifying guest 0:88 (virq 1, port 0)
Sep 19 15:43:22.892778 (XEN) Notifying guest 0:89 (virq 1, port 0)
Sep 19 15:43:22.904779 (XEN) Notifying guest 0:90 (virq 1, port 0)
Sep 19 15:43:22.904779 (XEN) Notifying guest 0:91 (virq 1, port 0)
Sep 19 15:43:22.904779 (XEN) Notifying guest 0:92 (virq 1, port 0)
Sep 19 15:43:22.916719 (XEN) Notifying guest 0:93 (virq 1, port 0)
Sep 19 15:43:22.916719 (XEN) Notifying guest 0:94 (virq 1, port 0)
Sep 19 15:43:22.916719 (XEN) Notifying guest 0:95 (virq 1, port 0)
Sep 19 15:43:22.928719 Sep 19 15:43:29.430243 <client 0x1a615f0 connected - now 1 clients>
(XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input)
Sep 19 15:43:29.444880 Sep 19 15:43:29.446157 <client 0x1a615f0 disconnected - now 0 clients>