Sep 25 00:52:51.359546 (XEN) UNIT79 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.359841 (XEN) VCPU79: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.368668 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.368668 (XEN) GICH_LRs (vcpu 79) mask=0 Sep 25 00:52:51.368668 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.380698 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.380698 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.380698 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.380698 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.380698 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.380698 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.392662 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.392662 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.392662 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.392662 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.392662 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.404664 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.404664 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.404664 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.404664 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.404664 (XEN) No periodic timer Sep 25 00:52:51.404664 (XEN) UNIT80 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.416662 (XEN) VCPU80: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.416662 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.428663 (XEN) GICH_LRs (vcpu 80) mask=0 Sep 25 00:52:51.428663 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.428663 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.428663 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.428663 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.428663 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.440659 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.440659 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.440659 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.440659 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.440659 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.440659 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.452660 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.452660 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.452660 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.452660 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.452660 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.452660 (XEN) No periodic timer Sep 25 00:52:51.464663 (XEN) UNIT81 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.464663 (XEN) VCPU81: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.476664 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.476664 (XEN) GICH_LRs (vcpu 81) mask=0 Sep 25 00:52:51.476664 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.476664 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.476664 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.488701 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.488701 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.488701 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.488701 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.488701 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.488701 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.500650 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.500650 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.500650 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.500650 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.500650 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.512661 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.512661 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.512661 (XEN) No periodic timer Sep 25 00:52:51.512661 (XEN) UNIT82 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.512661 (XEN) VCPU82: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.524660 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.524660 (XEN) GICH_LRs (vcpu 82) mask=0 Sep 25 00:52:51.536663 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.536663 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.536663 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.536663 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.536663 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.536663 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.548663 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.548663 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.548663 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.548663 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.548663 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.548663 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.560660 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.560660 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.560660 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.560660 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.560660 (XEN) No periodic timer Sep 25 00:52:51.560660 (XEN) UNIT83 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.572661 (XEN) VCPU83: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.572661 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.584662 (XEN) GICH_LRs (vcpu 83) mask=0 Sep 25 00:52:51.584662 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.584662 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.584662 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.584662 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.584662 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.596663 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.596663 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.596663 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.596663 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.596663 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.596663 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.608710 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.608710 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.608710 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.608710 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.608710 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.620932 (XEN) No periodic timer Sep 25 00:52:51.620996 (XEN) UNIT84 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.621067 (XEN) VCPU84: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.632887 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.632946 (XEN) GICH_LRs (vcpu 84) mask=0 Sep 25 00:52:51.632991 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.633032 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.644885 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.644941 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.644983 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.645025 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.645067 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.645130 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.656920 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.656976 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.657019 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.657060 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.657124 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.657165 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.668919 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.668997 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.669040 (XEN) No periodic timer Sep 25 00:52:51.669081 (XEN) UNIT85 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.680916 (XEN) VCPU85: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.680981 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.681049 (XEN) GICH_LRs (vcpu 85) mask=0 Sep 25 00:52:51.692916 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.692973 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.693015 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.693056 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.693119 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.693161 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.704918 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.704974 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.705016 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.705079 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.705121 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.705162 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.716919 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.716975 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.717040 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.717082 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.717124 (XEN) No periodic timer Sep 25 00:52:51.717166 (XEN) UNIT86 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.728911 (XEN) VCPU86: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.728997 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.740925 (XEN) GICH_LRs (vcpu 86) mask=0 Sep 25 00:52:51.740983 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.741025 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.741065 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.741127 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.752903 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.752960 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.753003 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.753046 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.753127 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.753172 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.764926 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.764982 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.765025 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.765088 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.765131 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.776916 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.776973 (XEN) No periodic timer Sep 25 00:52:51.777016 (XEN) UNIT87 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.777086 (XEN) VCPU87: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.788915 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.788974 (XEN) GICH_LRs (vcpu 87) mask=0 Sep 25 00:52:51.789020 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.789061 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.800919 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.800975 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.801017 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.801058 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.801098 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.801161 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.812924 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.812980 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.813022 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.813062 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.813125 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.813167 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.824916 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.824973 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.825015 (XEN) No periodic timer Sep 25 00:52:51.825080 (XEN) UNIT88 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.836879 (XEN) VCPU88: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.836943 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.836988 (XEN) GICH_LRs (vcpu 88) mask=0 Sep 25 00:52:51.848918 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.848996 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.849040 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.849082 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.849123 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.849164 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.860915 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.860972 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.861014 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.861056 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.861097 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.861138 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.872912 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.872968 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.873011 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.873053 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.873094 (XEN) No periodic timer Sep 25 00:52:51.873136 (XEN) UNIT89 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.884908 (XEN) VCPU89: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.896928 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.896988 (XEN) GICH_LRs (vcpu 89) mask=0 Sep 25 00:52:51.897033 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.897075 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.897116 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.908920 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.908977 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.909019 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.909060 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.909101 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.909142 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.920915 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.920972 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.921014 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.921055 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.921096 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.921137 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.932915 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.932972 (XEN) No periodic timer Sep 25 00:52:51.933016 (XEN) UNIT90 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.933063 (XEN) VCPU90: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.944943 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.945003 (XEN) GICH_LRs (vcpu 90) mask=0 Sep 25 00:52:51.945060 (XEN) VCPU_LR[0]=0 Sep 25 00:52:51.945105 (XEN) VCPU_LR[1]=0 Sep 25 00:52:51.956924 (XEN) VCPU_LR[2]=0 Sep 25 00:52:51.956979 (XEN) VCPU_LR[3]=0 Sep 25 00:52:51.957039 (XEN) VCPU_LR[4]=0 Sep 25 00:52:51.957083 (XEN) VCPU_LR[5]=0 Sep 25 00:52:51.957123 (XEN) VCPU_LR[6]=0 Sep 25 00:52:51.957164 (XEN) VCPU_LR[7]=0 Sep 25 00:52:51.968921 (XEN) VCPU_LR[8]=0 Sep 25 00:52:51.968977 (XEN) VCPU_LR[9]=0 Sep 25 00:52:51.969019 (XEN) VCPU_LR[10]=0 Sep 25 00:52:51.969060 (XEN) VCPU_LR[11]=0 Sep 25 00:52:51.969101 (XEN) VCPU_LR[12]=0 Sep 25 00:52:51.980925 (XEN) VCPU_LR[13]=0 Sep 25 00:52:51.980983 (XEN) VCPU_LR[14]=0 Sep 25 00:52:51.981026 (XEN) VCPU_LR[15]=0 Sep 25 00:52:51.981067 (XEN) No periodic timer Sep 25 00:52:51.981109 (XEN) UNIT91 affinities: hard={0-95} soft={0-95} Sep 25 00:52:51.992912 (XEN) VCPU91: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:51.992976 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:51.993022 (XEN) GICH_LRs (vcpu 91) mask=0 Sep 25 00:52:52.004856 (XEN) VCPU_LR[0]=0 Sep 25 00:52:52.004912 (XEN) VCPU_LR[1]=0 Sep 25 00:52:52.004955 (XEN) VCPU_LR[2]=0 Sep 25 00:52:52.004996 (XEN) VCPU_LR[3]=0 Sep 25 00:52:52.005037 (XEN) VCPU_LR[4]=0 Sep 25 00:52:52.005078 (XEN) VCPU_LR[5]=0 Sep 25 00:52:52.016911 (XEN) VCPU_LR[6]=0 Sep 25 00:52:52.016967 (XEN) VCPU_LR[7]=0 Sep 25 00:52:52.017010 (XEN) VCPU_LR[8]=0 Sep 25 00:52:52.017051 (XEN) VCPU_LR[9]=0 Sep 25 00:52:52.017092 (XEN) VCPU_LR[10]=0 Sep 25 00:52:52.028918 (XEN) VCPU_LR[11]=0 Sep 25 00:52:52.028974 (XEN) VCPU_LR[12]=0 Sep 25 00:52:52.029016 (XEN) VCPU_LR[13]=0 Sep 25 00:52:52.029057 (XEN) VCPU_LR[14]=0 Sep 25 00:52:52.029099 (XEN) VCPU_LR[15]=0 Sep 25 00:52:52.029140 (XEN) No periodic timer Sep 25 00:52:52.040914 (XEN) UNIT92 affinities: hard={0-95} soft={0-95} Sep 25 00:52:52.040976 (XEN) VCPU92: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:52.052928 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:52.052988 (XEN) GICH_LRs (vcpu 92) mask=0 Sep 25 00:52:52.053033 (XEN) VCPU_LR[0]=0 Sep 25 00:52:52.053075 (XEN) VCPU_LR[1]=0 Sep 25 00:52:52.053115 (XEN) VCPU_LR[2]=0 Sep 25 00:52:52.064916 (XEN) VCPU_LR[3]=0 Sep 25 00:52:52.064973 (XEN) VCPU_LR[4]=0 Sep 25 00:52:52.065015 (XEN) VCPU_LR[5]=0 Sep 25 00:52:52.065056 (XEN) VCPU_LR[6]=0 Sep 25 00:52:52.065096 (XEN) VCPU_LR[7]=0 Sep 25 00:52:52.065137 (XEN) VCPU_LR[8]=0 Sep 25 00:52:52.076917 (XEN) VCPU_LR[9]=0 Sep 25 00:52:52.076974 (XEN) VCPU_LR[10]=0 Sep 25 00:52:52.077017 (XEN) VCPU_LR[11]=0 Sep 25 00:52:52.077058 (XEN) VCPU_LR[12]=0 Sep 25 00:52:52.077099 (XEN) VCPU_LR[13]=0 Sep 25 00:52:52.077140 (XEN) VCPU_LR[14]=0 Sep 25 00:52:52.088911 (XEN) VCPU_LR[15]=0 Sep 25 00:52:52.088967 (XEN) No periodic timer Sep 25 00:52:52.089010 (XEN) UNIT93 affinities: hard={0-95} soft={0-95} Sep 25 00:52:52.089057 (XEN) VCPU93: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:52.100925 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:52.100984 (XEN) GICH_LRs (vcpu 93) mask=0 Sep 25 00:52:52.101029 (XEN) VCPU_LR[0]=0 Sep 25 00:52:52.112913 (XEN) VCPU_LR[1]=0 Sep 25 00:52:52.112970 (XEN) VCPU_LR[2]=0 Sep 25 00:52:52.113012 (XEN) VCPU_LR[3]=0 Sep 25 00:52:52.113054 (XEN) VCPU_LR[4]=0 Sep 25 00:52:52.113095 (XEN) VCPU_LR[5]=0 Sep 25 00:52:52.113136 (XEN) VCPU_LR[6]=0 Sep 25 00:52:52.124913 (XEN) VCPU_LR[7]=0 Sep 25 00:52:52.124969 (XEN) VCPU_LR[8]=0 Sep 25 00:52:52.125012 (XEN) VCPU_LR[9]=0 Sep 25 00:52:52.125053 (XEN) VCPU_LR[10]=0 Sep 25 00:52:52.125093 (XEN) VCPU_LR[11]=0 Sep 25 00:52:52.125133 (XEN) VCPU_LR[12]=0 Sep 25 00:52:52.136911 (XEN) VCPU_LR[13]=0 Sep 25 00:52:52.136967 (XEN) VCPU_LR[14]=0 Sep 25 00:52:52.137010 (XEN) VCPU_LR[15]=0 Sep 25 00:52:52.137050 (XEN) No periodic timer Sep 25 00:52:52.137091 (XEN) UNIT94 affinities: hard={0-95} soft={0-95} Sep 25 00:52:52.148912 (XEN) VCPU94: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:52.148976 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:52.160939 (XEN) GICH_LRs (vcpu 94) mask=0 Sep 25 00:52:52.160999 (XEN) VCPU_LR[0]=0 Sep 25 00:52:52.161042 (XEN) VCPU_LR[1]=0 Sep 25 00:52:52.161082 (XEN) VCPU_LR[2]=0 Sep 25 00:52:52.161122 (XEN) VCPU_LR[3]=0 Sep 25 00:52:52.161162 (XEN) VCPU_LR[4]=0 Sep 25 00:52:52.172916 (XEN) VCPU_LR[5]=0 Sep 25 00:52:52.172972 (XEN) VCPU_LR[6]=0 Sep 25 00:52:52.173013 (XEN) VCPU_LR[7]=0 Sep 25 00:52:52.173054 (XEN) VCPU_LR[8]=0 Sep 25 00:52:52.173095 (XEN) VCPU_LR[9]=0 Sep 25 00:52:52.173135 (XEN) VCPU_LR[10]=0 Sep 25 00:52:52.184916 (XEN) VCPU_LR[11]=0 Sep 25 00:52:52.184971 (XEN) VCPU_LR[12]=0 Sep 25 00:52:52.185014 (XEN) VCPU_LR[13]=0 Sep 25 00:52:52.185054 (XEN) VCPU_LR[14]=0 Sep 25 00:52:52.185095 (XEN) VCPU_LR[15]=0 Sep 25 00:52:52.196914 (XEN) No periodic timer Sep 25 00:52:52.196971 (XEN) UNIT95 affinities: hard={0-95} soft={0-95} Sep 25 00:52:52.197020 (XEN) VCPU95: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Sep 25 00:52:52.208922 (XEN) pause_count=0 pause_flags=1 Sep 25 00:52:52.208980 (XEN) GICH_LRs (vcpu 95) mask=0 Sep 25 00:52:52.209025 (XEN) VCPU_LR[0]=0 Sep 25 00:52:52.209066 (XEN) VCPU_LR[1]=0 Sep 25 00:52:52.209107 (XEN) VCPU_LR[2]=0 Sep 25 00:52:52.220921 (XEN) VCPU_LR[3]=0 Sep 25 00:52:52.220977 (XEN) VCPU_LR[4]=0 Sep 25 00:52:52.221019 (XEN) VCPU_LR[5]=0 Sep 25 00:52:52.221059 (XEN) VCPU_LR[6]=0 Sep 25 00:52:52.221100 (XEN) VCPU_LR[7]=0 Sep 25 00:52:52.221140 (XEN) VCPU_LR[8]=0 Sep 25 00:52:52.232926 (XEN) VCPU_LR[9]=0 Sep 25 00:52:52.232981 (XEN) VCPU_LR[10]=0 Sep 25 00:52:52.233024 (XEN) VCPU_LR[11]=0 Sep 25 00:52:52.233065 (XEN) VCPU_LR[12]=0 Sep 25 00:52:52.233105 (XEN) VCPU_LR[13]=0 Sep 25 00:52:52.233146 (XEN) VCPU_LR[14]=0 Sep 25 00:52:52.244922 (XEN) VCPU_LR[15]=0 Sep 25 00:52:52.244978 (XEN) No periodic timer Sep 25 00:52:52.245021 (XEN) Notifying guest 0:0 (virq 1, port 0) Sep 25 00:52:52.245066 (XEN) Notifying guest 0:1 (virq 1, port 0) Sep 25 00:52:52.256933 (XEN) Notifying guest 0:2 (virq 1, port 0) Sep 25 00:52:52.256992 (XEN) Notifying guest 0:3 (virq 1, port 0) Sep 25 00:52:52.257037 (XEN) Notifying guest 0:4 (virq 1, port 0) Sep 25 00:52:52.268909 (XEN) Notifying guest 0:5 (virq 1, port 0) Sep 25 00:52:52.268969 (XEN) Notifying guest 0:6 (virq 1, port 0) Sep 25 00:52:52.269015 (XEN) Notifying guest 0:7 (virq 1, port 0) Sep 25 00:52:52.280920 (XEN) Notifying guest 0:8 (virq 1, port 0) Sep 25 00:52:52.280979 (XEN) Notifying guest 0:9 (virq 1, port 0) Sep 25 00:52:52.281024 (XEN) Notifying guest 0:10 (virq 1, port 0) Sep 25 00:52:52.292910 (XEN) Notifying guest 0:11 (virq 1, port 0) Sep 25 00:52:52.292970 (XEN) Notifying guest 0:12 (virq 1, port 0) Sep 25 00:52:52.293015 (XEN) Notifying guest 0:13 (virq 1, port 0) Sep 25 00:52:52.304920 (XEN) Notifying guest 0:14 (virq 1, port 0) Sep 25 00:52:52.304979 (XEN) Notifying guest 0:15 (virq 1, port 0) Sep 25 00:52:52.305024 (XEN) Notifying guest 0:16 (virq 1, port 0) Sep 25 00:52:52.316928 (XEN) Notifying guest 0:17 (virq 1, port 0) Sep 25 00:52:52.316988 (XEN) Notifying guest 0:18 (virq 1, port 0) Sep 25 00:52:52.317034 (XEN) Notifying guest 0:19 (virq 1, port 0) Sep 25 00:52:52.328917 (XEN) Notifying guest 0:20 (virq 1, port 0) Sep 25 00:52:52.328977 (XEN) Notifying guest 0:21 (virq 1, port 0) Sep 25 00:52:52.329022 (XEN) Notifying guest 0:22 (virq 1, port 0) Sep 25 00:52:52.340907 (XEN) Notifying guest 0:23 (virq 1, port 0) Sep 25 00:52:52.340968 (XEN) Notifying guest 0:24 (virq 1, port 0) Sep 25 00:52:52.341013 (XEN) Notifying guest 0:25 (virq 1, port 0) Sep 25 00:52:52.352912 (XEN) Notifying guest 0:26 (virq 1, port 0) Sep 25 00:52:52.352973 (XEN) Notifying guest 0:27 (virq 1, port 0) Sep 25 00:52:52.353018 (XEN) Notifying guest 0:28 (virq 1, port 0) Sep 25 00:52:52.353062 (XEN) Notifying guest 0:29 (virq 1, port 0) Sep 25 00:52:52.364921 (XEN) Notifying guest 0:30 (virq 1, port 0) Sep 25 00:52:52.364980 (XEN) Notifying guest 0:31 (virq 1, port 0) Sep 25 00:52:52.365025 (XEN) Notifying guest 0:32 (virq 1, port 0) Sep 25 00:52:52.376937 (XEN) Notifying guest 0:33 (virq 1, port 0) Sep 25 00:52:52.376998 (XEN) Notifying guest 0:34 (virq 1, port 0) Sep 25 00:52:52.377043 (XEN) Notifying guest 0:35 (virq 1, port 0) Sep 25 00:52:52.388914 (XEN) Notifying guest 0:36 (virq 1, port 0) Sep 25 00:52:52.388973 (XEN) Notifying guest 0:37 (virq 1, port 0) Sep 25 00:52:52.400926 (XEN) Notifying guest 0:38 (virq 1, port 0) Sep 25 00:52:52.400986 (XEN) Notifying guest 0:39 (virq 1, port 0) Sep 25 00:52:52.401032 (XEN) Notifying guest 0:40 (virq 1, port 0) Sep 25 00:52:52.412916 (XEN) Notifying guest 0:41 (virq 1, port 0) Sep 25 00:52:52.412976 (XEN) Notifying guest 0:42 (virq 1, port 0) Sep 25 00:52:52.413022 (XEN) Notifying guest 0:43 (virq 1, port 0) Sep 25 00:52:52.424913 (XEN) Notifying guest 0:44 (virq 1, port 0) Sep 25 00:52:52.424974 (XEN) Notifying guest 0:45 (virq 1, port 0) Sep 25 00:52:52.425020 (XEN) Notifying guest 0:46 (virq 1, port 0) Sep 25 00:52:52.425064 (XEN) Notifying guest 0:47 (virq 1, port 0) Sep 25 00:52:52.436926 (XEN) Notifying guest 0:48 (virq 1, port 0) Sep 25 00:52:52.436985 (XEN) Notifying guest 0:49 (virq 1, port 0) Sep 25 00:52:52.437030 (XEN) Notifying guest 0:50 (virq 1, port 0) Sep 25 00:52:52.448927 (XEN) Notifying guest 0:51 (virq 1, port 0) Sep 25 00:52:52.448986 (XEN) Notifying guest 0:52 (virq 1, port 0) Sep 25 00:52:52.449031 (XEN) Notifying guest 0:53 (virq 1, port 0) Sep 25 00:52:52.460924 (XEN) Notifying guest 0:54 (virq 1, port 0) Sep 25 00:52:52.460983 (XEN) Notifying guest 0:55 (virq 1, port 0) Sep 25 00:52:52.461028 (XEN) Notifying guest 0:56 (virq 1, port 0) Sep 25 00:52:52.472926 (XEN) Notifying guest 0:57 (virq 1, port 0) Sep 25 00:52:52.472985 (XEN) Notifying guest 0:58 (virq 1, port 0) Sep 25 00:52:52.473029 (XEN) Notifying guest 0:59 (virq 1, port 0) Sep 25 00:52:52.484923 (XEN) Notifying guest 0:60 (virq 1, port 0) Sep 25 00:52:52.484983 (XEN) Notifying guest 0:61 (virq 1, port 0) Sep 25 00:52:52.485028 (XEN) Notifying guest 0:62 (virq 1, port 0) Sep 25 00:52:52.496922 (XEN) Notifying guest 0:63 (virq 1, port 0) Sep 25 00:52:52.496981 (XEN) Notifying guest 0:64 (virq 1, port 0) Sep 25 00:52:52.497026 (XEN) Notifying guest 0:65 (virq 1, port 0) Sep 25 00:52:52.508914 (XEN) Notifying guest 0:66 (virq 1, port 0) Sep 25 00:52:52.508973 (XEN) Notifying guest 0:67 (virq 1, port 0) Sep 25 00:52:52.509018 (XEN) Notifying guest 0:68 (virq 1, port 0) Sep 25 00:52:52.520906 (XEN) Notifying guest 0:69 (virq 1, port 0) Sep 25 00:52:52.520966 (XEN) Notifying guest 0:70 (virq 1, port 0) Sep 25 00:52:52.521011 (XEN) Notifying guest 0:71 (virq 1, port 0) Sep 25 00:52:52.532919 (XEN) Notifying guest 0:72 (virq 1, port 0) Sep 25 00:52:52.532978 (XEN) Notifying guest 0:73 (virq 1, port 0) Sep 25 00:52:52.533023 (XEN) Notifying guest 0:74 (virq 1, port 0) Sep 25 00:52:52.544927 (XEN) Notifying guest 0:75 (virq 1, port 0) Sep 25 00:52:52.544985 (XEN) Notifying guest 0:76 (virq 1, port 0) Sep 25 00:52:52.545031 (XEN) Notifying guest 0:77 (virq 1, port 0) Sep 25 00:52:52.556932 (XEN) Notifying guest 0:78 (virq 1, port 0) Sep 25 00:52:52.556991 (XEN) Notifying guest 0:79 (virq 1, port 0) Sep 25 00:52:52.557036 (XEN) Notifying guest 0:80 (virq 1, port 0) Sep 25 00:52:52.568927 (XEN) Notifying guest 0:81 (virq 1, port 0) Sep 25 00:52:52.568986 (XEN) Notifying guest 0:82 (virq 1, port 0) Sep 25 00:52:52.569031 (XEN) Notifying guest 0:83 (virq 1, port 0) Sep 25 00:52:52.580920 (XEN) Notifying guest 0:84 (virq 1, port 0) Sep 25 00:52:52.580980 (XEN) Notifying guest 0:85 (virq 1, port 0) Sep 25 00:52:52.581025 (XEN) Notifying guest 0:86 (virq 1, port 0) Sep 25 00:52:52.592917 (XEN) Notifying guest 0:87 (virq 1, port 0) Sep 25 00:52:52.592977 (XEN) Notifying guest 0:88 (virq 1, port 0) Sep 25 00:52:52.593022 (XEN) Notifying guest 0:89 (virq 1, port 0) Sep 25 00:52:52.604920 (XEN) Notifying guest 0:90 (virq 1, port 0) Sep 25 00:52:52.604980 (XEN) Notifying guest 0:91 (virq 1, port 0) Sep 25 00:52:52.605025 (XEN) Notifying guest 0:92 (virq 1, port 0) Sep 25 00:52:52.616930 (XEN) Notifying guest 0:93 (virq 1, port 0) Sep 25 00:52:52.616991 (XEN) Notifying guest 0:94 (virq 1, port 0) Sep 25 00:52:52.617036 (XEN) Notifying guest 0:95 (virq 1, port 0) Sep 25 00:52:52.628857 Sep 25 00:52:59.156569 (XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input) Sep 25 00:52:59.180710 Sep 25 00:52:59.180710 rochester0 login: Sep 25 00:52:59.180710