Sep 26 06:27:57.691476 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:57.691555 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:57.691600 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:57.691641 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:57.703391 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:57.703391 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:57.703391 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:57.703391 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:57.703391 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:57.712885 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:57.712965 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:57.713009 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:57.713050 (XEN) No periodic timer
Sep 26 06:27:57.713092 (XEN)   UNIT14 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:57.724890 (XEN)     VCPU14: CPU36 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:57.724977 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:57.736849 (XEN) GICH_LRs (vcpu 14) mask=0
Sep 26 06:27:57.736908 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:57.736951 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:57.736992 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:57.737054 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:57.737096 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:57.748855 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:57.748911 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:57.748954 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:57.749017 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:57.749059 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:57.749099 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:57.760865 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:57.760921 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:57.760963 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:57.761027 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:57.763695 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:57.763749 (XEN) No periodic timer
Sep 26 06:27:57.772858 (XEN)   UNIT15 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:57.772920 (XEN)     VCPU15: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:57.784851 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:57.784910 (XEN) GICH_LRs (vcpu 15) mask=0
Sep 26 06:27:57.784954 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:57.784996 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:57.785057 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:57.796852 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:57.796908 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:57.796950 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:57.796990 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:57.797031 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:57.797094 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:57.808856 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:57.808912 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:57.808954 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:57.808995 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:57.809058 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:57.809099 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:57.820859 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:57.820914 (XEN) No periodic timer
Sep 26 06:27:57.820957 (XEN)   UNIT16 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:57.821027 (XEN)     VCPU16: CPU70 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:57.832861 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:57.832920 (XEN) GICH_LRs (vcpu 16) mask=0
Sep 26 06:27:57.832964 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:57.844859 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:57.844937 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:57.844981 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:57.845023 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:57.845064 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:57.856850 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:57.856930 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:57.856974 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:57.857015 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:57.857054 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:57.857076 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:57.868851 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:57.868908 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:57.868951 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:57.868991 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:57.869032 (XEN) No periodic timer
Sep 26 06:27:57.869096 (XEN)   UNIT17 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:57.880860 (XEN)     VCPU17: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:57.880925 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:57.892858 (XEN) GICH_LRs (vcpu 17) mask=0
Sep 26 06:27:57.892937 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:57.892984 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:57.893037 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:57.893103 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:57.893187 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:57.908887 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:57.908943 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:57.908985 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:57.909026 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:57.909090 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:57.909131 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:57.909172 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:57.909212 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:57.926040 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:57.926040 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:57.926040 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:57.926040 (XEN) No periodic timer
Sep 26 06:27:57.926040 (XEN)   UNIT18 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:57.926040 (XEN)     VCPU18: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:57.943570 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:57.943635 (XEN) GICH_LRs (vcpu 18) mask=0
Sep 26 06:27:57.943681 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:57.943722 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:57.943763 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:57.955573 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:57.955630 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:57.955673 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:57.955714 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:57.955755 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:57.955818 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:57.967557 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:57.967613 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:57.967656 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:57.967697 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:57.967761 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:57.967803 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:57.979581 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:57.979637 (XEN) No periodic timer
Sep 26 06:27:57.979681 (XEN)   UNIT19 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:57.991580 (XEN)     VCPU19: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:57.991647 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:57.991693 (XEN) GICH_LRs (vcpu 19) mask=0
Sep 26 06:27:58.003578 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.003634 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.003700 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.003743 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.003783 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.003824 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.015575 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.015654 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.015699 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.015741 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.015782 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.015822 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.027579 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.027636 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.027685 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.027725 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.027766 (XEN) No periodic timer
Sep 26 06:27:58.027831 (XEN)   UNIT20 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.039585 (XEN)     VCPU20: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.039651 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.051569 (XEN) GICH_LRs (vcpu 20) mask=0
Sep 26 06:27:58.051627 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.051694 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.051737 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.051777 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.051818 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.063583 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.063661 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.063705 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.063746 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.063787 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.063827 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.075580 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.075658 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.075702 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.075743 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.075784 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.087583 (XEN) No periodic timer
Sep 26 06:27:58.087662 (XEN)   UNIT21 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.087730 (XEN)     VCPU21: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.099576 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.099635 (XEN) GICH_LRs (vcpu 21) mask=0
Sep 26 06:27:58.099681 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.099745 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.111581 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.111637 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.111680 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.111722 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.111785 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.111827 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.123579 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.123635 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.123677 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.123742 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.123785 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.123826 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.135578 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.135635 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.135700 (XEN) No periodic timer
Sep 26 06:27:58.135744 (XEN)   UNIT22 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.147570 (XEN)     VCPU22: CPU70 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.147635 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.147681 (XEN) GICH_LRs (vcpu 22) mask=0
Sep 26 06:27:58.159575 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.159632 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.159675 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.159716 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.159757 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.159820 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.171578 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.171634 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.171677 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.171718 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.171782 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.171824 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.183581 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.183637 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.183680 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.183721 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.183761 (XEN) No periodic timer
Sep 26 06:27:58.183802 (XEN)   UNIT23 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.195581 (XEN)     VCPU23: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.195645 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.207590 (XEN) GICH_LRs (vcpu 23) mask=0
Sep 26 06:27:58.207648 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.207692 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.207733 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.207774 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.219577 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.219633 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.219676 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.219717 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.219758 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.219798 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.231571 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.231628 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.231672 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.231713 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.231754 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.243577 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.243633 (XEN) No periodic timer
Sep 26 06:27:58.243677 (XEN)   UNIT24 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.243724 (XEN)     VCPU24: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.255578 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.255637 (XEN) GICH_LRs (vcpu 24) mask=0
Sep 26 06:27:58.255682 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.255723 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.267590 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.267645 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.267689 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.267730 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.267770 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.267811 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.279582 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.279638 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.279681 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.279722 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.279763 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.279804 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.291596 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.291653 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.291696 (XEN) No periodic timer
Sep 26 06:27:58.291738 (XEN)   UNIT25 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.303576 (XEN)     VCPU25: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.303640 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.303686 (XEN) GICH_LRs (vcpu 25) mask=0
Sep 26 06:27:58.315578 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.315635 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.315677 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.315718 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.315758 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.315798 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.327582 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.327637 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.327680 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.327720 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.327761 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.327801 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.339582 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.339638 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.339681 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.339721 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.339762 (XEN) No periodic timer
Sep 26 06:27:58.339804 (XEN)   UNIT26 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.351579 (XEN)     VCPU26: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.363580 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.363640 (XEN) GICH_LRs (vcpu 26) mask=0
Sep 26 06:27:58.363685 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.363726 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.363766 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.375578 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.375634 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.375677 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.375717 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.375758 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.375798 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.387577 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.387634 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.387678 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.387719 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.387760 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.387801 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.399570 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.399626 (XEN) No periodic timer
Sep 26 06:27:58.399671 (XEN)   UNIT27 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.399718 (XEN)     VCPU27: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.411590 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.411649 (XEN) GICH_LRs (vcpu 27) mask=0
Sep 26 06:27:58.411695 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.423582 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.423638 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.423682 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.423722 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.423763 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.423803 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.435574 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.435631 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.435674 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.435715 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.435755 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.435796 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.447581 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.447637 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.447680 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.447721 (XEN) No periodic timer
Sep 26 06:27:58.447762 (XEN)   UNIT28 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.459576 (XEN)     VCPU28: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.459641 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.459686 (XEN) GICH_LRs (vcpu 28) mask=0
Sep 26 06:27:58.471581 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.471637 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.471680 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.471721 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.471761 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.471801 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.483573 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.483628 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.483671 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.483729 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.483772 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.495582 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.495637 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.495680 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.495720 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.495761 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.495800 (XEN) No periodic timer
Sep 26 06:27:58.507575 (XEN)   UNIT29 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.507636 (XEN)     VCPU29: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.519597 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.519655 (XEN) GICH_LRs (vcpu 29) mask=0
Sep 26 06:27:58.519700 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.519741 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.519782 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.531580 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.531636 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.531678 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.531718 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.531759 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.531798 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.543579 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.543635 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.543678 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.543718 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.543759 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.543799 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.555574 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.555630 (XEN) No periodic timer
Sep 26 06:27:58.555673 (XEN)   UNIT30 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.555719 (XEN)     VCPU30: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.567584 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.567643 (XEN) GICH_LRs (vcpu 30) mask=0
Sep 26 06:27:58.567688 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.579579 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.579636 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.579679 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.579719 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.579759 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.579799 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.591586 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.591643 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.591685 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.591726 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.591766 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.591807 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.603574 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.603630 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.603673 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.603714 (XEN) No periodic timer
Sep 26 06:27:58.603755 (XEN)   UNIT31 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.615576 (XEN)     VCPU31: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.615640 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.627575 (XEN) GICH_LRs (vcpu 31) mask=0
Sep 26 06:27:58.627634 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.627677 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.627717 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.627757 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.627797 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.639582 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.639637 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.639679 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.639719 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.639759 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.639799 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.651579 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.651635 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.651677 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.651718 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.651758 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.663581 (XEN) No periodic timer
Sep 26 06:27:58.663638 (XEN)   UNIT32 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.663709 (XEN)     VCPU32: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.675573 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.675631 (XEN) GICH_LRs (vcpu 32) mask=0
Sep 26 06:27:58.675676 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.675717 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.675758 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.687581 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.687637 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.687698 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.687742 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.687784 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.687824 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.699585 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.699641 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.699683 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.699724 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.699765 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.699806 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.711579 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.711635 (XEN) No periodic timer
Sep 26 06:27:58.711678 (XEN)   UNIT33 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.711725 (XEN)     VCPU33: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.723586 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.723644 (XEN) GICH_LRs (vcpu 33) mask=0
Sep 26 06:27:58.723689 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.735565 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.735621 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.735663 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.735704 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.735745 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.747577 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.747633 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.747676 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.747717 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.747756 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.747796 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.759467 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.759467 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.759467 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.759467 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.759467 (XEN) No periodic timer
Sep 26 06:27:58.759467 (XEN)   UNIT34 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.771605 (XEN)     VCPU34: CPU72 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.771673 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.783582 (XEN) GICH_LRs (vcpu 34) mask=0
Sep 26 06:27:58.783641 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.783685 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.783726 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.783766 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.795574 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.795631 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.795673 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.795714 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.795754 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.795794 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.807570 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.807627 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.807669 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.807710 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.807750 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.807789 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.819580 (XEN) No periodic timer
Sep 26 06:27:58.819637 (XEN)   UNIT35 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.819685 (XEN)     VCPU35: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.831582 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.831641 (XEN) GICH_LRs (vcpu 35) mask=0
Sep 26 06:27:58.831686 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.831727 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.831768 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.843601 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.843656 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.843698 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.843739 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.843779 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.843819 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.855575 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.855631 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.855673 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.855714 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.855754 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.867562 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.867620 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.867664 (XEN) No periodic timer
Sep 26 06:27:58.867706 (XEN)   UNIT36 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.879579 (XEN)     VCPU36: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.879644 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.879690 (XEN) GICH_LRs (vcpu 36) mask=0
Sep 26 06:27:58.891591 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.891648 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.891691 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.891732 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.891772 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.891813 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.903575 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.903631 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.903674 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.903714 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.903754 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.903794 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.915572 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.915628 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.915671 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.915711 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.915751 (XEN) No periodic timer
Sep 26 06:27:58.915792 (XEN)   UNIT37 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.927579 (XEN)     VCPU37: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.927643 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.939592 (XEN) GICH_LRs (vcpu 37) mask=0
Sep 26 06:27:58.939650 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.939692 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.939733 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.939773 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.951590 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.951646 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.951689 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.951730 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:58.951770 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:58.951809 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:58.963580 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:58.963637 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:58.963679 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:58.963719 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:58.963760 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:58.963800 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:58.975576 (XEN) No periodic timer
Sep 26 06:27:58.975632 (XEN)   UNIT38 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:58.975697 (XEN)     VCPU38: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:58.987570 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:58.987629 (XEN) GICH_LRs (vcpu 38) mask=0
Sep 26 06:27:58.987673 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:58.987714 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:58.999583 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:58.999639 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:58.999682 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:58.999723 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:58.999763 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:58.999803 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.011593 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.011648 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.011690 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.011731 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.011771 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.023581 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.023638 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.023681 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.023722 (XEN) No periodic timer
Sep 26 06:27:59.023763 (XEN)   UNIT39 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.035578 (XEN)     VCPU39: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.035642 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.035688 (XEN) GICH_LRs (vcpu 39) mask=0
Sep 26 06:27:59.047575 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.047632 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.047674 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.047715 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.047755 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.047794 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.059581 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.059637 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.059679 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.059719 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.059759 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.059799 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.071485 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.071485 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.071485 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.071485 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.071485 (XEN) No periodic timer
Sep 26 06:27:59.083472 (XEN)   UNIT40 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.083472 (XEN)     VCPU40: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.083472 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.095478 (XEN) GICH_LRs (vcpu 40) mask=0
Sep 26 06:27:59.095478 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.095478 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.095478 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.095478 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.107477 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.107477 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.107477 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.107477 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.107477 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.107477 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.119460 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.119460 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.119460 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.119460 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.119460 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.131476 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.131476 (XEN) No periodic timer
Sep 26 06:27:59.131476 (XEN)   UNIT41 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.131476 (XEN)     VCPU41: CPU9 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.143472 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.143472 (XEN) GICH_LRs (vcpu 41) mask=0
Sep 26 06:27:59.143472 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.155473 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.155473 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.155473 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.155473 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.155473 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.155473 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.167480 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.167480 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.167480 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.167480 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.167480 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.167480 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.179534 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.179596 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.179639 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.179679 (XEN) No periodic timer
Sep 26 06:27:59.179720 (XEN)   UNIT42 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.191475 (XEN)     VCPU42: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.191475 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.191475 (XEN) GICH_LRs (vcpu 42) mask=0
Sep 26 06:27:59.203473 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.203473 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.203473 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.203473 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.203473 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.203473 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.215474 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.215474 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.215474 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.215474 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.215474 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.215474 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.227472 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.227472 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.227472 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.227472 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.227472 (XEN) No periodic timer
Sep 26 06:27:59.239466 (XEN)   UNIT43 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.239466 (XEN)     VCPU43: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.251470 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.251470 (XEN) GICH_LRs (vcpu 43) mask=0
Sep 26 06:27:59.251470 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.251470 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.251470 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.263477 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.263477 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.263477 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.263477 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.263477 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.263477 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.275473 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.275473 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.275473 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.275473 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.275473 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.275473 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.287480 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.287480 (XEN) No periodic timer
Sep 26 06:27:59.287480 (XEN)   UNIT44 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.287480 (XEN)     VCPU44: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.299475 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.299475 (XEN) GICH_LRs (vcpu 44) mask=0
Sep 26 06:27:59.299475 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.311476 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.311476 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.311476 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.311476 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.311476 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.311476 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.323475 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.323475 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.323475 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.323475 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.323475 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.323475 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.335476 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.335476 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.335476 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.335476 (XEN) No periodic timer
Sep 26 06:27:59.335476 (XEN)   UNIT45 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.347473 (XEN)     VCPU45: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.347473 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.347473 (XEN) GICH_LRs (vcpu 45) mask=0
Sep 26 06:27:59.359472 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.359472 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.359472 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.359472 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.359472 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.371465 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.371465 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.371465 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.371465 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.371465 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.371465 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.383476 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.383476 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.383476 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.383476 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.383476 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.395476 (XEN) No periodic timer
Sep 26 06:27:59.395476 (XEN)   UNIT46 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.395476 (XEN)     VCPU46: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.407475 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.407475 (XEN) GICH_LRs (vcpu 46) mask=0
Sep 26 06:27:59.407475 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.407475 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.407475 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.419477 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.419477 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.419477 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.419477 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.419477 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.419477 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.431582 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.431642 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.431685 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.431725 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.431765 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.431806 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.443478 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.443478 (XEN) No periodic timer
Sep 26 06:27:59.443478 (XEN)   UNIT47 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.443478 (XEN)     VCPU47: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.455468 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.455468 (XEN) GICH_LRs (vcpu 47) mask=0
Sep 26 06:27:59.455468 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.467477 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.467477 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.467477 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.467477 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.467477 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.467477 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.479472 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.479472 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.479472 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.479472 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.479472 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.479472 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.495482 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.495482 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.495482 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.495482 (XEN) No periodic timer
Sep 26 06:27:59.495482 (XEN)   UNIT48 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.495482 (XEN)     VCPU48: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.507473 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.507473 (XEN) GICH_LRs (vcpu 48) mask=0
Sep 26 06:27:59.519471 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.519471 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.519471 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.519471 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.519471 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.519471 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.531478 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.531478 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.531478 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.531478 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.531478 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.531478 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.543481 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.543481 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.543481 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.543481 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.543481 (XEN) No periodic timer
Sep 26 06:27:59.543481 (XEN)   UNIT49 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.555476 (XEN)     VCPU49: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.555476 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.567478 (XEN) GICH_LRs (vcpu 49) mask=0
Sep 26 06:27:59.567478 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.567478 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.567478 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.567478 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.567478 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.579473 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.579473 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.579473 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.579473 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.579473 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.579473 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.591476 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.591476 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.591476 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.591476 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.591476 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.603472 (XEN) No periodic timer
Sep 26 06:27:59.603472 (XEN)   UNIT50 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.603472 (XEN)     VCPU50: CPU34 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.615475 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.615475 (XEN) GICH_LRs (vcpu 50) mask=0
Sep 26 06:27:59.615475 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.615475 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.615475 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.627467 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.627467 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.627467 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.627467 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.627467 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.639479 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.639479 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.639479 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.639479 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.639479 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.639479 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.651477 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.651477 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.651477 (XEN) No periodic timer
Sep 26 06:27:59.651477 (XEN)   UNIT51 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.663470 (XEN)     VCPU51: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.663470 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.663470 (XEN) GICH_LRs (vcpu 51) mask=0
Sep 26 06:27:59.675471 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.675471 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.675471 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.675471 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.675471 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.675471 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.687477 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.687477 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.687477 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.687477 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.687477 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.687477 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.699472 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.699472 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.699472 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.699472 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.699472 (XEN) No periodic timer
Sep 26 06:27:59.699472 (XEN)   UNIT52 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.711473 (XEN)     VCPU52: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.711473 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.727497 (XEN) GICH_LRs (vcpu 52) mask=0
Sep 26 06:27:59.727497 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.727497 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.727497 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.727497 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.727497 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.727497 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.739446 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.739446 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.739446 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.739446 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.739446 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.739446 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.751467 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.751467 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.751467 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.751467 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.751467 (XEN) No periodic timer
Sep 26 06:27:59.763469 (XEN)   UNIT53 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.763469 (XEN)     VCPU53: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.763469 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.775471 (XEN) GICH_LRs (vcpu 53) mask=0
Sep 26 06:27:59.775471 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.775471 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.775471 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.775471 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.787474 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.787474 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.787474 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.787474 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.787474 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.787474 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.799491 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.799491 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.799491 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.799491 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.799491 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.811475 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.811475 (XEN) No periodic timer
Sep 26 06:27:59.811475 (XEN)   UNIT54 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.811475 (XEN)     VCPU54: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.823476 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.823476 (XEN) GICH_LRs (vcpu 54) mask=0
Sep 26 06:27:59.823476 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.823476 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.835473 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.835473 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.835473 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.835473 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.835473 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.835473 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.847478 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.847478 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.847478 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.847478 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.847478 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.847478 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.859485 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.859485 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.859485 (XEN) No periodic timer
Sep 26 06:27:59.859485 (XEN)   UNIT55 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.871474 (XEN)     VCPU55: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.871474 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.871474 (XEN) GICH_LRs (vcpu 55) mask=0
Sep 26 06:27:59.883462 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.883462 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.883462 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.883462 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.883462 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.895473 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.895473 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.895473 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.895473 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.895473 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.895473 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.907474 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.907474 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.907474 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.907474 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.907474 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.907474 (XEN) No periodic timer
Sep 26 06:27:59.919488 (XEN)   UNIT56 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.919488 (XEN)     VCPU56: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.919488 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.931470 (XEN) GICH_LRs (vcpu 56) mask=0
Sep 26 06:27:59.931470 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.931470 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.931470 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.943475 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.943475 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.943475 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.943475 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.943475 (XEN)    VCPU_LR[7]=0
Sep 26 06:27:59.943475 (XEN)    VCPU_LR[8]=0
Sep 26 06:27:59.955473 (XEN)    VCPU_LR[9]=0
Sep 26 06:27:59.955473 (XEN)    VCPU_LR[10]=0
Sep 26 06:27:59.955473 (XEN)    VCPU_LR[11]=0
Sep 26 06:27:59.955473 (XEN)    VCPU_LR[12]=0
Sep 26 06:27:59.955473 (XEN)    VCPU_LR[13]=0
Sep 26 06:27:59.955473 (XEN)    VCPU_LR[14]=0
Sep 26 06:27:59.967476 (XEN)    VCPU_LR[15]=0
Sep 26 06:27:59.967476 (XEN) No periodic timer
Sep 26 06:27:59.967476 (XEN)   UNIT57 affinities: hard={0-95} soft={0-95}
Sep 26 06:27:59.967476 (XEN)     VCPU57: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:27:59.979490 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:27:59.979490 (XEN) GICH_LRs (vcpu 57) mask=0
Sep 26 06:27:59.979490 (XEN)    VCPU_LR[0]=0
Sep 26 06:27:59.979490 (XEN)    VCPU_LR[1]=0
Sep 26 06:27:59.991477 (XEN)    VCPU_LR[2]=0
Sep 26 06:27:59.991477 (XEN)    VCPU_LR[3]=0
Sep 26 06:27:59.991477 (XEN)    VCPU_LR[4]=0
Sep 26 06:27:59.991477 (XEN)    VCPU_LR[5]=0
Sep 26 06:27:59.991477 (XEN)    VCPU_LR[6]=0
Sep 26 06:27:59.991477 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.003463 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.003463 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.003463 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.003463 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.003463 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.015479 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.015479 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.015479 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.015479 (XEN) No periodic timer
Sep 26 06:28:00.015479 (XEN)   UNIT58 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.027472 (XEN)     VCPU58: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.027472 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.039478 (XEN) GICH_LRs (vcpu 58) mask=0
Sep 26 06:28:00.039478 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.039478 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.039478 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.039478 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.039478 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.051480 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.051480 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.051480 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.051480 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.051480 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.051480 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.063475 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.063475 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.063475 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.063475 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.063475 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.063475 (XEN) No periodic timer
Sep 26 06:28:00.075474 (XEN)   UNIT59 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.075474 (XEN)     VCPU59: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.087472 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.087472 (XEN) GICH_LRs (vcpu 59) mask=0
Sep 26 06:28:00.087472 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.087472 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.087472 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.099474 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.099474 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.099474 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.099474 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.099474 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.099474 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.111477 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.111477 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.111477 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.111477 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.111477 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.111477 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.123477 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.123477 (XEN) No periodic timer
Sep 26 06:28:00.123477 (XEN)   UNIT60 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.123477 (XEN)     VCPU60: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.135465 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.135465 (XEN) GICH_LRs (vcpu 60) mask=0
Sep 26 06:28:00.135465 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.147477 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.147477 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.147477 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.147477 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.147477 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.147477 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.159474 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.159474 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.159474 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.159474 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.159474 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.159474 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.171473 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.171473 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.171473 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.171473 (XEN) No periodic timer
Sep 26 06:28:00.171473 (XEN)   UNIT61 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.183471 (XEN)     VCPU61: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.183471 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.195478 (XEN) GICH_LRs (vcpu 61) mask=0
Sep 26 06:28:00.195478 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.195478 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.195478 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.195478 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.195478 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.207475 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.207475 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.207475 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.207475 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.207475 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.207475 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.219462 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.219462 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.219462 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.219462 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.219462 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.219462 (XEN) No periodic timer
Sep 26 06:28:00.231475 (XEN)   UNIT62 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.231475 (XEN)     VCPU62: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.243477 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.243477 (XEN) GICH_LRs (vcpu 62) mask=0
Sep 26 06:28:00.243477 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.243477 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.243477 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.255470 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.255470 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.255470 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.255470 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.255470 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.255470 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.267568 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.267629 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.267672 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.267713 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.267754 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.279462 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.279462 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.279462 (XEN) No periodic timer
Sep 26 06:28:00.279462 (XEN)   UNIT63 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.279462 (XEN)     VCPU63: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.291475 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.291475 (XEN) GICH_LRs (vcpu 63) mask=0
Sep 26 06:28:00.303479 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.303479 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.303479 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.303479 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.303479 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.303479 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.315471 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.315471 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.315471 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.315471 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.315471 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.315471 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.327472 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.327472 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.327472 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.327472 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.327472 (XEN) No periodic timer
Sep 26 06:28:00.327472 (XEN)   UNIT64 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.339466 (XEN)     VCPU64: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.339466 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.351477 (XEN) GICH_LRs (vcpu 64) mask=0
Sep 26 06:28:00.351477 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.351477 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.351477 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.351477 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.351477 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.363475 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.363475 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.363475 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.363475 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.363475 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.363475 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.375475 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.375475 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.375475 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.375475 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.375475 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.387466 (XEN) No periodic timer
Sep 26 06:28:00.387466 (XEN)   UNIT65 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.387466 (XEN)     VCPU65: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.399479 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.399479 (XEN) GICH_LRs (vcpu 65) mask=0
Sep 26 06:28:00.399479 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.399479 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.411471 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.411471 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.411471 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.411471 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.411471 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.411471 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.423478 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.423478 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.423478 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.423478 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.423478 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.423478 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.435476 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.435476 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.435476 (XEN) No periodic timer
Sep 26 06:28:00.435476 (XEN)   UNIT66 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.447475 (XEN)     VCPU66: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.447475 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.447475 (XEN) GICH_LRs (vcpu 66) mask=0
Sep 26 06:28:00.459476 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.459476 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.459476 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.459476 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.459476 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.459476 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.471475 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.471475 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.471475 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.471475 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.471475 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.471475 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.483476 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.483476 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.483476 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.483476 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.483476 (XEN) No periodic timer
Sep 26 06:28:00.483476 (XEN)   UNIT67 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.495476 (XEN)     VCPU67: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.495476 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.507469 (XEN) GICH_LRs (vcpu 67) mask=0
Sep 26 06:28:00.507469 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.507469 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.507469 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.507469 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.519467 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.519467 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.519467 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.519467 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.519467 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.519467 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.531476 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.531476 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.531476 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.531476 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.531476 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.543479 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.543479 (XEN) No periodic timer
Sep 26 06:28:00.543479 (XEN)   UNIT68 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.543479 (XEN)     VCPU68: CPU36 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.555472 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.555472 (XEN) GICH_LRs (vcpu 68) mask=0
Sep 26 06:28:00.555472 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.555472 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.567474 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.567474 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.567474 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.567474 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.567474 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.567474 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.579473 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.579473 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.579473 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.579473 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.579473 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.579473 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.591482 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.591482 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.591482 (XEN) No periodic timer
Sep 26 06:28:00.591482 (XEN)   UNIT69 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.603482 (XEN)     VCPU69: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.603482 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.603482 (XEN) GICH_LRs (vcpu 69) mask=0
Sep 26 06:28:00.615475 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.615475 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.615475 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.615475 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.615475 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.615475 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.627477 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.627477 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.627477 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.627477 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.627477 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.627477 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.639465 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.639465 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.639465 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.639465 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.639465 (XEN) No periodic timer
Sep 26 06:28:00.651481 (XEN)   UNIT70 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.651481 (XEN)     VCPU70: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.663475 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.663475 (XEN) GICH_LRs (vcpu 70) mask=0
Sep 26 06:28:00.663475 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.663475 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.663475 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.675471 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.675471 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.675471 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.675471 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.675471 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.675471 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.687477 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.687477 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.687477 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.687477 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.687477 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.687477 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.699423 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.699423 (XEN) No periodic timer
Sep 26 06:28:00.699423 (XEN)   UNIT71 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.699423 (XEN)     VCPU71: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.711472 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.711472 (XEN) GICH_LRs (vcpu 71) mask=0
Sep 26 06:28:00.711472 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.711472 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.723474 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.723474 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.723474 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.723474 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.723474 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.723474 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.735473 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.735473 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.735473 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.735473 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.735473 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.747479 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.747479 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.747479 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.747479 (XEN) No periodic timer
Sep 26 06:28:00.747479 (XEN)   UNIT72 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.759475 (XEN)     VCPU72: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.759475 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.759475 (XEN) GICH_LRs (vcpu 72) mask=0
Sep 26 06:28:00.771468 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.771468 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.771468 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.771468 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.771468 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.783479 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.783479 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.783479 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.783479 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.783479 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.783479 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.795477 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.795477 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.795477 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.795477 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.795477 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.795477 (XEN) No periodic timer
Sep 26 06:28:00.807473 (XEN)   UNIT73 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.807473 (XEN)     VCPU73: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.819477 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.819477 (XEN) GICH_LRs (vcpu 73) mask=0
Sep 26 06:28:00.819477 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.819477 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.819477 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.831476 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.831476 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.831476 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.831476 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.831476 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.831476 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.843479 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.843479 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.843479 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.843479 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.843479 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.843479 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.855471 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.855471 (XEN) No periodic timer
Sep 26 06:28:00.855471 (XEN)   UNIT74 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.855471 (XEN)     VCPU74: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.867475 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.867475 (XEN) GICH_LRs (vcpu 74) mask=0
Sep 26 06:28:00.867475 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.879478 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.879478 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.879478 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.879478 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.879478 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.879478 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.891464 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.891464 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.891464 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.891464 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.891464 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.891464 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.903473 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.903473 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.903473 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.903473 (XEN) No periodic timer
Sep 26 06:28:00.903473 (XEN)   UNIT75 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.915474 (XEN)     VCPU75: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.915474 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.927477 (XEN) GICH_LRs (vcpu 75) mask=0
Sep 26 06:28:00.927477 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.927477 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.927477 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.927477 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.927477 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.939478 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.939478 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.939478 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.939478 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.939478 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.939478 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.951470 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.951470 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.951470 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.951470 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:00.951470 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:00.963474 (XEN) No periodic timer
Sep 26 06:28:00.963474 (XEN)   UNIT76 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:00.963474 (XEN)     VCPU76: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:00.975478 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:00.975478 (XEN) GICH_LRs (vcpu 76) mask=0
Sep 26 06:28:00.975478 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:00.975478 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:00.975478 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:00.987469 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:00.987469 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:00.987469 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:00.987469 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:00.987469 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:00.987469 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:00.999474 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:00.999474 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:00.999474 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:00.999474 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:00.999474 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:00.999474 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.011463 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.011463 (XEN) No periodic timer
Sep 26 06:28:01.011463 (XEN)   UNIT77 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.011702 (XEN)     VCPU77: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.023467 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.023467 (XEN) GICH_LRs (vcpu 77) mask=0
Sep 26 06:28:01.035472 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.035472 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.035472 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.035472 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.035472 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.035472 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.047472 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.047472 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.047472 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.047472 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.047472 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.047472 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.059474 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.059474 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.059474 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.059474 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.059474 (XEN) No periodic timer
Sep 26 06:28:01.059474 (XEN)   UNIT78 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.071476 (XEN)     VCPU78: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.071476 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.083463 (XEN) GICH_LRs (vcpu 78) mask=0
Sep 26 06:28:01.083463 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.083463 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.083463 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.083463 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.083463 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.095474 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.095474 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.095474 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.095474 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.095474 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.095474 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.107476 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.107476 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.107476 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.107476 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.107476 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.119470 (XEN) No periodic timer
Sep 26 06:28:01.119470 (XEN)   UNIT79 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.119470 (XEN)     VCPU79: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.131479 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.131479 (XEN) GICH_LRs (vcpu 79) mask=0
Sep 26 06:28:01.131479 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.131479 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.131479 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.143478 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.143478 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.143478 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.143478 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.143478 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.143478 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.155464 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.155464 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.155464 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.155464 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.155464 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.167471 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.167471 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.167471 (XEN) No periodic timer
Sep 26 06:28:01.167471 (XEN)   UNIT80 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.179473 (XEN)     VCPU80: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.179473 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.179473 (XEN) GICH_LRs (vcpu 80) mask=0
Sep 26 06:28:01.191478 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.191478 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.191478 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.191478 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.191478 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.191478 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.203479 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.203479 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.203479 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.203479 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.203479 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.203479 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.215479 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.215479 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.215479 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.215479 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.215479 (XEN) No periodic timer
Sep 26 06:28:01.215479 (XEN)   UNIT81 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.227479 (XEN)     VCPU81: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.227479 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.239469 (XEN) GICH_LRs (vcpu 81) mask=0
Sep 26 06:28:01.239469 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.239469 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.239469 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.239469 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.251481 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.251481 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.251481 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.251481 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.251481 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.251481 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.263467 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.263467 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.263467 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.263467 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.263467 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.263467 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.275465 (XEN) No periodic timer
Sep 26 06:28:01.275465 (XEN)   UNIT82 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.275465 (XEN)     VCPU82: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.287480 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.287480 (XEN) GICH_LRs (vcpu 82) mask=0
Sep 26 06:28:01.287480 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.287480 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.299479 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.299479 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.299479 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.299479 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.299479 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.299479 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.311481 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.311481 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.311481 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.311481 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.311481 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.311481 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.323481 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.323481 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.323481 (XEN) No periodic timer
Sep 26 06:28:01.323481 (XEN)   UNIT83 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.335479 (XEN)     VCPU83: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.335479 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.335479 (XEN) GICH_LRs (vcpu 83) mask=0
Sep 26 06:28:01.347468 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.347468 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.347468 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.347468 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.347468 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.347468 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.359477 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.359477 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.359477 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.359477 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.359477 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.359477 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.371475 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.371475 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.371475 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.371475 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.371475 (XEN) No periodic timer
Sep 26 06:28:01.371475 (XEN)   UNIT84 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.383475 (XEN)     VCPU84: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.383475 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.395545 (XEN) GICH_LRs (vcpu 84) mask=0
Sep 26 06:28:01.395608 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.395652 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.395692 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.395732 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.407472 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.407472 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.407472 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.407472 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.407472 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.419474 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.419474 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.419474 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.419474 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.419474 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.419474 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.431462 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.431462 (XEN) No periodic timer
Sep 26 06:28:01.431462 (XEN)   UNIT85 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.431462 (XEN)     VCPU85: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.443475 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.443475 (XEN) GICH_LRs (vcpu 85) mask=0
Sep 26 06:28:01.443475 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.455473 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.455473 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.455473 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.455473 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.455473 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.455473 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.455473 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.467474 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.467474 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.467474 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.467474 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.467474 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.479473 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.479473 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.479473 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.479473 (XEN) No periodic timer
Sep 26 06:28:01.479473 (XEN)   UNIT86 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.491474 (XEN)     VCPU86: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.491474 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.491474 (XEN) GICH_LRs (vcpu 86) mask=0
Sep 26 06:28:01.503478 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.503478 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.503478 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.503478 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.503478 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.503478 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.515477 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.515477 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.515477 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.515477 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.515477 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.515477 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.527469 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.527469 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.527469 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.527469 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.527469 (XEN) No periodic timer
Sep 26 06:28:01.539480 (XEN)   UNIT87 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.539480 (XEN)     VCPU87: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.551471 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.551471 (XEN) GICH_LRs (vcpu 87) mask=0
Sep 26 06:28:01.551471 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.551471 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.551471 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.563475 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.563475 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.563475 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.563475 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.563475 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.563475 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.575474 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.575474 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.575474 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.575474 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.575474 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.575474 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.587475 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.587475 (XEN) No periodic timer
Sep 26 06:28:01.587475 (XEN)   UNIT88 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.587475 (XEN)     VCPU88: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.599482 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.599482 (XEN) GICH_LRs (vcpu 88) mask=0
Sep 26 06:28:01.599482 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.611483 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.611483 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.611483 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.611483 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.611483 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.611483 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.623484 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.623484 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.623484 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.623484 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.623484 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.623484 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.635476 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.635476 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.635476 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.635476 (XEN) No periodic timer
Sep 26 06:28:01.635476 (XEN)   UNIT89 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.647484 (XEN)     VCPU89: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.647484 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.647484 (XEN) GICH_LRs (vcpu 89) mask=0
Sep 26 06:28:01.659467 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.659467 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.659467 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.659467 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.659467 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.671472 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.671472 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.671472 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.671472 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.671472 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.671472 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.683599 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.683666 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.683666 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.683666 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.683769 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.695469 (XEN) No periodic timer
Sep 26 06:28:01.695469 (XEN)   UNIT90 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.695469 (XEN)     VCPU90: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.707485 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.707485 (XEN) GICH_LRs (vcpu 90) mask=0
Sep 26 06:28:01.707485 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.707485 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.707485 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.719480 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.719480 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.719480 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.719480 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.719480 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.719480 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.731477 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.731477 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.731477 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.731477 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.731477 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.731477 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.743480 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.743480 (XEN) No periodic timer
Sep 26 06:28:01.743480 (XEN)   UNIT91 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.743480 (XEN)     VCPU91: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.755476 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.755476 (XEN) GICH_LRs (vcpu 91) mask=0
Sep 26 06:28:01.755476 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.767461 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.767461 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.767461 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.767461 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.767461 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.767461 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.779483 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.779483 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.779483 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.779483 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.779483 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.779483 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.791469 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.791469 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.791469 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.791469 (XEN) No periodic timer
Sep 26 06:28:01.791469 (XEN)   UNIT92 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.803481 (XEN)     VCPU92: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.803481 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.815482 (XEN) GICH_LRs (vcpu 92) mask=0
Sep 26 06:28:01.815482 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.815482 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.815482 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.815482 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.827481 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.827481 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.827481 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.827481 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.827481 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.827481 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.839481 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.839481 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.839481 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.839481 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.839481 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.839481 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.851594 (XEN) No periodic timer
Sep 26 06:28:01.851655 (XEN)   UNIT93 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.851704 (XEN)     VCPU93: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.863575 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.863634 (XEN) GICH_LRs (vcpu 93) mask=0
Sep 26 06:28:01.863680 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.863721 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.863778 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.875573 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.875629 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.875672 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.875712 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.875753 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.875793 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.887577 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.887634 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.887690 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.887757 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.887825 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.887874 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.899576 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.899632 (XEN) No periodic timer
Sep 26 06:28:01.899675 (XEN)   UNIT94 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.899722 (XEN)     VCPU94: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.911585 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.911644 (XEN) GICH_LRs (vcpu 94) mask=0
Sep 26 06:28:01.923573 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.923630 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.923673 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.923714 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.923754 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.923795 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.935582 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.935638 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.935681 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.935722 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.935763 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.935803 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.947574 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.947630 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.947673 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.947715 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:01.947756 (XEN) No periodic timer
Sep 26 06:28:01.947797 (XEN)   UNIT95 affinities: hard={0-95} soft={0-95}
Sep 26 06:28:01.959599 (XEN)     VCPU95: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 
Sep 26 06:28:01.959664 (XEN)     pause_count=0 pause_flags=1
Sep 26 06:28:01.971582 (XEN) GICH_LRs (vcpu 95) mask=0
Sep 26 06:28:01.971640 (XEN)    VCPU_LR[0]=0
Sep 26 06:28:01.971683 (XEN)    VCPU_LR[1]=0
Sep 26 06:28:01.971724 (XEN)    VCPU_LR[2]=0
Sep 26 06:28:01.971765 (XEN)    VCPU_LR[3]=0
Sep 26 06:28:01.983580 (XEN)    VCPU_LR[4]=0
Sep 26 06:28:01.983637 (XEN)    VCPU_LR[5]=0
Sep 26 06:28:01.983680 (XEN)    VCPU_LR[6]=0
Sep 26 06:28:01.983722 (XEN)    VCPU_LR[7]=0
Sep 26 06:28:01.983762 (XEN)    VCPU_LR[8]=0
Sep 26 06:28:01.983803 (XEN)    VCPU_LR[9]=0
Sep 26 06:28:01.995578 (XEN)    VCPU_LR[10]=0
Sep 26 06:28:01.995635 (XEN)    VCPU_LR[11]=0
Sep 26 06:28:01.995678 (XEN)    VCPU_LR[12]=0
Sep 26 06:28:01.995719 (XEN)    VCPU_LR[13]=0
Sep 26 06:28:01.995759 (XEN)    VCPU_LR[14]=0
Sep 26 06:28:01.995800 (XEN)    VCPU_LR[15]=0
Sep 26 06:28:02.007573 (XEN) No periodic timer
Sep 26 06:28:02.007630 (XEN) Notifying guest 0:0 (virq 1, port 0)
Sep 26 06:28:02.007678 (XEN) Notifying guest 0:1 (virq 1, port 0)
Sep 26 06:28:02.007724 (XEN) Notifying guest 0:2 (virq 1, port 0)
Sep 26 06:28:02.019595 (XEN) Notifying guest 0:3 (virq 1, port 0)
Sep 26 06:28:02.019656 (XEN) Notifying guest 0:4 (virq 1, port 0)
Sep 26 06:28:02.019702 (XEN) Notifying guest 0:5 (virq 1, port 0)
Sep 26 06:28:02.031580 (XEN) Notifying guest 0:6 (virq 1, port 0)
Sep 26 06:28:02.031640 (XEN) Notifying guest 0:7 (virq 1, port 0)
Sep 26 06:28:02.031685 (XEN) Notifying guest 0:8 (virq 1, port 0)
Sep 26 06:28:02.043569 (XEN) Notifying guest 0:9 (virq 1, port 0)
Sep 26 06:28:02.043629 (XEN) Notifying guest 0:10 (virq 1, port 0)
Sep 26 06:28:02.043675 (XEN) Notifying guest 0:11 (virq 1, port 0)
Sep 26 06:28:02.055588 (XEN) Notifying guest 0:12 (virq 1, port 0)
Sep 26 06:28:02.055648 (XEN) Notifying guest 0:13 (virq 1, port 0)
Sep 26 06:28:02.055694 (XEN) Notifying guest 0:14 (virq 1, port 0)
Sep 26 06:28:02.067583 (XEN) Notifying guest 0:15 (virq 1, port 0)
Sep 26 06:28:02.067643 (XEN) Notifying guest 0:16 (virq 1, port 0)
Sep 26 06:28:02.067689 (XEN) Notifying guest 0:17 (virq 1, port 0)
Sep 26 06:28:02.079599 (XEN) Notifying guest 0:18 (virq 1, port 0)
Sep 26 06:28:02.079660 (XEN) Notifying guest 0:19 (virq 1, port 0)
Sep 26 06:28:02.079707 (XEN) Notifying guest 0:20 (virq 1, port 0)
Sep 26 06:28:02.091592 (XEN) Notifying guest 0:21 (virq 1, port 0)
Sep 26 06:28:02.091652 (XEN) Notifying guest 0:22 (virq 1, port 0)
Sep 26 06:28:02.091699 (XEN) Notifying guest 0:23 (virq 1, port 0)
Sep 26 06:28:02.103583 (XEN) Notifying guest 0:24 (virq 1, port 0)
Sep 26 06:28:02.103643 (XEN) Notifying guest 0:25 (virq 1, port 0)
Sep 26 06:28:02.103689 (XEN) Notifying guest 0:26 (virq 1, port 0)
Sep 26 06:28:02.115577 (XEN) Notifying guest 0:27 (virq 1, port 0)
Sep 26 06:28:02.115637 (XEN) Notifying guest 0:28 (virq 1, port 0)
Sep 26 06:28:02.115684 (XEN) Notifying guest 0:29 (virq 1, port 0)
Sep 26 06:28:02.127577 (XEN) Notifying guest 0:30 (virq 1, port 0)
Sep 26 06:28:02.127637 (XEN) Notifying guest 0:31 (virq 1, port 0)
Sep 26 06:28:02.127684 (XEN) Notifying guest 0:32 (virq 1, port 0)
Sep 26 06:28:02.139580 (XEN) Notifying guest 0:33 (virq 1, port 0)
Sep 26 06:28:02.139640 (XEN) Notifying guest 0:34 (virq 1, port 0)
Sep 26 06:28:02.139687 (XEN) Notifying guest 0:35 (virq 1, port 0)
Sep 26 06:28:02.151573 (XEN) Notifying guest 0:36 (virq 1, port 0)
Sep 26 06:28:02.151634 (XEN) Notifying guest 0:37 (virq 1, port 0)
Sep 26 06:28:02.151680 (XEN) Notifying guest 0:38 (virq 1, port 0)
Sep 26 06:28:02.163531 (XEN) Notifying guest 0:39 (virq 1, port 0)
Sep 26 06:28:02.163564 (XEN) Notifying guest 0:40 (virq 1, port 0)
Sep 26 06:28:02.163590 (XEN) Notifying guest 0:41 (virq 1, port 0)
Sep 26 06:28:02.175577 (XEN) Notifying guest 0:42 (virq 1, port 0)
Sep 26 06:28:02.175637 (XEN) Notifying guest 0:43 (virq 1, port 0)
Sep 26 06:28:02.175683 (XEN) Notifying guest 0:44 (virq 1, port 0)
Sep 26 06:28:02.187589 (XEN) Notifying guest 0:45 (virq 1, port 0)
Sep 26 06:28:02.187650 (XEN) Notifying guest 0:46 (virq 1, port 0)
Sep 26 06:28:02.187696 (XEN) Notifying guest 0:47 (virq 1, port 0)
Sep 26 06:28:02.199579 (XEN) Notifying guest 0:48 (virq 1, port 0)
Sep 26 06:28:02.199640 (XEN) Notifying guest 0:49 (virq 1, port 0)
Sep 26 06:28:02.199707 (XEN) Notifying guest 0:50 (virq 1, port 0)
Sep 26 06:28:02.211589 (XEN) Notifying guest 0:51 (virq 1, port 0)
Sep 26 06:28:02.211650 (XEN) Notifying guest 0:52 (virq 1, port 0)
Sep 26 06:28:02.211697 (XEN) Notifying guest 0:53 (virq 1, port 0)
Sep 26 06:28:02.223578 (XEN) Notifying guest 0:54 (virq 1, port 0)
Sep 26 06:28:02.223639 (XEN) Notifying guest 0:55 (virq 1, port 0)
Sep 26 06:28:02.223685 (XEN) Notifying guest 0:56 (virq 1, port 0)
Sep 26 06:28:02.235576 (XEN) Notifying guest 0:57 (virq 1, port 0)
Sep 26 06:28:02.235636 (XEN) Notifying guest 0:58 (virq 1, port 0)
Sep 26 06:28:02.235684 (XEN) Notifying guest 0:59 (virq 1, port 0)
Sep 26 06:28:02.247573 (XEN) Notifying guest 0:60 (virq 1, port 0)
Sep 26 06:28:02.247635 (XEN) Notifying guest 0:61 (virq 1, port 0)
Sep 26 06:28:02.247681 (XEN) Notifying guest 0:62 (virq 1, port 0)
Sep 26 06:28:02.247725 (XEN) Notifying guest 0:63 (virq 1, port 0)
Sep 26 06:28:02.259593 (XEN) Notifying guest 0:64 (virq 1, port 0)
Sep 26 06:28:02.259651 (XEN) Notifying guest 0:65 (virq 1, port 0)
Sep 26 06:28:02.259698 (XEN) Notifying guest 0:66 (virq 1, port 0)
Sep 26 06:28:02.271583 (XEN) Notifying guest 0:67 (virq 1, port 0)
Sep 26 06:28:02.271642 (XEN) Notifying guest 0:68 (virq 1, port 0)
Sep 26 06:28:02.271689 (XEN) Notifying guest 0:69 (virq 1, port 0)
Sep 26 06:28:02.283580 (XEN) Notifying guest 0:70 (virq 1, port 0)
Sep 26 06:28:02.283639 (XEN) Notifying guest 0:71 (virq 1, port 0)
Sep 26 06:28:02.283686 (XEN) Notifying guest 0:72 (virq 1, port 0)
Sep 26 06:28:02.295570 (XEN) Notifying guest 0:73 (virq 1, port 0)
Sep 26 06:28:02.295629 (XEN) Notifying guest 0:74 (virq 1, port 0)
Sep 26 06:28:02.307579 (XEN) Notifying guest 0:75 (virq 1, port 0)
Sep 26 06:28:02.307640 (XEN) Notifying guest 0:76 (virq 1, port 0)
Sep 26 06:28:02.307686 (XEN) Notifying guest 0:77 (virq 1, port 0)
Sep 26 06:28:02.319575 (XEN) Notifying guest 0:78 (virq 1, port 0)
Sep 26 06:28:02.319652 (XEN) Notifying guest 0:79 (virq 1, port 0)
Sep 26 06:28:02.319701 (XEN) Notifying guest 0:80 (virq 1, port 0)
Sep 26 06:28:02.319746 (XEN) Notifying guest 0:81 (virq 1, port 0)
Sep 26 06:28:02.331584 (XEN) Notifying guest 0:82 (virq 1, port 0)
Sep 26 06:28:02.331644 (XEN) Notifying guest 0:83 (virq 1, port 0)
Sep 26 06:28:02.331690 (XEN) Notifying guest 0:84 (virq 1, port 0)
Sep 26 06:28:02.343581 (XEN) Notifying guest 0:85 (virq 1, port 0)
Sep 26 06:28:02.343641 (XEN) Notifying guest 0:86 (virq 1, port 0)
Sep 26 06:28:02.343687 (XEN) Notifying guest 0:87 (virq 1, port 0)
Sep 26 06:28:02.355584 (XEN) Notifying guest 0:88 (virq 1, port 0)
Sep 26 06:28:02.355644 (XEN) Notifying guest 0:89 (virq 1, port 0)
Sep 26 06:28:02.355689 (XEN) Notifying guest 0:90 (virq 1, port 0)
Sep 26 06:28:02.367577 (XEN) Notifying guest 0:91 (virq 1, port 0)
Sep 26 06:28:02.367637 (XEN) Notifying guest 0:92 (virq 1, port 0)
Sep 26 06:28:02.367683 (XEN) Notifying guest 0:93 (virq 1, port 0)
Sep 26 06:28:02.379574 (XEN) Notifying guest 0:94 (virq 1, port 0)
Sep 26 06:28:02.379634 (XEN) Notifying guest 0:95 (virq 1, port 0)
Sep 26 06:28:02.379679 Sep 26 06:28:08.889699 <client 0x1a61580 connected - now 1 clients>
(XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input)
Sep 26 06:28:08.911616 


Sep 26 06:28:08.911682 rochester1 login: 
Sep 26 06:28:08.913453 <client 0x1a61580 disconnected - now 0 clients>