Oct 2 19:26:10.063274 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.063702 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.072841 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.072898 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.072942 (XEN) No periodic timer Oct 2 19:26:10.072984 (XEN) UNIT1 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.073032 (XEN) VCPU1: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.084767 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.084799 (XEN) GICH_LRs (vcpu 1) mask=0 Oct 2 19:26:10.084824 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.096748 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.096778 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.096813 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.096836 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.096858 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.108762 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.108793 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.108829 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.108852 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.108874 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.108896 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.120764 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.120806 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.120830 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.120852 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.120874 (XEN) No periodic timer Oct 2 19:26:10.120897 (XEN) UNIT2 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.132764 (XEN) VCPU2: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.132799 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.144760 (XEN) GICH_LRs (vcpu 2) mask=0 Oct 2 19:26:10.144792 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.144815 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.144850 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.144873 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.156764 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.156795 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.156819 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.156853 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.156876 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.156898 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.172778 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.172810 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.172846 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.172869 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.172891 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.172914 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.172936 (XEN) No periodic timer Oct 2 19:26:10.172960 (XEN) UNIT3 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.184767 (XEN) VCPU3: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.184803 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.196759 (XEN) GICH_LRs (vcpu 3) mask=0 Oct 2 19:26:10.196791 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.196815 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.196849 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.196872 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.196894 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.212818 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.212872 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.212936 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.212978 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.213019 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.213060 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.213101 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.213156 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.228783 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.228835 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.228878 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.228919 (XEN) No periodic timer Oct 2 19:26:10.228983 (XEN) UNIT4 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.240885 (XEN) VCPU4: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.240949 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.240996 (XEN) GICH_LRs (vcpu 4) mask=0 Oct 2 19:26:10.252895 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.252974 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.253019 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.253060 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.253101 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.253141 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.264894 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.264950 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.265013 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.265057 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.265097 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.265161 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.276897 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.276953 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.276997 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.277037 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.277101 (XEN) No periodic timer Oct 2 19:26:10.277145 (XEN) UNIT5 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.288901 (XEN) VCPU5: CPU72 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.288965 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.300897 (XEN) GICH_LRs (vcpu 5) mask=0 Oct 2 19:26:10.300978 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.301023 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.301064 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.301120 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.301162 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.312899 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.312955 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.312998 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.313062 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.313105 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.313146 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.324906 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.324962 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.325027 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.325070 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.325110 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.336892 (XEN) No periodic timer Oct 2 19:26:10.336949 (XEN) UNIT6 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.337020 (XEN) VCPU6: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.348886 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.348945 (XEN) GICH_LRs (vcpu 6) mask=0 Oct 2 19:26:10.348989 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.349031 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.360821 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.360829 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.360872 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.361023 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.361050 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.361123 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.372908 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.372964 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.373007 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.373049 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.373113 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.373155 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.384897 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.384953 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.384996 (XEN) No periodic timer Oct 2 19:26:10.385060 (XEN) UNIT7 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.396889 (XEN) VCPU7: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.396955 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.397000 (XEN) GICH_LRs (vcpu 7) mask=0 Oct 2 19:26:10.408893 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.408971 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.409015 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.409057 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.409098 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.409140 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.420902 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.420949 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.420972 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.420995 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.421017 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.421075 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.432885 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.432943 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.432987 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.433028 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.433093 (XEN) No periodic timer Oct 2 19:26:10.433137 (XEN) UNIT8 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.444911 (XEN) VCPU8: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.444975 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.456890 (XEN) GICH_LRs (vcpu 8) mask=0 Oct 2 19:26:10.456970 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.457014 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.457057 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.457098 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.457156 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.468906 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.468962 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.469004 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.469044 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.469086 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.469149 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.480886 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.480943 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.480986 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.481028 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.481070 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.492895 (XEN) No periodic timer Oct 2 19:26:10.492951 (XEN) UNIT9 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.492998 (XEN) VCPU9: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.504860 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.504911 (XEN) GICH_LRs (vcpu 9) mask=0 Oct 2 19:26:10.504977 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.505020 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.516853 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.516909 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.516951 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.517016 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.517058 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.517099 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.528895 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.528951 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.529017 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.529059 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.529100 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.529141 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.540894 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.540973 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.541016 (XEN) No periodic timer Oct 2 19:26:10.541058 (XEN) UNIT10 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.541104 (XEN) VCPU10: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.552906 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.552965 (XEN) GICH_LRs (vcpu 10) mask=0 Oct 2 19:26:10.564895 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.564951 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.564994 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.565036 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.565076 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.565116 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.576895 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.576951 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.576994 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.577034 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.577074 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.577114 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.588896 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.588952 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.588995 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.589036 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.589077 (XEN) No periodic timer Oct 2 19:26:10.589118 (XEN) UNIT11 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.600897 (XEN) VCPU11: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.600960 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.612903 (XEN) GICH_LRs (vcpu 11) mask=0 Oct 2 19:26:10.612961 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.613003 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.613044 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.613084 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.624902 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.624957 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.624999 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.625041 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.625081 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.625121 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.636896 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.636952 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.636994 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.637034 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.637074 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.637114 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.648893 (XEN) No periodic timer Oct 2 19:26:10.648949 (XEN) UNIT12 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.648997 (XEN) VCPU12: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.660903 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.660961 (XEN) GICH_LRs (vcpu 12) mask=0 Oct 2 19:26:10.661025 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.661069 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.672902 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.672958 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.673000 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.673041 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.673081 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.673121 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.684905 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.684960 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.685002 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.685043 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.685082 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.685122 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.696898 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.696953 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.696995 (XEN) No periodic timer Oct 2 19:26:10.697037 (XEN) UNIT13 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.708868 (XEN) VCPU13: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.708932 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.708977 (XEN) GICH_LRs (vcpu 13) mask=0 Oct 2 19:26:10.720895 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.720951 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.720993 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.721034 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.721075 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.721115 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.732885 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.732941 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.732984 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.733025 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.733066 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.744894 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.744950 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.744992 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.745034 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.745075 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.745116 (XEN) No periodic timer Oct 2 19:26:10.756895 (XEN) UNIT14 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.756956 (XEN) VCPU14: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.757007 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.768927 (XEN) GICH_LRs (vcpu 14) mask=0 Oct 2 19:26:10.768985 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.769028 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.769069 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.769109 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.780898 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.780953 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.780995 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.781035 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.781075 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.781115 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.792896 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.792951 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.792994 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.793034 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.793074 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.804895 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.804951 (XEN) No periodic timer Oct 2 19:26:10.804995 (XEN) UNIT15 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.805042 (XEN) VCPU15: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.816895 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.816953 (XEN) GICH_LRs (vcpu 15) mask=0 Oct 2 19:26:10.816997 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.817038 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.828909 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.828964 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.829006 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.829047 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.829087 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.829127 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.840884 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.840939 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.840981 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.841021 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.841062 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.841102 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.852894 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.852949 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.852991 (XEN) No periodic timer Oct 2 19:26:10.853033 (XEN) UNIT16 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.864917 (XEN) VCPU16: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.864983 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.865027 (XEN) GICH_LRs (vcpu 16) mask=0 Oct 2 19:26:10.876900 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.876955 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.876997 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.877038 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.877078 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.888894 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.888949 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.888992 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.889033 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.889073 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.889114 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.900892 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.900948 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.900990 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.901031 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.901071 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.901111 (XEN) No periodic timer Oct 2 19:26:10.912898 (XEN) UNIT17 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.912959 (XEN) VCPU17: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.924899 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.924960 (XEN) GICH_LRs (vcpu 17) mask=0 Oct 2 19:26:10.925005 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.925046 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.925086 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.936928 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.936984 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.937026 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.937066 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.937106 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.937146 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.948893 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.948949 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.948992 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.949034 (XEN) VCPU_LR[12]=0 Oct 2 19:26:10.949074 (XEN) VCPU_LR[13]=0 Oct 2 19:26:10.949114 (XEN) VCPU_LR[14]=0 Oct 2 19:26:10.960898 (XEN) VCPU_LR[15]=0 Oct 2 19:26:10.960954 (XEN) No periodic timer Oct 2 19:26:10.960997 (XEN) UNIT18 affinities: hard={0-95} soft={0-95} Oct 2 19:26:10.961044 (XEN) VCPU18: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:10.972913 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:10.972971 (XEN) GICH_LRs (vcpu 18) mask=0 Oct 2 19:26:10.973017 (XEN) VCPU_LR[0]=0 Oct 2 19:26:10.973058 (XEN) VCPU_LR[1]=0 Oct 2 19:26:10.984892 (XEN) VCPU_LR[2]=0 Oct 2 19:26:10.984947 (XEN) VCPU_LR[3]=0 Oct 2 19:26:10.984989 (XEN) VCPU_LR[4]=0 Oct 2 19:26:10.985030 (XEN) VCPU_LR[5]=0 Oct 2 19:26:10.985071 (XEN) VCPU_LR[6]=0 Oct 2 19:26:10.996904 (XEN) VCPU_LR[7]=0 Oct 2 19:26:10.996959 (XEN) VCPU_LR[8]=0 Oct 2 19:26:10.997001 (XEN) VCPU_LR[9]=0 Oct 2 19:26:10.997042 (XEN) VCPU_LR[10]=0 Oct 2 19:26:10.997083 (XEN) VCPU_LR[11]=0 Oct 2 19:26:10.997123 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.008899 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.008954 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.008996 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.009037 (XEN) No periodic timer Oct 2 19:26:11.009079 (XEN) UNIT19 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.020901 (XEN) VCPU19: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.020965 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.032891 (XEN) GICH_LRs (vcpu 19) mask=0 Oct 2 19:26:11.032949 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.032992 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.033033 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.033073 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.033113 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.044897 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.044953 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.044995 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.045035 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.045076 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.045116 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.056892 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.056947 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.057009 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.057053 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.057093 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.057133 (XEN) No periodic timer Oct 2 19:26:11.068903 (XEN) UNIT20 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.068963 (XEN) VCPU20: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.080891 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.080950 (XEN) GICH_LRs (vcpu 20) mask=0 Oct 2 19:26:11.080995 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.081036 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.081077 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.092891 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.092947 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.092989 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.093030 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.093071 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.093111 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.104892 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.104948 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.104990 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.105030 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.105070 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.105110 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.116895 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.116950 (XEN) No periodic timer Oct 2 19:26:11.116992 (XEN) UNIT21 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.117039 (XEN) VCPU21: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.128906 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.128963 (XEN) GICH_LRs (vcpu 21) mask=0 Oct 2 19:26:11.129007 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.140897 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.140951 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.140993 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.141033 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.141073 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.141113 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.152902 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.152958 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.152999 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.153040 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.153080 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.164893 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.164950 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.164992 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.165032 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.165072 (XEN) No periodic timer Oct 2 19:26:11.165113 (XEN) UNIT22 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.176913 (XEN) VCPU22: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.176977 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.188894 (XEN) GICH_LRs (vcpu 22) mask=0 Oct 2 19:26:11.188952 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.188994 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.189035 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.189075 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.189115 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.200890 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.200946 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.200988 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.201028 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.201068 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.201108 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.212906 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.212961 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.213003 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.213044 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.213084 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.224894 (XEN) No periodic timer Oct 2 19:26:11.224951 (XEN) UNIT23 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.224999 (XEN) VCPU23: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.236889 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.236948 (XEN) GICH_LRs (vcpu 23) mask=0 Oct 2 19:26:11.236992 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.237034 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.248895 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.248951 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.248993 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.249033 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.249074 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.249114 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.260903 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.260979 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.261025 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.261065 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.261105 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.261144 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.272897 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.272952 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.272994 (XEN) No periodic timer Oct 2 19:26:11.273036 (XEN) UNIT24 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.273083 (XEN) VCPU24: CPU7 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.284909 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.284967 (XEN) GICH_LRs (vcpu 24) mask=0 Oct 2 19:26:11.296892 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.296948 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.296990 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.297031 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.297071 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.297111 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.308893 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.308949 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.308991 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.309032 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.309072 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.309112 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.320902 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.320958 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.321001 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.321041 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.321082 (XEN) No periodic timer Oct 2 19:26:11.321124 (XEN) UNIT25 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.332897 (XEN) VCPU25: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.332961 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.344895 (XEN) GICH_LRs (vcpu 25) mask=0 Oct 2 19:26:11.344953 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.344995 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.345036 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.345075 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.345115 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.356898 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.356953 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.356995 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.357035 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.357075 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.357115 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.368902 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.368957 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.368999 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.369041 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.380890 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.380947 (XEN) No periodic timer Oct 2 19:26:11.380991 (XEN) UNIT26 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.381037 (XEN) VCPU26: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.392899 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.392957 (XEN) GICH_LRs (vcpu 26) mask=0 Oct 2 19:26:11.393002 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.393043 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.404907 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.404962 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.405004 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.405046 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.405086 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.405126 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.416889 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.416945 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.416986 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.417027 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.417067 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.417107 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.428906 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.428961 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.429003 (XEN) No periodic timer Oct 2 19:26:11.429044 (XEN) UNIT27 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.440902 (XEN) VCPU27: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.440967 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.441012 (XEN) GICH_LRs (vcpu 27) mask=0 Oct 2 19:26:11.452894 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.452949 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.452991 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.453032 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.453091 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.453134 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.464812 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.464844 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.464885 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.464926 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.464966 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.465006 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.476901 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.476957 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.476999 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.477040 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.477080 (XEN) No periodic timer Oct 2 19:26:11.477121 (XEN) UNIT28 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.488904 (XEN) VCPU28: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.488968 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.500888 (XEN) GICH_LRs (vcpu 28) mask=0 Oct 2 19:26:11.500946 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.500988 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.501029 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.512889 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.512946 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.512989 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.513030 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.513070 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.513110 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.524897 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.524954 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.524997 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.525038 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.525078 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.525119 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.536893 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.536949 (XEN) No periodic timer Oct 2 19:26:11.536992 (XEN) UNIT29 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.537038 (XEN) VCPU29: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.548902 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.548961 (XEN) GICH_LRs (vcpu 29) mask=0 Oct 2 19:26:11.549005 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.549045 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.560898 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.560953 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.560995 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.561036 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.561075 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.561116 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.572777 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.572810 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.572851 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.572892 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.572932 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.572973 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.584913 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.584968 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.585011 (XEN) No periodic timer Oct 2 19:26:11.585052 (XEN) UNIT30 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.596898 (XEN) VCPU30: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.596962 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.597007 (XEN) GICH_LRs (vcpu 30) mask=0 Oct 2 19:26:11.608890 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.608946 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.608987 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.609028 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.609068 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.609108 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.620898 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.620954 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.620996 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.621036 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.621076 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.632898 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.632953 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.632995 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.633037 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.633077 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.633117 (XEN) No periodic timer Oct 2 19:26:11.644900 (XEN) UNIT31 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.644961 (XEN) VCPU31: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.656902 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.656961 (XEN) GICH_LRs (vcpu 31) mask=0 Oct 2 19:26:11.657025 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.657070 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.657111 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.668890 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.668946 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.668988 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.669029 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.669069 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.669110 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.680905 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.680961 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.681003 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.681044 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.681085 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.681125 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.692896 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.692951 (XEN) No periodic timer Oct 2 19:26:11.692994 (XEN) UNIT32 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.693041 (XEN) VCPU32: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.704902 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.704960 (XEN) GICH_LRs (vcpu 32) mask=0 Oct 2 19:26:11.705003 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.705044 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.716912 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.716967 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.717009 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.717049 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.717090 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.717130 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.728897 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.728951 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.728994 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.729034 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.729075 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.740894 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.740950 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.740992 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.741033 (XEN) No periodic timer Oct 2 19:26:11.741075 (XEN) UNIT33 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.752881 (XEN) VCPU33: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.752945 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.764900 (XEN) GICH_LRs (vcpu 33) mask=0 Oct 2 19:26:11.764959 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.765002 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.765043 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.765083 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.765123 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.776909 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.776965 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.777006 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.777047 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.777087 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.777127 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.788899 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.788954 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.788996 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.789037 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.789078 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.789118 (XEN) No periodic timer Oct 2 19:26:11.800899 (XEN) UNIT34 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.800960 (XEN) VCPU34: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.812894 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.812953 (XEN) GICH_LRs (vcpu 34) mask=0 Oct 2 19:26:11.812997 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.813038 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.813078 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.824907 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.824963 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.825005 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.825045 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.825086 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.825126 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.836884 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.836940 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.836982 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.837023 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.837063 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.837103 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.848895 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.848951 (XEN) No periodic timer Oct 2 19:26:11.848994 (XEN) UNIT35 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.849061 (XEN) VCPU35: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.860891 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.860950 (XEN) GICH_LRs (vcpu 35) mask=0 Oct 2 19:26:11.860994 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.872894 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.872950 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.872992 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.873033 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.873073 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.884888 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.884944 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.884987 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.885027 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.885068 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.885108 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.896895 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.896951 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.896994 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.897035 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.897075 (XEN) No periodic timer Oct 2 19:26:11.897116 (XEN) UNIT36 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.908900 (XEN) VCPU36: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.908964 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.920904 (XEN) GICH_LRs (vcpu 36) mask=0 Oct 2 19:26:11.920962 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.921004 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.921044 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.921085 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.921124 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.932890 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.932945 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.932987 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.933028 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.933068 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.933107 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.944911 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.944966 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.945008 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.945049 (XEN) VCPU_LR[14]=0 Oct 2 19:26:11.945089 (XEN) VCPU_LR[15]=0 Oct 2 19:26:11.956886 (XEN) No periodic timer Oct 2 19:26:11.956943 (XEN) UNIT37 affinities: hard={0-95} soft={0-95} Oct 2 19:26:11.956991 (XEN) VCPU37: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:11.968909 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:11.968967 (XEN) GICH_LRs (vcpu 37) mask=0 Oct 2 19:26:11.969012 (XEN) VCPU_LR[0]=0 Oct 2 19:26:11.969053 (XEN) VCPU_LR[1]=0 Oct 2 19:26:11.969093 (XEN) VCPU_LR[2]=0 Oct 2 19:26:11.980899 (XEN) VCPU_LR[3]=0 Oct 2 19:26:11.980954 (XEN) VCPU_LR[4]=0 Oct 2 19:26:11.980996 (XEN) VCPU_LR[5]=0 Oct 2 19:26:11.981037 (XEN) VCPU_LR[6]=0 Oct 2 19:26:11.981077 (XEN) VCPU_LR[7]=0 Oct 2 19:26:11.981118 (XEN) VCPU_LR[8]=0 Oct 2 19:26:11.992901 (XEN) VCPU_LR[9]=0 Oct 2 19:26:11.992957 (XEN) VCPU_LR[10]=0 Oct 2 19:26:11.992998 (XEN) VCPU_LR[11]=0 Oct 2 19:26:11.993039 (XEN) VCPU_LR[12]=0 Oct 2 19:26:11.993079 (XEN) VCPU_LR[13]=0 Oct 2 19:26:11.993120 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.004893 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.004949 (XEN) No periodic timer Oct 2 19:26:12.004991 (XEN) UNIT38 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.016896 (XEN) VCPU38: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.016961 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.017006 (XEN) GICH_LRs (vcpu 38) mask=0 Oct 2 19:26:12.028894 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.028950 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.028993 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.029034 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.029075 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.029115 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.040893 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.040948 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.040991 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.041031 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.041071 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.041112 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.052876 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.052931 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.052994 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.053038 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.053078 (XEN) No periodic timer Oct 2 19:26:12.053119 (XEN) UNIT39 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.064901 (XEN) VCPU39: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.064965 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.076897 (XEN) GICH_LRs (vcpu 39) mask=0 Oct 2 19:26:12.076956 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.076998 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.077038 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.077079 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.088901 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.088957 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.089000 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.089040 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.089081 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.089120 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.100891 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.100948 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.100991 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.101032 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.101072 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.101113 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.112888 (XEN) No periodic timer Oct 2 19:26:12.112944 (XEN) UNIT40 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.112992 (XEN) VCPU40: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.124904 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.124961 (XEN) GICH_LRs (vcpu 40) mask=0 Oct 2 19:26:12.125006 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.125047 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.136889 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.136944 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.136987 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.137027 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.137067 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.137107 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.148899 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.148954 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.148995 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.149036 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.149076 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.149116 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.160905 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.160960 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.161002 (XEN) No periodic timer Oct 2 19:26:12.161044 (XEN) UNIT41 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.172900 (XEN) VCPU41: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.172964 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.173010 (XEN) GICH_LRs (vcpu 41) mask=0 Oct 2 19:26:12.184908 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.184964 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.185006 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.185047 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.185087 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.185126 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.196897 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.196953 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.196996 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.197037 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.197077 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.197117 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.208889 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.208945 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.208986 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.209027 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.209067 (XEN) No periodic timer Oct 2 19:26:12.209109 (XEN) UNIT42 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.220913 (XEN) VCPU42: CPU9 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.220976 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.232897 (XEN) GICH_LRs (vcpu 42) mask=0 Oct 2 19:26:12.232955 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.232997 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.233038 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.233078 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.244892 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.244948 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.244990 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.245031 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.245071 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.245131 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.256885 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.256942 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.256985 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.257026 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.257066 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.268896 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.268952 (XEN) No periodic timer Oct 2 19:26:12.268995 (XEN) UNIT43 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.269042 (XEN) VCPU43: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.280900 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.280958 (XEN) GICH_LRs (vcpu 43) mask=0 Oct 2 19:26:12.281002 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.281043 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.292896 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.292950 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.292992 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.293032 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.293072 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.293112 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.304902 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.304957 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.304999 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.305039 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.305079 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.305119 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.316893 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.316948 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.316990 (XEN) No periodic timer Oct 2 19:26:12.317032 (XEN) UNIT44 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.328907 (XEN) VCPU44: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.328972 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.329017 (XEN) GICH_LRs (vcpu 44) mask=0 Oct 2 19:26:12.340884 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.340940 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.340981 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.341023 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.341063 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.341103 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.352893 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.352949 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.352990 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.353031 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.353071 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.353111 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.364909 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.364964 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.365006 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.365047 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.365087 (XEN) No periodic timer Oct 2 19:26:12.365128 (XEN) UNIT45 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.376906 (XEN) VCPU45: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.376970 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.388887 (XEN) GICH_LRs (vcpu 45) mask=0 Oct 2 19:26:12.388945 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.388987 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.389027 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.400892 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.400948 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.400990 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.401031 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.401071 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.401111 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.412895 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.412951 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.412993 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.413034 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.413073 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.413113 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.424907 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.424963 (XEN) No periodic timer Oct 2 19:26:12.425006 (XEN) UNIT46 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.425053 (XEN) VCPU46: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.436898 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.436956 (XEN) GICH_LRs (vcpu 46) mask=0 Oct 2 19:26:12.437033 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.448895 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.448952 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.448994 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.449035 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.449095 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.449138 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.460888 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.460944 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.461015 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.461061 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.461102 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.461143 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.472904 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.472960 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.473002 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.473042 (XEN) No periodic timer Oct 2 19:26:12.473089 (XEN) UNIT47 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.484895 (XEN) VCPU47: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.484958 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.485004 (XEN) GICH_LRs (vcpu 47) mask=0 Oct 2 19:26:12.496898 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.496954 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.496996 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.497036 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.497076 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.497116 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.508890 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.508945 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.508986 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.509026 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.509067 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.520894 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.520949 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.520990 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.521031 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.521071 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.521111 (XEN) No periodic timer Oct 2 19:26:12.532898 (XEN) UNIT48 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.532958 (XEN) VCPU48: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.544897 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.544956 (XEN) GICH_LRs (vcpu 48) mask=0 Oct 2 19:26:12.545000 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.545041 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.545081 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.556897 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.556952 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.556995 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.557035 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.557075 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.557116 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.568899 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.568955 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.568997 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.569038 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.569078 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.569119 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.580898 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.580953 (XEN) No periodic timer Oct 2 19:26:12.580996 (XEN) UNIT49 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.581043 (XEN) VCPU49: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.592903 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.592961 (XEN) GICH_LRs (vcpu 49) mask=0 Oct 2 19:26:12.593006 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.604890 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.604945 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.604988 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.605028 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.605069 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.605109 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.616904 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.616959 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.617001 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.617041 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.617081 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.617121 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.628894 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.628951 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.628993 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.629034 (XEN) No periodic timer Oct 2 19:26:12.629075 (XEN) UNIT50 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.640885 (XEN) VCPU50: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.640949 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.652897 (XEN) GICH_LRs (vcpu 50) mask=0 Oct 2 19:26:12.652974 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.653019 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.653059 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.653099 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.653138 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.664909 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.664965 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.665007 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.665047 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.665087 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.665127 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.676812 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.676838 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.676880 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.676921 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.676961 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.688905 (XEN) No periodic timer Oct 2 19:26:12.688962 (XEN) UNIT51 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.689009 (XEN) VCPU51: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.700904 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.700962 (XEN) GICH_LRs (vcpu 51) mask=0 Oct 2 19:26:12.701007 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.701048 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.701088 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.712895 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.712950 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.712992 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.713032 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.713072 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.713113 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.724896 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.724952 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.724993 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.725034 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.725074 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.725114 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.736897 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.736953 (XEN) No periodic timer Oct 2 19:26:12.736996 (XEN) UNIT52 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.737042 (XEN) VCPU52: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.748909 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.748967 (XEN) GICH_LRs (vcpu 52) mask=0 Oct 2 19:26:12.749011 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.760888 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.760944 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.760986 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.761027 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.761067 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.772898 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.772955 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.772997 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.773037 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.773077 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.773118 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.784897 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.784953 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.784995 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.785036 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.785076 (XEN) No periodic timer Oct 2 19:26:12.785117 (XEN) UNIT53 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.796912 (XEN) VCPU53: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.796976 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.808897 (XEN) GICH_LRs (vcpu 53) mask=0 Oct 2 19:26:12.808955 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.808997 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.809038 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.809078 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.820883 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.820941 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.820983 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.821023 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.821064 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.821104 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.832893 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.832950 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.832992 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.833033 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.833073 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.833113 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.844900 (XEN) No periodic timer Oct 2 19:26:12.844956 (XEN) UNIT54 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.845022 (XEN) VCPU54: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.856893 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.856951 (XEN) GICH_LRs (vcpu 54) mask=0 Oct 2 19:26:12.856995 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.857036 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.857076 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.868909 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.868964 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.869006 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.869046 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.869086 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.869126 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.880894 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.880949 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.880991 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.881032 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.881073 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.892885 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.892942 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.892985 (XEN) No periodic timer Oct 2 19:26:12.893026 (XEN) UNIT55 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.904840 (XEN) VCPU55: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.904848 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.904893 (XEN) GICH_LRs (vcpu 55) mask=0 Oct 2 19:26:12.916908 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.916964 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.917005 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.917046 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.917086 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.917126 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.928906 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.928962 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.929004 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.929045 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.929085 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.929125 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.940895 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.940950 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.940992 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.941032 (XEN) VCPU_LR[15]=0 Oct 2 19:26:12.941072 (XEN) No periodic timer Oct 2 19:26:12.941114 (XEN) UNIT56 affinities: hard={0-95} soft={0-95} Oct 2 19:26:12.952906 (XEN) VCPU56: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:12.952970 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:12.964888 (XEN) GICH_LRs (vcpu 56) mask=0 Oct 2 19:26:12.964946 (XEN) VCPU_LR[0]=0 Oct 2 19:26:12.964988 (XEN) VCPU_LR[1]=0 Oct 2 19:26:12.965029 (XEN) VCPU_LR[2]=0 Oct 2 19:26:12.965069 (XEN) VCPU_LR[3]=0 Oct 2 19:26:12.976907 (XEN) VCPU_LR[4]=0 Oct 2 19:26:12.976963 (XEN) VCPU_LR[5]=0 Oct 2 19:26:12.977005 (XEN) VCPU_LR[6]=0 Oct 2 19:26:12.977046 (XEN) VCPU_LR[7]=0 Oct 2 19:26:12.977087 (XEN) VCPU_LR[8]=0 Oct 2 19:26:12.977126 (XEN) VCPU_LR[9]=0 Oct 2 19:26:12.988901 (XEN) VCPU_LR[10]=0 Oct 2 19:26:12.988957 (XEN) VCPU_LR[11]=0 Oct 2 19:26:12.989000 (XEN) VCPU_LR[12]=0 Oct 2 19:26:12.989041 (XEN) VCPU_LR[13]=0 Oct 2 19:26:12.989082 (XEN) VCPU_LR[14]=0 Oct 2 19:26:12.989122 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.000904 (XEN) No periodic timer Oct 2 19:26:13.000960 (XEN) UNIT57 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.001007 (XEN) VCPU57: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.012878 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.012936 (XEN) GICH_LRs (vcpu 57) mask=0 Oct 2 19:26:13.012981 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.013022 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.024882 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.024938 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.024981 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.025022 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.025062 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.025102 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.036898 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.036953 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.036994 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.037035 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.037075 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.048893 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.048975 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.049021 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.049062 (XEN) No periodic timer Oct 2 19:26:13.049103 (XEN) UNIT58 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.060894 (XEN) VCPU58: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.060958 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.061004 (XEN) GICH_LRs (vcpu 58) mask=0 Oct 2 19:26:13.072898 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.072954 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.072996 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.073037 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.073077 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.073117 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.084883 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.084937 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.084979 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.085020 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.085060 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.085100 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.096891 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.096946 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.096988 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.097029 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.097070 (XEN) No periodic timer Oct 2 19:26:13.108889 (XEN) UNIT59 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.108952 (XEN) VCPU59: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.109003 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.120912 (XEN) GICH_LRs (vcpu 59) mask=0 Oct 2 19:26:13.120969 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.121012 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.121053 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.121093 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.132897 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.132953 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.132995 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.133035 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.133076 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.133117 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.144893 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.144948 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.144991 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.145031 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.145071 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.156909 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.156965 (XEN) No periodic timer Oct 2 19:26:13.157007 (XEN) UNIT60 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.157054 (XEN) VCPU60: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.168900 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.168957 (XEN) GICH_LRs (vcpu 60) mask=0 Oct 2 19:26:13.169001 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.180878 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.180935 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.180977 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.181018 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.181058 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.181098 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.192892 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.192948 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.192991 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.193032 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.193073 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.193113 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.204895 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.204951 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.204994 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.205034 (XEN) No periodic timer Oct 2 19:26:13.205075 (XEN) UNIT61 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.216901 (XEN) VCPU61: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.216965 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.217010 (XEN) GICH_LRs (vcpu 61) mask=0 Oct 2 19:26:13.228895 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.228950 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.228992 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.229032 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.229073 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.229113 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.240901 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.240956 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.240998 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.241039 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.241100 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.241144 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.252903 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.252958 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.253000 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.253040 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.253080 (XEN) No periodic timer Oct 2 19:26:13.264900 (XEN) UNIT62 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.264962 (XEN) VCPU62: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.265012 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.276896 (XEN) GICH_LRs (vcpu 62) mask=0 Oct 2 19:26:13.276953 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.276995 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.277036 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.288898 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.288954 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.288996 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.289036 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.289076 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.289116 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.300899 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.300953 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.300996 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.301036 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.301076 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.301116 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.312895 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.312950 (XEN) No periodic timer Oct 2 19:26:13.312993 (XEN) UNIT63 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.313039 (XEN) VCPU63: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.324914 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.324972 (XEN) GICH_LRs (vcpu 63) mask=0 Oct 2 19:26:13.325017 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.336893 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.336949 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.336992 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.337033 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.337073 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.337112 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.348898 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.348954 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.348995 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.349036 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.349076 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.349116 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.360895 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.360951 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.360993 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.361034 (XEN) No periodic timer Oct 2 19:26:13.361075 (XEN) UNIT64 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.372913 (XEN) VCPU64: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.372977 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.373022 (XEN) GICH_LRs (vcpu 64) mask=0 Oct 2 19:26:13.384903 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.384958 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.385000 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.385041 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.385080 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.396884 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.396940 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.396983 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.397024 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.397064 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.408902 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.408959 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.409000 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.409042 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.409082 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.409122 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.420891 (XEN) No periodic timer Oct 2 19:26:13.420947 (XEN) UNIT65 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.420995 (XEN) VCPU65: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.432907 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.432966 (XEN) GICH_LRs (vcpu 65) mask=0 Oct 2 19:26:13.433011 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.433052 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.433093 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.444899 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.444954 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.445016 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.445060 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.445101 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.445141 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.456898 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.456953 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.456996 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.457037 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.457077 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.457118 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.468907 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.468961 (XEN) No periodic timer Oct 2 19:26:13.469004 (XEN) UNIT66 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.469050 (XEN) VCPU66: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.480897 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.480955 (XEN) GICH_LRs (vcpu 66) mask=0 Oct 2 19:26:13.480999 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.492871 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.492927 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.492969 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.493010 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.493050 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.493091 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.504900 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.504955 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.504997 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.505038 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.505079 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.505119 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.516897 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.516953 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.516995 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.517036 (XEN) No periodic timer Oct 2 19:26:13.517078 (XEN) UNIT67 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.528887 (XEN) VCPU67: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.528950 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.540902 (XEN) GICH_LRs (vcpu 67) mask=0 Oct 2 19:26:13.540959 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.541002 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.541043 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.541083 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.552898 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.552953 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.552995 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.553036 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.553076 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.553115 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.564894 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.564950 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.564992 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.565033 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.565073 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.565113 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.576900 (XEN) No periodic timer Oct 2 19:26:13.576956 (XEN) UNIT68 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.577004 (XEN) VCPU68: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.588901 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.588959 (XEN) GICH_LRs (vcpu 68) mask=0 Oct 2 19:26:13.589004 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.589044 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.600886 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.600943 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.600986 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.601027 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.601067 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.601107 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.601147 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.612890 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.612945 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.612987 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.613028 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.613069 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.624909 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.624965 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.625007 (XEN) No periodic timer Oct 2 19:26:13.625049 (XEN) UNIT69 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.625095 (XEN) VCPU69: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.636910 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.636968 (XEN) GICH_LRs (vcpu 69) mask=0 Oct 2 19:26:13.637012 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.648916 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.648972 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.649014 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.649054 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.649093 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.649133 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.660899 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.660954 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.660996 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.661037 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.661077 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.672832 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.672837 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.672879 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.672920 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.672960 (XEN) No periodic timer Oct 2 19:26:13.673001 (XEN) UNIT70 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.684920 (XEN) VCPU70: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.684984 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.696903 (XEN) GICH_LRs (vcpu 70) mask=0 Oct 2 19:26:13.696961 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.697026 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.697076 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.697117 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.708896 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.708951 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.708993 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.709034 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.709075 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.709115 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.720896 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.720952 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.720995 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.721035 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.721077 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.721117 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.732890 (XEN) No periodic timer Oct 2 19:26:13.732946 (XEN) UNIT71 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.732994 (XEN) VCPU71: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.744898 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.744957 (XEN) GICH_LRs (vcpu 71) mask=0 Oct 2 19:26:13.745001 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.745042 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.756894 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.756950 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.756992 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.757033 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.757073 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.757113 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.768818 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.768835 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.768878 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.768918 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.768958 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.768997 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.780896 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.780953 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.780995 (XEN) No periodic timer Oct 2 19:26:13.781037 (XEN) UNIT72 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.792898 (XEN) VCPU72: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.792962 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.793007 (XEN) GICH_LRs (vcpu 72) mask=0 Oct 2 19:26:13.804904 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.804960 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.805002 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.805043 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.805083 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.805124 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.816893 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.816948 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.816989 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.817030 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.817070 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.817111 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.828912 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.828966 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.829008 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.829048 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.829088 (XEN) No periodic timer Oct 2 19:26:13.840892 (XEN) UNIT73 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.840954 (XEN) VCPU73: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.841025 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.852873 (XEN) GICH_LRs (vcpu 73) mask=0 Oct 2 19:26:13.852930 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.852972 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.853013 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.853054 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.864884 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.864939 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.864981 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.865022 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.865062 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.865102 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.876908 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.876964 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.877006 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.877047 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.877087 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.877128 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.888897 (XEN) No periodic timer Oct 2 19:26:13.888952 (XEN) UNIT74 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.889000 (XEN) VCPU74: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.900896 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.900955 (XEN) GICH_LRs (vcpu 74) mask=0 Oct 2 19:26:13.900999 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.901040 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.912885 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.912941 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.912984 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.913024 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.913064 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.924903 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.924959 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.925001 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.925041 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.925081 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.925121 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.936888 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.936944 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.936986 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.937027 (XEN) No periodic timer Oct 2 19:26:13.937068 (XEN) UNIT75 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.948896 (XEN) VCPU75: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.948961 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:13.949006 (XEN) GICH_LRs (vcpu 75) mask=0 Oct 2 19:26:13.960889 (XEN) VCPU_LR[0]=0 Oct 2 19:26:13.960945 (XEN) VCPU_LR[1]=0 Oct 2 19:26:13.960987 (XEN) VCPU_LR[2]=0 Oct 2 19:26:13.961027 (XEN) VCPU_LR[3]=0 Oct 2 19:26:13.961067 (XEN) VCPU_LR[4]=0 Oct 2 19:26:13.972901 (XEN) VCPU_LR[5]=0 Oct 2 19:26:13.972959 (XEN) VCPU_LR[6]=0 Oct 2 19:26:13.973001 (XEN) VCPU_LR[7]=0 Oct 2 19:26:13.973042 (XEN) VCPU_LR[8]=0 Oct 2 19:26:13.973081 (XEN) VCPU_LR[9]=0 Oct 2 19:26:13.973120 (XEN) VCPU_LR[10]=0 Oct 2 19:26:13.984898 (XEN) VCPU_LR[11]=0 Oct 2 19:26:13.984955 (XEN) VCPU_LR[12]=0 Oct 2 19:26:13.984997 (XEN) VCPU_LR[13]=0 Oct 2 19:26:13.985038 (XEN) VCPU_LR[14]=0 Oct 2 19:26:13.985079 (XEN) VCPU_LR[15]=0 Oct 2 19:26:13.985119 (XEN) No periodic timer Oct 2 19:26:13.996896 (XEN) UNIT76 affinities: hard={0-95} soft={0-95} Oct 2 19:26:13.996957 (XEN) VCPU76: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:13.997008 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.008902 (XEN) GICH_LRs (vcpu 76) mask=0 Oct 2 19:26:14.008960 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.009003 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.009044 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.009084 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.020898 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.020953 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.020995 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.021036 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.021076 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.021116 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.032884 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.032940 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.032982 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.033023 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.033064 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.044916 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.044973 (XEN) No periodic timer Oct 2 19:26:14.045016 (XEN) UNIT77 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.045062 (XEN) VCPU77: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.056909 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.056967 (XEN) GICH_LRs (vcpu 77) mask=0 Oct 2 19:26:14.057011 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.068897 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.068953 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.068995 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.069036 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.069076 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.069117 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.080896 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.080951 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.080993 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.081033 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.081074 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.081113 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.092895 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.092951 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.092993 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.093033 (XEN) No periodic timer Oct 2 19:26:14.093075 (XEN) UNIT78 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.104898 (XEN) VCPU78: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.104962 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.105006 (XEN) GICH_LRs (vcpu 78) mask=0 Oct 2 19:26:14.116849 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.116904 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.116946 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.116986 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.117026 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.128893 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.128948 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.128990 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.129031 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.129072 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.129111 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.140896 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.140951 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.140993 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.141034 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.141074 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.141115 (XEN) No periodic timer Oct 2 19:26:14.152891 (XEN) UNIT79 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.152952 (XEN) VCPU79: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.153003 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.164901 (XEN) GICH_LRs (vcpu 79) mask=0 Oct 2 19:26:14.164959 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.165001 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.165041 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.176900 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.176956 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.176998 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.177038 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.177078 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.177118 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.188912 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.188967 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.189009 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.189050 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.189090 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.200890 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.200947 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.200989 (XEN) No periodic timer Oct 2 19:26:14.201031 (XEN) UNIT80 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.201077 (XEN) VCPU80: CPU34 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.212902 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.212960 (XEN) GICH_LRs (vcpu 80) mask=0 Oct 2 19:26:14.213004 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.224900 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.224955 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.224998 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.225038 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.225078 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.225118 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.236898 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.236953 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.236995 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.237054 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.237098 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.237138 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.248898 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.248954 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.248996 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.249037 (XEN) No periodic timer Oct 2 19:26:14.249078 (XEN) UNIT81 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.260899 (XEN) VCPU81: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.260963 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.261008 (XEN) GICH_LRs (vcpu 81) mask=0 Oct 2 19:26:14.272898 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.272954 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.272995 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.273035 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.273076 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.284897 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.284952 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.284995 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.285036 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.285077 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.285117 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.296890 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.296946 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.296988 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.297028 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.297069 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.308895 (XEN) No periodic timer Oct 2 19:26:14.308952 (XEN) UNIT82 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.309000 (XEN) VCPU82: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.320893 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.320951 (XEN) GICH_LRs (vcpu 82) mask=0 Oct 2 19:26:14.320996 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.321037 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.332902 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.332958 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.333001 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.333042 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.333082 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.333121 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.344894 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.344951 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.344993 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.345033 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.345074 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.345114 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.356891 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.356947 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.356989 (XEN) No periodic timer Oct 2 19:26:14.357031 (XEN) UNIT83 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.357077 (XEN) VCPU83: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.368914 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.368972 (XEN) GICH_LRs (vcpu 83) mask=0 Oct 2 19:26:14.369016 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.380899 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.380954 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.380995 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.381036 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.381077 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.381117 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.392899 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.392954 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.392996 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.393037 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.393078 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.393119 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.404905 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.404960 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.405002 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.405043 (XEN) No periodic timer Oct 2 19:26:14.405085 (XEN) UNIT84 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.416901 (XEN) VCPU84: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.416964 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.428904 (XEN) GICH_LRs (vcpu 84) mask=0 Oct 2 19:26:14.428962 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.429005 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.429045 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.429085 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.440891 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.440946 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.441008 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.441052 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.441092 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.441132 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.452892 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.452948 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.452991 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.453032 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.453073 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.453113 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.464889 (XEN) No periodic timer Oct 2 19:26:14.464945 (XEN) UNIT85 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.464993 (XEN) VCPU85: CPU36 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.476907 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.476966 (XEN) GICH_LRs (vcpu 85) mask=0 Oct 2 19:26:14.477010 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.477051 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.488895 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.488951 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.488993 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.489034 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.489074 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.489114 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.500889 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.500946 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.500988 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.501028 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.501068 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.501108 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.512898 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.512954 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.512996 (XEN) No periodic timer Oct 2 19:26:14.513038 (XEN) UNIT86 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.513085 (XEN) VCPU86: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.524905 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.524963 (XEN) GICH_LRs (vcpu 86) mask=0 Oct 2 19:26:14.536893 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.536951 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.536993 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.537033 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.537074 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.537113 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.548884 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.548941 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.548984 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.549024 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.549064 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.549103 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.560903 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.560958 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.561000 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.561040 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.561081 (XEN) No periodic timer Oct 2 19:26:14.572895 (XEN) UNIT87 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.572957 (XEN) VCPU87: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.573007 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.584898 (XEN) GICH_LRs (vcpu 87) mask=0 Oct 2 19:26:14.584955 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.584998 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.585038 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.585078 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.596900 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.596955 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.596997 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.597037 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.597078 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.597118 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.608892 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.608947 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.608989 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.609030 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.609072 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.609112 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.620910 (XEN) No periodic timer Oct 2 19:26:14.620966 (XEN) UNIT88 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.621014 (XEN) VCPU88: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.632900 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.632957 (XEN) GICH_LRs (vcpu 88) mask=0 Oct 2 19:26:14.633001 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.633062 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.644899 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.644954 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.644996 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.645037 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.645077 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.645117 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.656890 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.656946 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.656989 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.657029 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.657069 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.657109 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.668899 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.668955 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.668997 (XEN) No periodic timer Oct 2 19:26:14.669039 (XEN) UNIT89 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.680902 (XEN) VCPU89: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.680965 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.681010 (XEN) GICH_LRs (vcpu 89) mask=0 Oct 2 19:26:14.692897 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.692952 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.692994 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.693035 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.693075 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.704893 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.704949 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.704991 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.705032 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.705073 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.705113 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.716895 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.716951 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.716994 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.717034 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.717074 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.717114 (XEN) No periodic timer Oct 2 19:26:14.728897 (XEN) UNIT90 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.728958 (XEN) VCPU90: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.729008 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.740912 (XEN) GICH_LRs (vcpu 90) mask=0 Oct 2 19:26:14.740972 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.741026 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.741069 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.741110 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.752883 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.752938 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.752979 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.753020 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.753060 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.753100 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.764895 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.764951 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.764993 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.765034 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.765074 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.776901 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.776958 (XEN) No periodic timer Oct 2 19:26:14.777000 (XEN) UNIT91 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.777058 (XEN) VCPU91: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.788906 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.788964 (XEN) GICH_LRs (vcpu 91) mask=0 Oct 2 19:26:14.789008 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.789049 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.800889 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.800944 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.800985 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.801026 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.801066 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.812894 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.812950 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.812992 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.813032 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.813073 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.813114 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.824913 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.824970 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.825012 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.825052 (XEN) No periodic timer Oct 2 19:26:14.825092 (XEN) UNIT92 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.836885 (XEN) VCPU92: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.836968 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.837015 (XEN) GICH_LRs (vcpu 92) mask=0 Oct 2 19:26:14.848899 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.848954 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.848997 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.849037 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.849077 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.860889 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.860944 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.860987 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.861027 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.861068 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.861107 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.872907 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.872963 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.873005 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.873046 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.873086 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.873126 (XEN) No periodic timer Oct 2 19:26:14.884890 (XEN) UNIT93 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.884951 (XEN) VCPU93: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.885002 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.896909 (XEN) GICH_LRs (vcpu 93) mask=0 Oct 2 19:26:14.896966 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.897008 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.897049 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.908901 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.908958 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.909000 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.909041 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.909081 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.909121 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.920879 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.920936 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.920978 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.921018 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.921059 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.921099 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.932906 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.932961 (XEN) No periodic timer Oct 2 19:26:14.933004 (XEN) UNIT94 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.933051 (XEN) VCPU94: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.944910 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:14.944968 (XEN) GICH_LRs (vcpu 94) mask=0 Oct 2 19:26:14.945013 (XEN) VCPU_LR[0]=0 Oct 2 19:26:14.956896 (XEN) VCPU_LR[1]=0 Oct 2 19:26:14.956951 (XEN) VCPU_LR[2]=0 Oct 2 19:26:14.956993 (XEN) VCPU_LR[3]=0 Oct 2 19:26:14.957034 (XEN) VCPU_LR[4]=0 Oct 2 19:26:14.957074 (XEN) VCPU_LR[5]=0 Oct 2 19:26:14.957114 (XEN) VCPU_LR[6]=0 Oct 2 19:26:14.968812 (XEN) VCPU_LR[7]=0 Oct 2 19:26:14.968837 (XEN) VCPU_LR[8]=0 Oct 2 19:26:14.968879 (XEN) VCPU_LR[9]=0 Oct 2 19:26:14.968919 (XEN) VCPU_LR[10]=0 Oct 2 19:26:14.968960 (XEN) VCPU_LR[11]=0 Oct 2 19:26:14.969000 (XEN) VCPU_LR[12]=0 Oct 2 19:26:14.980906 (XEN) VCPU_LR[13]=0 Oct 2 19:26:14.980962 (XEN) VCPU_LR[14]=0 Oct 2 19:26:14.981004 (XEN) VCPU_LR[15]=0 Oct 2 19:26:14.981045 (XEN) No periodic timer Oct 2 19:26:14.981087 (XEN) UNIT95 affinities: hard={0-95} soft={0-95} Oct 2 19:26:14.992901 (XEN) VCPU95: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 2 19:26:14.992965 (XEN) pause_count=0 pause_flags=1 Oct 2 19:26:15.004894 (XEN) GICH_LRs (vcpu 95) mask=0 Oct 2 19:26:15.004953 (XEN) VCPU_LR[0]=0 Oct 2 19:26:15.004996 (XEN) VCPU_LR[1]=0 Oct 2 19:26:15.005036 (XEN) VCPU_LR[2]=0 Oct 2 19:26:15.005077 (XEN) VCPU_LR[3]=0 Oct 2 19:26:15.005117 (XEN) VCPU_LR[4]=0 Oct 2 19:26:15.016897 (XEN) VCPU_LR[5]=0 Oct 2 19:26:15.016953 (XEN) VCPU_LR[6]=0 Oct 2 19:26:15.016995 (XEN) VCPU_LR[7]=0 Oct 2 19:26:15.017036 (XEN) VCPU_LR[8]=0 Oct 2 19:26:15.017076 (XEN) VCPU_LR[9]=0 Oct 2 19:26:15.017117 (XEN) VCPU_LR[10]=0 Oct 2 19:26:15.028875 (XEN) VCPU_LR[11]=0 Oct 2 19:26:15.028931 (XEN) VCPU_LR[12]=0 Oct 2 19:26:15.028973 (XEN) VCPU_LR[13]=0 Oct 2 19:26:15.029014 (XEN) VCPU_LR[14]=0 Oct 2 19:26:15.029073 (XEN) VCPU_LR[15]=0 Oct 2 19:26:15.029117 (XEN) No periodic timer Oct 2 19:26:15.040899 (XEN) Notifying guest 0:0 (virq 1, port 0) Oct 2 19:26:15.040958 (XEN) Notifying guest 0:1 (virq 1, port 0) Oct 2 19:26:15.041004 (XEN) Notifying guest 0:2 (virq 1, port 0) Oct 2 19:26:15.052861 (XEN) Notifying guest 0:3 (virq 1, port 0) Oct 2 19:26:15.052921 (XEN) Notifying guest 0:4 (virq 1, port 0) Oct 2 19:26:15.052966 (XEN) Notifying guest 0:5 (virq 1, port 0) Oct 2 19:26:15.064891 (XEN) Notifying guest 0:6 (virq 1, port 0) Oct 2 19:26:15.064950 (XEN) Notifying guest 0:7 (virq 1, port 0) Oct 2 19:26:15.064995 (XEN) Notifying guest 0:8 (virq 1, port 0) Oct 2 19:26:15.076900 (XEN) Notifying guest 0:9 (virq 1, port 0) Oct 2 19:26:15.076959 (XEN) Notifying guest 0:10 (virq 1, port 0) Oct 2 19:26:15.077004 (XEN) Notifying guest 0:11 (virq 1, port 0) Oct 2 19:26:15.088895 (XEN) Notifying guest 0:12 (virq 1, port 0) Oct 2 19:26:15.088954 (XEN) Notifying guest 0:13 (virq 1, port 0) Oct 2 19:26:15.088999 (XEN) Notifying guest 0:14 (virq 1, port 0) Oct 2 19:26:15.100899 (XEN) Notifying guest 0:15 (virq 1, port 0) Oct 2 19:26:15.100959 (XEN) Notifying guest 0:16 (virq 1, port 0) Oct 2 19:26:15.101005 (XEN) Notifying guest 0:17 (virq 1, port 0) Oct 2 19:26:15.112892 (XEN) Notifying guest 0:18 (virq 1, port 0) Oct 2 19:26:15.112951 (XEN) Notifying guest 0:19 (virq 1, port 0) Oct 2 19:26:15.112996 (XEN) Notifying guest 0:20 (virq 1, port 0) Oct 2 19:26:15.124909 (XEN) Notifying guest 0:21 (virq 1, port 0) Oct 2 19:26:15.124969 (XEN) Notifying guest 0:22 (virq 1, port 0) Oct 2 19:26:15.125014 (XEN) Notifying guest 0:23 (virq 1, port 0) Oct 2 19:26:15.136872 (XEN) Notifying guest 0:24 (virq 1, port 0) Oct 2 19:26:15.136932 (XEN) Notifying guest 0:25 (virq 1, port 0) Oct 2 19:26:15.136978 (XEN) Notifying guest 0:26 (virq 1, port 0) Oct 2 19:26:15.137022 (XEN) Notifying guest 0:27 (virq 1, port 0) Oct 2 19:26:15.148904 (XEN) Notifying guest 0:28 (virq 1, port 0) Oct 2 19:26:15.148963 (XEN) Notifying guest 0:29 (virq 1, port 0) Oct 2 19:26:15.149008 (XEN) Notifying guest 0:30 (virq 1, port 0) Oct 2 19:26:15.160906 (XEN) Notifying guest 0:31 (virq 1, port 0) Oct 2 19:26:15.160966 (XEN) Notifying guest 0:32 (virq 1, port 0) Oct 2 19:26:15.161011 (XEN) Notifying guest 0:33 (virq 1, port 0) Oct 2 19:26:15.172897 (XEN) Notifying guest 0:34 (virq 1, port 0) Oct 2 19:26:15.172956 (XEN) Notifying guest 0:35 (virq 1, port 0) Oct 2 19:26:15.173001 (XEN) Notifying guest 0:36 (virq 1, port 0) Oct 2 19:26:15.184901 (XEN) Notifying guest 0:37 (virq 1, port 0) Oct 2 19:26:15.184960 (XEN) Notifying guest 0:38 (virq 1, port 0) Oct 2 19:26:15.196886 (XEN) Notifying guest 0:39 (virq 1, port 0) Oct 2 19:26:15.196946 (XEN) Notifying guest 0:40 (virq 1, port 0) Oct 2 19:26:15.196997 (XEN) Notifying guest 0:41 (virq 1, port 0) Oct 2 19:26:15.208833 (XEN) Notifying guest 0:42 (virq 1, port 0) Oct 2 19:26:15.208839 (XEN) Notifying guest 0:43 (virq 1, port 0) Oct 2 19:26:15.208884 (XEN) Notifying guest 0:44 (virq 1, port 0) Oct 2 19:26:15.220906 (XEN) Notifying guest 0:45 (virq 1, port 0) Oct 2 19:26:15.220968 (XEN) Notifying guest 0:46 (virq 1, port 0) Oct 2 19:26:15.221014 (XEN) Notifying guest 0:47 (virq 1, port 0) Oct 2 19:26:15.221058 (XEN) Notifying guest 0:48 (virq 1, port 0) Oct 2 19:26:15.232897 (XEN) Notifying guest 0:49 (virq 1, port 0) Oct 2 19:26:15.232956 (XEN) Notifying guest 0:50 (virq 1, port 0) Oct 2 19:26:15.233001 (XEN) Notifying guest 0:51 (virq 1, port 0) Oct 2 19:26:15.244904 (XEN) Notifying guest 0:52 (virq 1, port 0) Oct 2 19:26:15.244963 (XEN) Notifying guest 0:53 (virq 1, port 0) Oct 2 19:26:15.245008 (XEN) Notifying guest 0:54 (virq 1, port 0) Oct 2 19:26:15.256908 (XEN) Notifying guest 0:55 (virq 1, port 0) Oct 2 19:26:15.256966 (XEN) Notifying guest 0:56 (virq 1, port 0) Oct 2 19:26:15.257012 (XEN) Notifying guest 0:57 (virq 1, port 0) Oct 2 19:26:15.268900 (XEN) Notifying guest 0:58 (virq 1, port 0) Oct 2 19:26:15.268978 (XEN) Notifying guest 0:59 (virq 1, port 0) Oct 2 19:26:15.269026 (XEN) Notifying guest 0:60 (virq 1, port 0) Oct 2 19:26:15.280900 (XEN) Notifying guest 0:61 (virq 1, port 0) Oct 2 19:26:15.280959 (XEN) Notifying guest 0:62 (virq 1, port 0) Oct 2 19:26:15.281004 (XEN) Notifying guest 0:63 (virq 1, port 0) Oct 2 19:26:15.292903 (XEN) Notifying guest 0:64 (virq 1, port 0) Oct 2 19:26:15.292962 (XEN) Notifying guest 0:65 (virq 1, port 0) Oct 2 19:26:15.293008 (XEN) Notifying guest 0:66 (virq 1, port 0) Oct 2 19:26:15.304890 (XEN) Notifying guest 0:67 (virq 1, port 0) Oct 2 19:26:15.304950 (XEN) Notifying guest 0:68 (virq 1, port 0) Oct 2 19:26:15.304995 (XEN) Notifying guest 0:69 (virq 1, port 0) Oct 2 19:26:15.316906 (XEN) Notifying guest 0:70 (virq 1, port 0) Oct 2 19:26:15.316964 (XEN) Notifying guest 0:71 (virq 1, port 0) Oct 2 19:26:15.317009 (XEN) Notifying guest 0:72 (virq 1, port 0) Oct 2 19:26:15.328912 (XEN) Notifying guest 0:73 (virq 1, port 0) Oct 2 19:26:15.328971 (XEN) Notifying guest 0:74 (virq 1, port 0) Oct 2 19:26:15.329016 (XEN) Notifying guest 0:75 (virq 1, port 0) Oct 2 19:26:15.340903 (XEN) Notifying guest 0:76 (virq 1, port 0) Oct 2 19:26:15.340962 (XEN) Notifying guest 0:77 (virq 1, port 0) Oct 2 19:26:15.341007 (XEN) Notifying guest 0:78 (virq 1, port 0) Oct 2 19:26:15.352900 (XEN) Notifying guest 0:79 (virq 1, port 0) Oct 2 19:26:15.352958 (XEN) Notifying guest 0:80 (virq 1, port 0) Oct 2 19:26:15.353003 (XEN) Notifying guest 0:81 (virq 1, port 0) Oct 2 19:26:15.364865 (XEN) Notifying guest 0:82 (virq 1, port 0) Oct 2 19:26:15.364924 (XEN) Notifying guest 0:83 (virq 1, port 0) Oct 2 19:26:15.364969 (XEN) Notifying guest 0:84 (virq 1, port 0) Oct 2 19:26:15.376912 (XEN) Notifying guest 0:85 (virq 1, port 0) Oct 2 19:26:15.376971 (XEN) Notifying guest 0:86 (virq 1, port 0) Oct 2 19:26:15.377016 (XEN) Notifying guest 0:87 (virq 1, port 0) Oct 2 19:26:15.388899 (XEN) Notifying guest 0:88 (virq 1, port 0) Oct 2 19:26:15.388958 (XEN) Notifying guest 0:89 (virq 1, port 0) Oct 2 19:26:15.389003 (XEN) Notifying guest 0:90 (virq 1, port 0) Oct 2 19:26:15.400891 (XEN) Notifying guest 0:91 (virq 1, port 0) Oct 2 19:26:15.400951 (XEN) Notifying guest 0:92 (virq 1, port 0) Oct 2 19:26:15.400996 (XEN) Notifying guest 0:93 (virq 1, port 0) Oct 2 19:26:15.412890 (XEN) Notifying guest 0:94 (virq 1, port 0) Oct 2 19:26:15.412950 (XEN) Notifying guest 0:95 (virq 1, port 0) Oct 2 19:26:15.412996 Oct 2 19:26:21.921045 (XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input) Oct 2 19:26:21.944930 Oct 2 19:26:21.946311