Oct 4 01:50:59.963537 (XEN) 0000800ffb31fcf0 00000a000025efb4 0000000000000002 00000a000032e000 Oct 4 01:50:59.963919 (XEN) 0000800ffb31fd40 0000800ffd873ae8 0000800ffb31fd30 00000a000026c114 Oct 4 01:50:59.964008 (XEN) 00000a000034e5b4 000000000000002e 0000800ffb31fe48 0000000000000249 Oct 4 01:50:59.967588 (XEN) 0000000007e00000 000000000000002e 0000800ffb31fe60 00000a000025332c Oct 4 01:50:59.967647 (XEN) 0000000000000000 0000760ffb17a000 0000800ffb492048 ffffffffffffff9e Oct 4 01:50:59.979590 (XEN) 0000000000000000 00000a000034e5a8 00000a000034e5b0 0000800ffb490150 Oct 4 01:50:59.991566 (XEN) 0000000000000012 0000000000000080 7f7f7f7f7f7f7f7f 0101010101010101 Oct 4 01:50:59.991653 (XEN) 0000000000000008 0000000000000020 0000000000000000 fffffc0000b85980 Oct 4 01:51:00.003550 (XEN) ffff8000092a1238 0000000000000000 ffff80000c3f3c58 00000a000034e5b4 Oct 4 01:51:00.003615 (XEN) 000000000000002e 00000a000031f680 0000000000004000 000000000000002e Oct 4 01:51:00.015565 (XEN) 000000000000002e 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.015628 (XEN) 0000000000000000 0000800ffb31fe60 00000a000025d1b0 0000800ffb31fe60 Oct 4 01:51:00.027563 (XEN) 00000a000025d1cc 0000000000000249 0000000007e00000 00000a000025d1b0 Oct 4 01:51:00.039562 (XEN) 0000800ffb31fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:00.039627 (XEN) 000000000000002e 0000000000000000 0000000000000000 000000000000020e Oct 4 01:51:00.051559 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.051623 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.063566 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.063652 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.075569 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.075632 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.087572 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.099577 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.099662 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.111565 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.111629 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.123566 (XEN) Xen call trace: Oct 4 01:51:00.123624 (XEN) [<00000a0000218850>] keyhandler.c#read_clocks_slave+0xf8/0x128 (PC) Oct 4 01:51:00.135548 (XEN) [<00000a000021884c>] keyhandler.c#read_clocks_slave+0xf4/0x128 (LR) Oct 4 01:51:00.135615 (XEN) [<00000a00002240e0>] smp_call_function_interrupt+0x164/0x16c Oct 4 01:51:00.147575 (XEN) [<00000a000025efb4>] gic_interrupt+0x10c/0x110 Oct 4 01:51:00.147638 (XEN) [<00000a000026c114>] do_trap_irq+0x10/0x18 Oct 4 01:51:00.147685 (XEN) [<00000a000025332c>] entry.o#hyp_irq+0x80/0x84 Oct 4 01:51:00.159574 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:00.159637 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:00.169754 (XEN) Oct 4 01:51:00.169783 (XEN) *** Dumping CPU47 host state: *** Oct 4 01:51:00.169809 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:00.183737 (XEN) CPU: 47 Oct 4 01:51:00.183790 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:00.183840 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:00.183883 (XEN) SP: 0000800ffb30fe60 Oct 4 01:51:00.195627 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:00.195720 (XEN) X0: 0000000000000000 X1: 0000760ffaffe000 X2: 0000800ffb316048 Oct 4 01:51:00.207474 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:00.207474 (XEN) X6: 00000a000034e5b0 X7: 0000800ffb490590 X8: 0000000000000012 Oct 4 01:51:00.219452 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Oct 4 01:51:00.219567 (XEN) X12: 0000000000000001 X13: 00000000000003b0 X14: 00000000000003b0 Oct 4 01:51:00.229356 (XEN) X15: 0000ffffffaba9d8 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:00.243584 (XEN) X18: 0000000000000000 X19: 00000a000034e5b4 X20: 000000000000002f Oct 4 01:51:00.243662 (XEN) X21: 00000a000031f700 X22: 0000000000008000 X23: 000000000000002f Oct 4 01:51:00.243738 (XEN) X24: 000000000000002f X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:00.255555 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb30fe60 Oct 4 01:51:00.267568 (XEN) Oct 4 01:51:00.267568 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:00.267653 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:00.267734 (XEN) Oct 4 01:51:00.267743 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:00.279542 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:00.279607 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:00.279672 (XEN) Oct 4 01:51:00.279688 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:00.279688 (XEN) HPFAR_EL2: 0000009010804b00 Oct 4 01:51:00.291503 (XEN) FAR_EL2: ffff80000b4b0100 Oct 4 01:51:00.291526 (XEN) Oct 4 01:51:00.291547 (XEN) Xen stack trace from sp=0000800ffb30fe60: Oct 4 01:51:00.291547 (XEN) 0000800ffb30fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:00.303443 (XEN) 000000000000002f 0000000000000000 0000000000000000 000000000000020f Oct 4 01:51:00.303604 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.315532 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.327513 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.327558 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.339497 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.339551 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.351500 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.351555 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.363494 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.363571 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.375439 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.387569 (XEN) Xen call trace: Oct 4 01:51:00.387569 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:00.387666 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:00.399524 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:00.399613 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:00.411545 (XEN) Oct 4 01:51:00.411545 (XEN) *** Dumping CPU48 host state: *** Oct 4 01:51:00.411623 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:00.411623 (XEN) CPU: 48 Oct 4 01:51:00.411746 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:00.423458 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:00.423548 (XEN) SP: 0000800ffb307e60 Oct 4 01:51:00.423629 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:00.435528 (XEN) X0: 0000000000000000 X1: 0000760ffaffa000 X2: 0000800ffb312048 Oct 4 01:51:00.435620 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:00.447528 (XEN) X6: 00000a000034e5b0 X7: 0000800ffb490a50 X8: 0000000000000012 Oct 4 01:51:00.459498 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:00.459519 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:00.471525 (XEN) X15: ffff00002475bf0c X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:00.471592 (XEN) X18: ffff80000c7a3c58 X19: 00000a000034e5b4 X20: 0000000000000030 Oct 4 01:51:00.483527 (XEN) X21: 00000a000031f780 X22: 0000000000010000 X23: 0000000000000030 Oct 4 01:51:00.483527 (XEN) X24: 0000000000000030 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:00.495515 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffb307e60 Oct 4 01:51:00.495515 (XEN) Oct 4 01:51:00.507559 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:00.507648 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:00.507648 (XEN) Oct 4 01:51:00.507747 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:00.507800 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:00.519568 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:00.519654 (XEN) Oct 4 01:51:00.519654 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:00.519654 (XEN) HPFAR_EL2: 0000009010805b00 Oct 4 01:51:00.519654 (XEN) FAR_EL2: ffff80000b5b0100 Oct 4 01:51:00.531513 (XEN) Oct 4 01:51:00.531513 (XEN) Xen stack trace from sp=0000800ffb307e60: Oct 4 01:51:00.531570 (XEN) 0000800ffb307e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:00.543430 (XEN) 0000000000000030 0000000000000000 0000000000000000 0000000000010000 Oct 4 01:51:00.543430 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.555536 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.555619 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.567438 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.579520 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.579538 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.591559 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.591625 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.603566 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.603653 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.615534 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.615647 (XEN) Xen call trace: Oct 4 01:51:00.627562 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:00.627655 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:00.639543 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:00.639616 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:00.639686 (XEN) Oct 4 01:51:00.639693 (XEN) *** Dumping CPU49 host state: *** Oct 4 01:51:00.651562 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:00.651562 (XEN) CPU: 49 Oct 4 01:51:00.651663 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:00.663590 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:00.663590 (XEN) SP: 0000800f22297e60 Oct 4 01:51:00.663590 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:00.675570 (XEN) X0: 0000000000000000 X1: 0000760ffaff8000 X2: 0000800ffb310048 Oct 4 01:51:00.675669 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:00.687566 (XEN) X6: 00000a000034e5b0 X7: 0000800f2229e010 X8: 0000000000000012 Oct 4 01:51:00.687642 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Oct 4 01:51:00.699560 (XEN) X12: 0000000000000001 X13: 00000000000001f8 X14: 00000000000001f8 Oct 4 01:51:00.711545 (XEN) X15: 00003d0900000000 X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:00.711656 (XEN) X18: 0000000000000006 X19: 00000a000034e5b4 X20: 0000000000000031 Oct 4 01:51:00.723562 (XEN) X21: 00000a000031f800 X22: 0000000000020000 X23: 0000000000000031 Oct 4 01:51:00.723653 (XEN) X24: 0000000000000031 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:00.735561 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f22297e60 Oct 4 01:51:00.735645 (XEN) Oct 4 01:51:00.735645 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:00.747562 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:00.747562 (XEN) Oct 4 01:51:00.747652 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:00.747716 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:00.759565 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:00.759635 (XEN) Oct 4 01:51:00.759651 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:00.759651 (XEN) HPFAR_EL2: 0000008010800700 Oct 4 01:51:00.759651 (XEN) FAR_EL2: ffff80000a870100 Oct 4 01:51:00.771562 (XEN) Oct 4 01:51:00.771562 (XEN) Xen stack trace from sp=0000800f22297e60: Oct 4 01:51:00.771665 (XEN) 0000800f22297e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:00.783614 (XEN) 0000000000000031 0000000000000000 0000000000000000 0000000000010001 Oct 4 01:51:00.783687 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.795541 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.795605 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.807627 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.807691 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.819532 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.831653 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.831716 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.843465 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.843528 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.855551 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:00.855636 (XEN) Xen call trace: Oct 4 01:51:00.867526 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:00.867591 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:00.879525 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:00.879588 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:00.879658 (XEN) Oct 4 01:51:00.879699 (XEN) *** Dumping CPU50 host state: *** Oct 4 01:51:00.891545 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:00.891608 (XEN) CPU: 50 Oct 4 01:51:00.891651 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:00.903534 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:00.903591 (XEN) SP: 0000800f2228fe60 Oct 4 01:51:00.903635 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:00.915532 (XEN) X0: 0000000000000000 X1: 0000760f21f84000 X2: 0000800f2229c048 Oct 4 01:51:00.915597 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:00.927584 (XEN) X6: 00000a000034e5b0 X7: 0000800f2229e410 X8: 0000000000000012 Oct 4 01:51:00.927648 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:00.939567 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:00.939630 (XEN) X15: 0000000000000002 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:00.951595 (XEN) X18: 0000000000000000 X19: 00000a000034e5b4 X20: 0000000000000032 Oct 4 01:51:00.963573 (XEN) X21: 00000a000031f880 X22: 0000000000040000 X23: 0000000000000032 Oct 4 01:51:00.963637 (XEN) X24: 0000000000000032 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:00.975562 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f2228fe60 Oct 4 01:51:00.975627 (XEN) Oct 4 01:51:00.975668 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:00.987576 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:00.987634 (XEN) Oct 4 01:51:00.987675 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:00.987718 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:00.987760 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:00.999577 (XEN) Oct 4 01:51:00.999631 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:00.999676 (XEN) HPFAR_EL2: 0000000000030300 Oct 4 01:51:00.999719 (XEN) FAR_EL2: ffff80000b010100 Oct 4 01:51:01.011575 (XEN) Oct 4 01:51:01.011630 (XEN) Xen stack trace from sp=0000800f2228fe60: Oct 4 01:51:01.011678 (XEN) 0000800f2228fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:01.011728 (XEN) 0000000000000032 0000000000000000 0000000000000000 0000000000010002 Oct 4 01:51:01.023587 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.035576 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.035640 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.047523 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.047586 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.059565 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.059635 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.071511 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.083504 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.083538 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.095498 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.095532 (XEN) Xen call trace: Oct 4 01:51:01.095556 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:01.107515 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:01.107578 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:01.119575 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:01.119636 (XEN) Oct 4 01:51:01.119680 (XEN) *** Dumping CPU51 host state: *** Oct 4 01:51:01.131571 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:01.131635 (XEN) CPU: 51 Oct 4 01:51:01.131678 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:01.143575 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:01.143632 (XEN) SP: 0000800f22287e60 Oct 4 01:51:01.143676 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:01.155577 (XEN) X0: 0000000000000000 X1: 0000760f21f80000 X2: 0000800f22298048 Oct 4 01:51:01.155641 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:01.167575 (XEN) X6: 00000a000034e5b0 X7: 0000800f2229e8d0 X8: 0000000000000012 Oct 4 01:51:01.167640 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:01.179576 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:01.179640 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:01.191590 (XEN) X18: 0000000000000000 X19: 00000a000034e5b4 X20: 0000000000000033 Oct 4 01:51:01.191653 (XEN) X21: 00000a000031f900 X22: 0000000000080000 X23: 0000000000000033 Oct 4 01:51:01.203578 (XEN) X24: 0000000000000033 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:01.215572 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f22287e60 Oct 4 01:51:01.215635 (XEN) Oct 4 01:51:01.215676 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:01.215720 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:01.227599 (XEN) Oct 4 01:51:01.227654 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:01.227699 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:01.227752 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:01.239543 (XEN) Oct 4 01:51:01.239597 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:01.239642 (XEN) HPFAR_EL2: 0000008010801f00 Oct 4 01:51:01.239685 (XEN) FAR_EL2: ffff80000a9f0100 Oct 4 01:51:01.239727 (XEN) Oct 4 01:51:01.239765 (XEN) Xen stack trace from sp=0000800f22287e60: Oct 4 01:51:01.251536 (XEN) 0000800f22287e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:01.251600 (XEN) 0000000000000033 0000000000000000 0000000000000000 0000000000010003 Oct 4 01:51:01.263535 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.263598 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.275539 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.287527 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.287589 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.299530 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.299593 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.311535 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.311598 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.323534 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.335536 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.335598 (XEN) Xen call trace: Oct 4 01:51:01.335642 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:01.347536 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:01.347599 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:01.359595 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:01.359654 (XEN) Oct 4 01:51:01.359695 (XEN) *** Dumping CPU52 host state: *** Oct 4 01:51:01.359739 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:01.371559 (XEN) CPU: 52 Oct 4 01:51:01.371617 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:01.371666 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:01.383530 (XEN) SP: 0000800f223b7e60 Oct 4 01:51:01.383587 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:01.383639 (XEN) X0: 0000000000000000 X1: 0000760f220a6000 X2: 0000800f223be048 Oct 4 01:51:01.395535 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:01.407524 (XEN) X6: 00000a000034e5b0 X7: 0000800f2229ed90 X8: 0000000000000012 Oct 4 01:51:01.407589 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:01.419475 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:01.419538 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:01.431534 (XEN) X18: 0000000000000000 X19: 00000a000034e5b4 X20: 0000000000000034 Oct 4 01:51:01.431597 (XEN) X21: 00000a000031f980 X22: 0000000000100000 X23: 0000000000000034 Oct 4 01:51:01.443534 (XEN) X24: 0000000000000034 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:01.443596 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f223b7e60 Oct 4 01:51:01.455524 (XEN) Oct 4 01:51:01.455577 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:01.455622 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:01.467497 (XEN) Oct 4 01:51:01.467547 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:01.467591 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:01.467635 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:01.467696 (XEN) Oct 4 01:51:01.467737 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:01.479433 (XEN) HPFAR_EL2: 0000000000030500 Oct 4 01:51:01.479433 (XEN) FAR_EL2: ffff80000b030100 Oct 4 01:51:01.479433 (XEN) Oct 4 01:51:01.479433 (XEN) Xen stack trace from sp=0000800f223b7e60: Oct 4 01:51:01.491427 (XEN) 0000800f223b7e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:01.491427 (XEN) 0000000000000034 0000000000000000 0000000000000000 0000000000010004 Oct 4 01:51:01.503447 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.503447 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.519436 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.519436 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.531393 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.531393 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.543419 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.543419 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.555388 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.567529 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.567568 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.579432 (XEN) Xen call trace: Oct 4 01:51:01.579432 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:01.579432 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:01.591409 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:01.591409 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:01.603440 (XEN) Oct 4 01:51:01.603440 (XEN) *** Dumping CPU53 host state: *** Oct 4 01:51:01.603440 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:01.603440 (XEN) CPU: 53 Oct 4 01:51:01.615556 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:01.615624 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:01.615668 (XEN) SP: 0000800f223afe60 Oct 4 01:51:01.615717 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:01.624903 (XEN) X0: 0000000000000000 X1: 0000760f220a2000 X2: 0000800f223ba048 Oct 4 01:51:01.639413 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:01.639413 (XEN) X6: 00000a000034e5b0 X7: 0000800f223bc280 X Oct 4 01:51:01.639810 8: 0000000000000012 Oct 4 01:51:01.651587 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:01.651587 (XEN) X12: 0000000000000008 X13: 0000 Oct 4 01:51:01.653646 000000000020 X14: 0000000000000000 Oct 4 01:51:01.663379 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:01.663379 (XEN) X18: 0000000000000000 X19: 00000a000034e5b4 X20: 0000000000000035 Oct 4 01:51:01.675405 (XEN) X21: 00000a000031fa00 X22: 0000000000200000 X23: 0000000000000035 Oct 4 01:51:01.675405 (XEN) X24: 0000000000000035 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:01.687426 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f223afe60 Oct 4 01:51:01.699120 (XEN) Oct 4 01:51:01.699179 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:01.699225 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:01.699268 (XEN) Oct 4 01:51:01.699306 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:01.699348 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:01.711425 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:01.711425 (XEN) Oct 4 01:51:01.711425 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:01.711425 (XEN) HPFAR_EL2: 0000008010000200 Oct 4 01:51:01.723438 (XEN) FAR_EL2: ffff80000a380090 Oct 4 01:51:01.723438 (XEN) Oct 4 01:51:01.723438 (XEN) Xen stack trace from sp=0000800f223afe60: Oct 4 01:51:01.723438 (XEN) 0000800f223afe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:01.735430 (XEN) 0000000000000035 0000000000000000 0000000000000000 0000000000010005 Oct 4 01:51:01.735430 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.747436 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.747436 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.759444 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.771425 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.771425 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.783422 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.783422 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.795435 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.795435 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.807427 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.819427 (XEN) Xen call trace: Oct 4 01:51:01.819427 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:01.819427 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:01.831449 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:01.831449 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:01.831449 (XEN) Oct 4 01:51:01.843446 (XEN) *** Dumping CPU54 host state: *** Oct 4 01:51:01.843538 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:01.843567 (XEN) CPU: 54 Oct 4 01:51:01.843567 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:01.855563 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:01.855563 (XEN) SP: 0000800f2233fe60 Oct 4 01:51:01.855662 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:01.867564 (XEN) X0: 0000000000000000 X1: 0000760f2208e000 X2: 0000800f223a6048 Oct 4 01:51:01.867656 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:01.879572 (XEN) X6: 00000a000034e5b0 X7: 0000800f223bc740 X8: 0000000000000012 Oct 4 01:51:01.891582 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:01.891657 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:01.903574 (XEN) X15: 0000000000000000 X16: 0000000000000001 X17: 00000000000002af Oct 4 01:51:01.903640 (XEN) X18: 0000000000000000 X19: 00000a000034e5b4 X20: 0000000000000036 Oct 4 01:51:01.915568 (XEN) X21: 00000a000031fa80 X22: 0000000000400000 X23: 0000000000000036 Oct 4 01:51:01.915666 (XEN) X24: 0000000000000036 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:01.927582 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f2233fe60 Oct 4 01:51:01.927649 (XEN) Oct 4 01:51:01.927714 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:01.939480 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:01.939480 (XEN) Oct 4 01:51:01.939554 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:01.939554 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:01.951553 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:01.951638 (XEN) Oct 4 01:51:01.951664 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:01.951664 (XEN) HPFAR_EL2: 0000008010804300 Oct 4 01:51:01.951664 (XEN) FAR_EL2: ffff80000ac30100 Oct 4 01:51:01.963570 (XEN) Oct 4 01:51:01.963645 (XEN) Xen stack trace from sp=0000800f2233fe60: Oct 4 01:51:01.963730 (XEN) 0000800f2233fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:01.975581 (XEN) 0000000000000036 0000000000000000 0000000000000000 0000000000010006 Oct 4 01:51:01.975662 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.987578 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.987639 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.999542 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:01.999615 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.011575 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.023565 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.023629 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.035466 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.035538 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.047458 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.047458 (XEN) Xen call trace: Oct 4 01:51:02.059541 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:02.059541 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:02.071470 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:02.071542 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:02.071613 (XEN) Oct 4 01:51:02.071680 (XEN) *** Dumping CPU55 host state: *** Oct 4 01:51:02.083488 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:02.083564 (XEN) CPU: 55 Oct 4 01:51:02.083628 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:02.095480 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:02.095570 (XEN) SP: 0000800f22337e60 Oct 4 01:51:02.095646 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:02.107471 (XEN) X0: 0000000000000000 X1: 0000760f2208c000 X2: 0000800f223a4048 Oct 4 01:51:02.107578 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:02.119550 (XEN) X6: 00000a000034e5b0 X7: 0000800f223bcc00 X8: 0000000000000012 Oct 4 01:51:02.119638 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Oct 4 01:51:02.131551 (XEN) X12: 0000000000000001 X13: 00000000000000f8 X14: 00000000000000f8 Oct 4 01:51:02.143585 (XEN) X15: 0000000000000000 X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:02.143683 (XEN) X18: 0000000000000000 X19: 00000a000034e5b4 X20: 0000000000000037 Oct 4 01:51:02.155571 (XEN) X21: 00000a000031fb00 X22: 0000000000800000 X23: 0000000000000037 Oct 4 01:51:02.155636 (XEN) X24: 0000000000000037 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:02.167566 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f22337e60 Oct 4 01:51:02.167650 (XEN) Oct 4 01:51:02.167689 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:02.179464 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:02.179464 (XEN) Oct 4 01:51:02.179464 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:02.179543 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:02.179543 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:02.191466 (XEN) Oct 4 01:51:02.191466 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:02.191530 (XEN) HPFAR_EL2: 0000000000030900 Oct 4 01:51:02.191530 (XEN) FAR_EL2: ffff80000b070100 Oct 4 01:51:02.203486 (XEN) Oct 4 01:51:02.203564 (XEN) Xen stack trace from sp=0000800f22337e60: Oct 4 01:51:02.203691 (XEN) 0000800f22337e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:02.215564 (XEN) 0000000000000037 0000000000000000 0000000000000000 0000000000010007 Oct 4 01:51:02.215662 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.227558 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.227624 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.239565 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.239654 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.251557 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.251622 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.263587 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.275540 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.275540 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.287663 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.287734 (XEN) Xen call trace: Oct 4 01:51:02.287778 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:02.299533 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:02.299596 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:02.311606 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:02.311639 (XEN) Oct 4 01:51:02.311662 (XEN) *** Dumping CPU56 host state: *** Oct 4 01:51:02.323532 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:02.323596 (XEN) CPU: 56 Oct 4 01:51:02.323640 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:02.335638 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:02.335697 (XEN) SP: 0000800f22327e60 Oct 4 01:51:02.335742 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:02.347511 (XEN) X0: 0000000000000000 X1: 0000760f22088000 X2: 0000800f223a0048 Oct 4 01:51:02.347576 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:02.359626 (XEN) X6: 00000a000034e5b0 X7: 0000800f2232f150 X8: 0000000000000012 Oct 4 01:51:02.359676 (XEN) X9: 0000000000000000 X10: 00000000000009d0 X11: 0000000000000001 Oct 4 01:51:02.371535 (XEN) X12: 0000000000000001 X13: 0000000000000182 X14: 0000000000000182 Oct 4 01:51:02.371599 (XEN) X15: fffffc0000256dc0 X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:02.383617 (XEN) X18: ffff80000a50bc58 X19: 00000a000034e5b4 X20: 0000000000000038 Oct 4 01:51:02.383652 (XEN) X21: 00000a000031fb80 X22: 0000000001000000 X23: 0000000000000038 Oct 4 01:51:02.395560 (XEN) X24: 0000000000000038 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:02.407631 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f22327e60 Oct 4 01:51:02.407696 (XEN) Oct 4 01:51:02.407737 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:02.407782 (XEN) VTTBR_EL2: 0002010720277000 Oct 4 01:51:02.419660 (XEN) Oct 4 01:51:02.419716 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:02.419763 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:02.419807 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:02.431536 (XEN) Oct 4 01:51:02.431590 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:02.431634 (XEN) HPFAR_EL2: 0000000000030300 Oct 4 01:51:02.431677 (XEN) FAR_EL2: ffff80000b010100 Oct 4 01:51:02.431719 (XEN) Oct 4 01:51:02.431756 (XEN) Xen stack trace from sp=0000800f22327e60: Oct 4 01:51:02.443599 (XEN) 0000800f22327e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:02.443662 (XEN) 0000000000000038 0000000000000000 0000000000000000 0000000000010008 Oct 4 01:51:02.459689 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.459753 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.471550 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.471615 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.483629 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.483693 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.495624 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.507536 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.507599 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.519600 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.519663 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.531587 (XEN) Xen call trace: Oct 4 01:51:02.531645 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:02.531696 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:02.543528 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:02.543590 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:02.555613 (XEN) Oct 4 01:51:02.555667 (XEN) *** Dumping CPU57 host state: *** Oct 4 01:51:02.555713 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:02.567516 (XEN) CPU: 57 Oct 4 01:51:02.567572 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:02.567623 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:02.567666 (XEN) SP: 0000800f1e2bfe60 Oct 4 01:51:02.579558 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:02.579594 (XEN) X0: 0000000000000000 X1: 0000760f22014000 X2: 0000800f2232c048 Oct 4 01:51:02.591546 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:02.591610 (XEN) X6: 00000a000034e5b0 X7: 0000800f2232f590 X8: 0000000000000012 Oct 4 01:51:02.603643 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:02.603706 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:02.615564 (XEN) X15: ffff0000349a0f0c X16: 0000000000000001 X17: 00000000000001fb Oct 4 01:51:02.615628 (XEN) X18: ffff80000c62bc58 X19: 00000a000034e5b4 X20: 0000000000000039 Oct 4 01:51:02.627668 (XEN) X21: 00000a000031fc00 X22: 0000000002000000 X23: 0000000000000039 Oct 4 01:51:02.639544 (XEN) X24: 0000000000000039 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:02.639609 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f1e2bfe60 Oct 4 01:51:02.651640 (XEN) Oct 4 01:51:02.651695 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:02.651740 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:02.651785 (XEN) Oct 4 01:51:02.651823 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:02.663571 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:02.663630 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:02.663677 (XEN) Oct 4 01:51:02.663717 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:02.663760 (XEN) HPFAR_EL2: 0000009010800700 Oct 4 01:51:02.675552 (XEN) FAR_EL2: ffff80000b070100 Oct 4 01:51:02.675611 (XEN) Oct 4 01:51:02.675652 (XEN) Xen stack trace from sp=0000800f1e2bfe60: Oct 4 01:51:02.675699 (XEN) 0000800f1e2bfe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:02.687640 (XEN) 0000000000000039 0000000000000000 0000000000000000 0000000000010009 Oct 4 01:51:02.699560 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.699625 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.711547 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.711610 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.723651 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.723736 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.735542 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.735605 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.747645 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.759562 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.759626 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.771642 (XEN) Xen call trace: Oct 4 01:51:02.771701 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:02.771753 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:02.783547 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:02.783609 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:02.795651 (XEN) Oct 4 01:51:02.795705 (XEN) *** Dumping CPU58 host state: *** Oct 4 01:51:02.795752 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:02.795802 (XEN) CPU: 58 Oct 4 01:51:02.811601 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:02.811665 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:02.811710 (XEN) SP: 0000800f1e2b7e60 Oct 4 01:51:02.811753 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:02.823552 (XEN) X0: 0000000000000000 X1: 0000760f22012000 X2: 0000800f2232a048 Oct 4 01:51:02.823588 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:02.835521 (XEN) X6: 00000a000034e5b0 X7: 0000800f2232fa50 X8: 0000000000000012 Oct 4 01:51:02.835557 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:02.847516 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:02.847579 (XEN) X15: ffff000027951d0c X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:02.859633 (XEN) X18: ffff800010173c58 X19: 00000a000034e5b4 X20: 000000000000003a Oct 4 01:51:02.871558 (XEN) X21: 00000a000031fc80 X22: 0000000004000000 X23: 000000000000003a Oct 4 01:51:02.871623 (XEN) X24: 000000000000003a X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:02.883532 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f1e2b7e60 Oct 4 01:51:02.883589 (XEN) Oct 4 01:51:02.883629 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:02.895534 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:02.895593 (XEN) Oct 4 01:51:02.895634 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:02.895677 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:02.895720 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:02.907587 (XEN) Oct 4 01:51:02.907617 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:02.907674 (XEN) HPFAR_EL2: 0000009010801300 Oct 4 01:51:02.907718 (XEN) FAR_EL2: ffff80000b130100 Oct 4 01:51:02.919538 (XEN) Oct 4 01:51:02.919594 (XEN) Xen stack trace from sp=0000800f1e2b7e60: Oct 4 01:51:02.919643 (XEN) 0000800f1e2b7e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:02.919693 (XEN) 000000000000003a 0000000000000000 0000000000000000 000000000001000a Oct 4 01:51:02.931660 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.943553 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.943617 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.955650 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.955713 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.967547 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.967611 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.979585 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.991542 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:02.991606 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.003658 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.003722 (XEN) Xen call trace: Oct 4 01:51:03.003765 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:03.015569 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:03.015633 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:03.027659 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:03.027720 (XEN) Oct 4 01:51:03.027761 (XEN) *** Dumping CPU59 host state: *** Oct 4 01:51:03.039557 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:03.039622 (XEN) CPU: 59 Oct 4 01:51:03.039666 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:03.051646 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:03.051705 (XEN) SP: 0000800f1e2a7e60 Oct 4 01:51:03.051750 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:03.063529 (XEN) X0: 0000000000000000 X1: 0000760f1df96000 X2: 0000800f1e2ae048 Oct 4 01:51:03.063594 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:03.075608 (XEN) X6: 00000a000034e5b0 X7: 0000800f1e2ad010 X8: 0000000000000012 Oct 4 01:51:03.075672 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:03.087532 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:03.087596 (XEN) X15: ffff000030043d0c X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:03.099636 (XEN) X18: ffff80001080bc58 X19: 00000a000034e5b4 X20: 000000000000003b Oct 4 01:51:03.099700 (XEN) X21: 00000a000031fd00 X22: 0000000008000000 X23: 000000000000003b Oct 4 01:51:03.111528 (XEN) X24: 000000000000003b X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:03.123626 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f1e2a7e60 Oct 4 01:51:03.123691 (XEN) Oct 4 01:51:03.123732 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:03.123785 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:03.135494 (XEN) Oct 4 01:51:03.135547 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:03.135593 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:03.135637 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:03.147578 (XEN) Oct 4 01:51:03.147633 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:03.147678 (XEN) HPFAR_EL2: 0000009010801f00 Oct 4 01:51:03.147722 (XEN) FAR_EL2: ffff80000b1f0100 Oct 4 01:51:03.147764 (XEN) Oct 4 01:51:03.147801 (XEN) Xen stack trace from sp=0000800f1e2a7e60: Oct 4 01:51:03.159448 (XEN) 0000800f1e2a7e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:03.159448 (XEN) 000000000000003b 0000000000000000 0000000000000000 000000000001000b Oct 4 01:51:03.171429 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.171429 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.183421 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.195423 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.195423 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.207480 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.207480 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.219466 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.219466 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.231476 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.243474 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.243474 (XEN) Xen call trace: Oct 4 01:51:03.243474 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:03.255468 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:03.255468 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:03.267473 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:03.267473 (XEN) Oct 4 01:51:03.267473 (XEN) *** Dumping CPU60 host state: *** Oct 4 01:51:03.267473 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:03.279477 (XEN) CPU: 60 Oct 4 01:51:03.279477 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:03.279477 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:03.291478 (XEN) SP: 0000800f1e23fe60 Oct 4 01:51:03.291478 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:03.291478 (XEN) X0: 0000000000000000 X1: 0000760f1df92000 X2: 0000800f1e2aa048 Oct 4 01:51:03.303435 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:03.315482 (XEN) X6: 00000a000034e5b0 X7: 0000800f1e2ad410 X8: 0000000000000012 Oct 4 01:51:03.315482 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:03.327476 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:03.327476 (XEN) X15: ffff000021c1ed0c X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:03.339476 (XEN) X18: ffff80000d8abc58 X19: 00000a000034e5b4 X20: 000000000000003c Oct 4 01:51:03.339476 (XEN) X21: 00000a000031fd80 X22: 0000000010000000 X23: 000000000000003c Oct 4 01:51:03.351462 (XEN) X24: 000000000000003c X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:03.351561 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f1e23fe60 Oct 4 01:51:03.363479 (XEN) Oct 4 01:51:03.363479 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:03.363479 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:03.375467 (XEN) Oct 4 01:51:03.375467 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:03.375467 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:03.375467 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:03.375467 (XEN) Oct 4 01:51:03.375467 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:03.387475 (XEN) HPFAR_EL2: 0000009010802b00 Oct 4 01:51:03.387475 (XEN) FAR_EL2: ffff80000b2b0100 Oct 4 01:51:03.387475 (XEN) Oct 4 01:51:03.387475 (XEN) Xen stack trace from sp=0000800f1e23fe60: Oct 4 01:51:03.399472 (XEN) 0000800f1e23fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:03.399472 (XEN) 000000000000003c 0000000000000000 0000000000000000 000000000001000c Oct 4 01:51:03.411852 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.411892 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.423554 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.435531 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.435595 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.447524 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.447524 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.459566 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.459631 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.471529 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.471611 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.483159 (XEN) Xen call trace: Oct 4 01:51:03.483159 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:03.495528 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:03.495590 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:03.507491 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:03.507512 (XEN) Oct 4 01:51:03.507593 (XEN) *** Dumping CPU61 host state: *** Oct 4 01:51:03.507593 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:03.519385 (XEN) CPU: 61 Oct 4 01:51:03.519385 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:03.519385 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:03.531374 (XEN) SP: 0000800f1e22fe60 Oct 4 01:51:03.531374 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:03.531374 (XEN) X0: 0000000000000000 X1: 0000760f1df90000 X2: 0000800f1e2a8048 Oct 4 01:51:03.542354 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:03.542354 (XEN) X6: 00000a000034e5b0 X7: 0000800f1e2ad8d0 X8: 0000000000000012 Oct 4 01:51:03.555550 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:03.567469 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:03.567469 (XEN) X15: fffffc0000b1b6c0 X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:03.579564 (XEN) X18: ffff80000c713c58 X19: 00000a000034e5b4 X20: 000000000000003d Oct 4 01:51:03.579623 (XEN) X21: 00000a000031fe00 X22: 0000000020000000 X23: 000000000000003d Oct 4 01:51:03.591416 (XEN) X24: 000000000000003d X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:03.591496 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f1e22fe60 Oct 4 01:51:03.603545 (XEN) Oct 4 01:51:03.603545 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:03.603657 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:03.603712 (XEN) Oct 4 01:51:03.615475 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:03.615539 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:03.615539 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:03.615539 (XEN) Oct 4 01:51:03.615539 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:03.625009 (XEN) HPFAR_EL2: 0000009010803700 Oct 4 01:51:03.625009 (XEN) FAR_EL2: ffff80000b370100 Oct 4 01:51:03.625009 (XEN) Oct 4 01:51:03.625009 (XEN) Xen stack trace from sp=0000800f1e22fe60: Oct 4 01:51:03.643447 (XEN) 0000800f1e22fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:03.643447 (XEN) 000000000000003d 0000000000000000 0000000000000000 000000000001000d Oct 4 01:51:03.643447 (XEN) 00000000000 Oct 4 01:51:03.648460 00000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.655530 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.655588 (XE Oct 4 01:51:03.658037 N) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.667538 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.679510 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.679574 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.691533 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.691597 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.702924 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.702993 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.715474 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.727559 (XEN) Xen call trace: Oct 4 01:51:03.727627 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:03.727706 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:03.739526 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:03.739590 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:03.739645 (XEN) Oct 4 01:51:03.751518 (XEN) *** Dumping CPU62 host state: *** Oct 4 01:51:03.751518 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:03.751605 (XEN) CPU: 62 Oct 4 01:51:03.751667 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:03.763518 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:03.763518 (XEN) SP: 0000800f1e227e60 Oct 4 01:51:03.763578 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:03.775507 (XEN) X0: 0000000000000000 X1: 0000760f1df1c000 X2: 0000800f1e234048 Oct 4 01:51:03.775596 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:03.787541 (XEN) X6: 00000a000034e5b0 X7: 0000800f1e2add90 X8: 0000000000000012 Oct 4 01:51:03.799483 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:03.799547 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:03.811504 (XEN) X15: ffff0000313d660c X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:03.811568 (XEN) X18: ffff80001014bc58 X19: 00000a000034e5b4 X20: 000000000000003e Oct 4 01:51:03.823552 (XEN) X21: 00000a000031fe80 X22: 0000000040000000 X23: 000000000000003e Oct 4 01:51:03.823615 (XEN) X24: 000000000000003e X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:03.835469 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800f1e227e60 Oct 4 01:51:03.835469 (XEN) Oct 4 01:51:03.835469 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:03.847562 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:03.847624 (XEN) Oct 4 01:51:03.847663 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:03.847706 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:03.859543 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:03.859601 (XEN) Oct 4 01:51:03.859641 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:03.859683 (XEN) HPFAR_EL2: 0000009010804300 Oct 4 01:51:03.859726 (XEN) FAR_EL2: ffff80000b430100 Oct 4 01:51:03.871536 (XEN) Oct 4 01:51:03.871589 (XEN) Xen stack trace from sp=0000800f1e227e60: Oct 4 01:51:03.871636 (XEN) 0000800f1e227e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:03.883530 (XEN) 000000000000003e 0000000000000000 0000000000000000 000000000001000e Oct 4 01:51:03.883593 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.895540 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.895602 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.907540 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.907601 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.919540 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.931535 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.931597 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.943540 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.943602 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.955536 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:03.955598 (XEN) Xen call trace: Oct 4 01:51:03.967590 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:03.967655 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:03.979552 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:03.979633 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:03.979683 (XEN) Oct 4 01:51:03.979722 (XEN) *** Dumping CPU63 host state: *** Oct 4 01:51:03.991533 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:03.991596 (XEN) CPU: 63 Oct 4 01:51:03.991637 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:04.003537 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:04.003594 (XEN) SP: 0000800fffdbfe60 Oct 4 01:51:04.003637 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:04.015573 (XEN) X0: 0000000000000000 X1: 0000760f1df18000 X2: 0000800f1e230048 Oct 4 01:51:04.015636 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:04.027539 (XEN) X6: 00000a000034e5b0 X7: 0000800f1e233280 X8: 0000000000000012 Oct 4 01:51:04.027603 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:04.039589 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:04.051646 (XEN) X15: ffff00003154760c X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:04.051711 (XEN) X18: ffff80000d8ebc58 X19: 00000a000034e5b4 X20: 000000000000003f Oct 4 01:51:04.063614 (XEN) X21: 00000a000031ff00 X22: 0000000080000000 X23: 000000000000003f Oct 4 01:51:04.063678 (XEN) X24: 000000000000003f X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:04.075541 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffdbfe60 Oct 4 01:51:04.075604 (XEN) Oct 4 01:51:04.075644 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:04.087545 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:04.087603 (XEN) Oct 4 01:51:04.087643 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:04.087686 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:04.087729 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:04.099593 (XEN) Oct 4 01:51:04.099646 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:04.099690 (XEN) HPFAR_EL2: 0000009010804f00 Oct 4 01:51:04.099733 (XEN) FAR_EL2: ffff80000b4f0100 Oct 4 01:51:04.111559 (XEN) Oct 4 01:51:04.111612 (XEN) Xen stack trace from sp=0000800fffdbfe60: Oct 4 01:51:04.111659 (XEN) 0000800fffdbfe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:04.123497 (XEN) 000000000000003f 0000000000000000 0000000000000000 000000000001000f Oct 4 01:51:04.123550 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.135547 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.135609 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.147549 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.147611 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.159536 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.159598 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.171577 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.183519 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.183581 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.195514 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.195576 (XEN) Xen call trace: Oct 4 01:51:04.195619 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:04.207509 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:04.207571 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:04.219536 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:04.219595 (XEN) Oct 4 01:51:04.219634 (XEN) *** Dumping CPU64 host state: *** Oct 4 01:51:04.231523 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:04.231604 (XEN) CPU: 64 Oct 4 01:51:04.231649 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:04.243525 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:04.243582 (XEN) SP: 0000800fffdafe60 Oct 4 01:51:04.243625 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:04.255526 (XEN) X0: 0000000000000000 X1: 0000760fffa9e000 X2: 0000800fffdb6048 Oct 4 01:51:04.255589 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:04.267526 (XEN) X6: 00000a000034e5b0 X7: 0000800f1e233740 X8: 0000000000000012 Oct 4 01:51:04.267590 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:04.279579 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:04.279642 (XEN) X15: 0000000000000000 X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:04.291579 (XEN) X18: 0000000000000000 X19: 00000a000034e5b8 X20: 0000000000000040 Oct 4 01:51:04.303568 (XEN) X21: 00000a000031ff80 X22: 0000000000000001 X23: 0000000000000040 Oct 4 01:51:04.303633 (XEN) X24: 0000000000000040 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:04.315565 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffdafe60 Oct 4 01:51:04.315629 (XEN) Oct 4 01:51:04.315670 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:04.327554 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:04.327614 (XEN) Oct 4 01:51:04.327655 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:04.327698 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:04.327741 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:04.339576 (XEN) Oct 4 01:51:04.339629 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:04.339673 (XEN) HPFAR_EL2: 0000009010805d00 Oct 4 01:51:04.339716 (XEN) FAR_EL2: ffff80000b5d0100 Oct 4 01:51:04.339759 (XEN) Oct 4 01:51:04.339798 (XEN) Xen stack trace from sp=0000800fffdafe60: Oct 4 01:51:04.351567 (XEN) 0000800fffdafe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:04.351631 (XEN) 0000000000000040 0000000000000000 0000000000000000 0000000000010100 Oct 4 01:51:04.363568 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.375531 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.375593 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.387575 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.387637 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.399577 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.399640 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.411577 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.411640 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.423624 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.435605 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.435668 (XEN) Xen call trace: Oct 4 01:51:04.435710 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:04.447591 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:04.447654 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:04.459581 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:04.459640 (XEN) Oct 4 01:51:04.459680 (XEN) *** Dumping CPU65 host state: *** Oct 4 01:51:04.459724 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:04.471571 (XEN) CPU: 65 Oct 4 01:51:04.471626 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:04.483526 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:04.483602 (XEN) SP: 0000800fffda7e60 Oct 4 01:51:04.483649 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:04.483698 (XEN) X0: 0000000000000000 X1: 0000760fffa9a000 X2: 0000800fffdb2048 Oct 4 01:51:04.495530 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:04.507568 (XEN) X6: 00000a000034e5b0 X7: 0000800f1e233c00 X8: 0000000000000012 Oct 4 01:51:04.507632 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:04.519576 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:04.519639 (XEN) X15: 0000000000000002 X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:04.531524 (XEN) X18: 0000000000000000 X19: 00000a000034e5b8 X20: 0000000000000041 Oct 4 01:51:04.531587 (XEN) X21: 00000a0000320000 X22: 0000000000000002 X23: 0000000000000041 Oct 4 01:51:04.543577 (XEN) X24: 0000000000000041 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:04.555568 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffda7e60 Oct 4 01:51:04.555634 (XEN) Oct 4 01:51:04.555673 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:04.555697 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:04.567573 (XEN) Oct 4 01:51:04.567627 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:04.567673 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:04.567718 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:04.567762 (XEN) Oct 4 01:51:04.579574 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:04.579632 (XEN) HPFAR_EL2: 0000000000030900 Oct 4 01:51:04.579677 (XEN) FAR_EL2: ffff80000b070100 Oct 4 01:51:04.579721 (XEN) Oct 4 01:51:04.579760 (XEN) Xen stack trace from sp=0000800fffda7e60: Oct 4 01:51:04.591590 (XEN) 0000800fffda7e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:04.591653 (XEN) 0000000000000041 0000000000000000 0000000000000000 0000000000010101 Oct 4 01:51:04.603591 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.603654 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.615581 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.627570 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.627632 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.639479 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.639513 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.651468 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.651502 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.663537 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.675465 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.675500 (XEN) Xen call trace: Oct 4 01:51:04.675523 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:04.687474 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:04.687508 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:04.699549 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:04.699609 (XEN) Oct 4 01:51:04.699649 (XEN) *** Dumping CPU66 host state: *** Oct 4 01:51:04.699694 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:04.711580 (XEN) CPU: 66 Oct 4 01:51:04.711635 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:04.711685 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:04.723578 (XEN) SP: 0000800fffd37e60 Oct 4 01:51:04.723635 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:04.723686 (XEN) X0: 0000000000000000 X1: 0000760fffa98000 X2: 0000800fffdb0048 Oct 4 01:51:04.735500 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:04.735536 (XEN) X6: 00000a000034e5b0 X7: 0000800fffd3e150 X8: 0000000000000012 Oct 4 01:51:04.747468 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000002 Oct 4 01:51:04.759540 (XEN) X12: 0000000000000001 X13: 00000000000001de X14: 00000000000001de Oct 4 01:51:04.759604 (XEN) X15: 0000aaaae88beca0 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:04.771496 (XEN) X18: 0000000000000000 X19: 00000a000034e5b8 X20: 0000000000000042 Oct 4 01:51:04.771530 (XEN) X21: 00000a0000320080 X22: 0000000000000004 X23: 0000000000000042 Oct 4 01:51:04.783466 (XEN) X24: 0000000000000042 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:04.783501 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffd37e60 Oct 4 01:51:04.795444 (XEN) Oct 4 01:51:04.795473 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:04.795497 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:04.807536 (XEN) Oct 4 01:51:04.807590 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:04.807637 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:04.807682 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:04.807725 (XEN) Oct 4 01:51:04.807764 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:04.819538 (XEN) HPFAR_EL2: 0000000000030900 Oct 4 01:51:04.819597 (XEN) FAR_EL2: ffff80000b070100 Oct 4 01:51:04.819641 (XEN) Oct 4 01:51:04.819680 (XEN) Xen stack trace from sp=0000800fffd37e60: Oct 4 01:51:04.831561 (XEN) 0000800fffd37e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:04.831624 (XEN) 0000000000000042 0000000000000000 0000000000000000 0000000000010102 Oct 4 01:51:04.843556 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.843618 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.855535 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.855598 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.867550 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.879532 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.879594 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.891501 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.891535 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.903467 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.903501 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:04.915440 (XEN) Xen call trace: Oct 4 01:51:04.915471 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:04.927491 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:04.927526 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:04.927553 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:04.939482 (XEN) Oct 4 01:51:04.939536 (XEN) *** Dumping CPU67 host state: *** Oct 4 01:51:04.939583 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:04.951596 (XEN) CPU: 67 Oct 4 01:51:04.951652 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:04.951701 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:04.951742 (XEN) SP: 0000800fffd2fe60 Oct 4 01:51:04.963578 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:04.963578 (XEN) X0: 0000000000000000 X1: 0000760fffa24000 X2: 0000800fffd3c048 Oct 4 01:51:04.975496 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:04.975536 (XEN) X6: 00000a000034e5b0 X7: 0000800fffd3e590 X8: 0000000000000012 Oct 4 01:51:04.987455 (XEN) X9: 0000000000000000 X10: ffff000002408170 X11: 0000000000000040 Oct 4 01:51:04.987490 (XEN) X12: 0000000000000001 X13: 0000000000000000 X14: 0000000000000002 Oct 4 01:51:04.999430 (XEN) X15: ffff80000a05ba10 X16: ffff80000a030000 X17: ffff800016651000 Oct 4 01:51:05.011513 (XEN) X18: ffffffffffffffff X19: 00000a000034e5b8 X20: 0000000000000043 Oct 4 01:51:05.011513 (XEN) X21: 00000a0000320100 X22: 0000000000000008 X23: 0000000000000043 Oct 4 01:51:05.023473 (XEN) X24: 0000000000000043 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:05.023473 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffd2fe60 Oct 4 01:51:05.035401 (XEN) Oct 4 01:51:05.035401 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:05.035401 (XEN) VTTBR_EL2: 0002010720277000 Oct 4 01:51:05.035401 (XEN) Oct 4 01:51:05.035401 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:05.047401 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:05.047401 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:05.047401 (XEN) Oct 4 01:51:05.047401 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:05.059398 (XEN) HPFAR_EL2: 0000000000030900 Oct 4 01:51:05.059398 (XEN) FAR_EL2: ffff80000b070100 Oct 4 01:51:05.059398 (XEN) Oct 4 01:51:05.059398 (XEN) Xen stack trace from sp=0000800fffd2fe60: Oct 4 01:51:05.059398 (XEN) 0000800fffd2fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:05.071398 (XEN) 0000000000000043 0000000000000000 0000000000000000 0000000000010103 Oct 4 01:51:05.083418 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.083418 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.095424 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.095424 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.107461 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.107461 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.119420 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.131423 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.131423 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.143400 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.143400 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.155423 (XEN) Xen call trace: Oct 4 01:51:05.155423 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:05.155423 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:05.167426 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:05.167426 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:05.179547 (XEN) Oct 4 01:51:05.179616 (XEN) *** Dumping CPU68 host state: *** Oct 4 01:51:05.179651 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:05.191462 (XEN) CPU: 68 Oct 4 01:51:05.191462 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:05.191462 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:05.191462 (XEN) SP: 0000800fffd27e60 Oct 4 01:51:05.203471 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:05.203471 (XEN) X0: 0000000000000000 X1: 0000760fffa20000 X2: 0000800fffd38048 Oct 4 01:51:05.215481 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:05.215481 (XEN) X6: 00000a000034e5b0 X7: 0000800fffd3ea50 X8: 0000000000000012 Oct 4 01:51:05.227474 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:05.227474 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:05.239437 (XEN) X15: ffff80000ceabbb0 X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:05.239437 (XEN) X18: ffffffffffffffff X19: 00000a000034e5b8 X20: 0000000000000044 Oct 4 01:51:05.251435 (XEN) X21: 00000a0000320180 X22: 0000000000000010 X23: 0000000000000044 Oct 4 01:51:05.263480 (XEN) X24: 0000000000000044 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:05.263480 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffd27e60 Oct 4 01:51:05.275475 (XEN) Oct 4 01:51:05.275475 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:05.275475 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:05.275475 (XEN) Oct 4 01:51:05.275475 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:05.287430 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:05.287430 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:05.287430 (XEN) Oct 4 01:51:05.287430 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:05.287430 (XEN) HPFAR_EL2: 0000008010000200 Oct 4 01:51:05.299423 (XEN) FAR_EL2: ffff80000a380090 Oct 4 01:51:05.299423 (XEN) Oct 4 01:51:05.299423 (XEN) Xen stack trace from sp=0000800fffd27e60: Oct 4 01:51:05.299423 (XEN) 0000800fffd27e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:05.311470 (XEN) 0000000000000044 0000000000000000 0000000000000000 0000000000010104 Oct 4 01:51:05.311470 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.323475 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.335430 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.335430 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.347446 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.347446 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.359441 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.359441 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.371446 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.383468 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.383468 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.395465 (XEN) Xen call trace: Oct 4 01:51:05.395465 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:05.395465 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:05.407465 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:05.407465 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:05.419426 (XEN) Oct 4 01:51:05.419426 (XEN) *** Dumping CPU69 host state: *** Oct 4 01:51:05.419426 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:05.419426 (XEN) CPU: 69 Oct 4 01:51:05.431570 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:05.431655 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:05.431700 (XEN) SP: 0000800fffcd7e60 Oct 4 01:51:05.431743 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:05.443587 (XEN) X0: 0000000000000000 X1: 0000760fff9c6000 X2: 0000800fffcde048 Oct 4 01:51:05.455413 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:05.455413 (XEN) X6: 00000a000034e5b0 X7: 0000800fffcdc010 X8: 0000000000000012 Oct 4 01:51:05.464860 (XEN) X9: 0000000000000000 X10: ffff000002408170 X11: 0000000000000040 Oct 4 01:51:05.464923 (XEN) X12: 003d090000000000 X13: 0000000000000000 X14: 0000000000061a80 Oct 4 01:51:05.479521 (XEN) X15: 00003d0900000000 X16: ffff80000a030000 X17: ffff800016651000 Oct 4 01:51:05.479561 (XEN) X18: ffffffffffffffff X19: 00000a000034e5b8 X20: 0000000000000045 Oct 4 01:51:05.491466 (XEN) X21: 00000a0000320200 X22: 0000000000000020 X23: 0000000000000045 Oct 4 01:51:05.491466 (XEN) X24: 0000000000000045 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:05.503562 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffcd7e60 Oct 4 01:51:05.515462 (XEN) Oct 4 01:51:05.515462 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:05.515462 (XEN) VTTBR_EL2: 00020107fc629000 Oct 4 01:51:05.515462 (XEN) Oct 4 01:51:05.515462 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:05.515462 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:05.527529 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:05.527596 (XEN) Oct 4 01:51:05.527596 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:05.527596 (XEN) HPFAR_EL2: 0000000000030900 Oct 4 01:51:05.539399 (XEN) FAR_EL2: ffff80000b070100 Oct 4 01:51:05.539399 (XEN) Oct 4 01:51:05.539399 (XEN) Xen stack trace from sp=0000800fffcd7e60: Oct 4 01:51:05.539399 (XEN) 0000800fffcd7e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:05.551377 (XEN) 0000000000000045 0000000000000000 0000000000000000 0000000000010105 Oct 4 01:51:05.551377 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.560860 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.560926 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.575376 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.587406 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.587406 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.599423 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.599423 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.611440 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.611440 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.622711 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.635430 (XEN) Xen call trace: Oct 4 01:51:05.635430 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:05.635430 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:05.645371 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:05.645371 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:05.645371 (X Oct 4 01:51:05.648946 EN) Oct 4 01:51:05.659504 (XEN) *** Dumping CPU70 host state: *** Oct 4 01:51:05.659504 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:05.659504 (XEN) CPU: 70 Oct 4 01:51:05.659504 (XEN) PC Oct 4 01:51:05.661690 : 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:05.671383 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:05.671383 (XEN) SP: 0000800fffccfe60 Oct 4 01:51:05.671383 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:05.683454 (XEN) X0: 0000000000000000 X1: 0000760fff9c2000 X2: 0000800fffcda048 Oct 4 01:51:05.683454 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:05.695412 (XEN) X6: 00000a000034e5b0 X7: 0000800fffcdc410 X8: 0000000000000012 Oct 4 01:51:05.706521 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:05.706590 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:05.719460 (XEN) X15: 000000000a95402a X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:05.719460 (XEN) X18: 0000000000000001 X19: 00000a000034e5b8 X20: 0000000000000046 Oct 4 01:51:05.731460 (XEN) X21: 00000a0000320280 X22: 0000000000000040 X23: 0000000000000046 Oct 4 01:51:05.731460 (XEN) X24: 0000000000000046 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:05.743458 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffccfe60 Oct 4 01:51:05.743458 (XEN) Oct 4 01:51:05.743458 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:05.755451 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:05.755451 (XEN) Oct 4 01:51:05.755451 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:05.755451 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:05.767472 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:05.767472 (XEN) Oct 4 01:51:05.767472 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:05.767472 (XEN) HPFAR_EL2: 0000000000030900 Oct 4 01:51:05.767472 (XEN) FAR_EL2: ffff80000b070100 Oct 4 01:51:05.779479 (XEN) Oct 4 01:51:05.779479 (XEN) Xen stack trace from sp=0000800fffccfe60: Oct 4 01:51:05.779479 (XEN) 0000800fffccfe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:05.791474 (XEN) 0000000000000046 0000000000000000 0000000000000000 0000000000010106 Oct 4 01:51:05.791474 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.803481 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.803481 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.815469 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.815469 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.827483 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.839478 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.839478 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.851515 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.851515 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.863596 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:05.863663 (XEN) Xen call trace: Oct 4 01:51:05.875507 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:05.875543 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:05.887504 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:05.887538 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:05.887564 (XEN) Oct 4 01:51:05.887585 (XEN) *** Dumping CPU71 host state: *** Oct 4 01:51:05.899564 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:05.899628 (XEN) CPU: 71 Oct 4 01:51:05.899670 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:05.911472 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:05.911504 (XEN) SP: 0000800fffc5fe60 Oct 4 01:51:05.911528 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:05.923470 (XEN) X0: 0000000000000000 X1: 0000760fff9ae000 X2: 0000800fffcc6048 Oct 4 01:51:05.923505 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:05.935476 (XEN) X6: 00000a000034e5b0 X7: 0000800fffcdc8d0 X8: 0000000000000012 Oct 4 01:51:05.935511 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000001 Oct 4 01:51:05.947593 (XEN) X12: 0000000000000001 X13: 0000000000000104 X14: 0000000000000104 Oct 4 01:51:05.959573 (XEN) X15: 000000000a95402a X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:05.959637 (XEN) X18: 0000000000000001 X19: 00000a000034e5b8 X20: 0000000000000047 Oct 4 01:51:05.971585 (XEN) X21: 00000a0000320300 X22: 0000000000000080 X23: 0000000000000047 Oct 4 01:51:05.971649 (XEN) X24: 0000000000000047 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:05.983647 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffc5fe60 Oct 4 01:51:05.983713 (XEN) Oct 4 01:51:05.983789 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:05.995621 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:05.995680 (XEN) Oct 4 01:51:05.995720 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:05.995763 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:05.995806 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:06.007532 (XEN) Oct 4 01:51:06.007586 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:06.007630 (XEN) HPFAR_EL2: 0000000000030700 Oct 4 01:51:06.007673 (XEN) FAR_EL2: ffff80000b050100 Oct 4 01:51:06.019609 (XEN) Oct 4 01:51:06.019663 (XEN) Xen stack trace from sp=0000800fffc5fe60: Oct 4 01:51:06.019712 (XEN) 0000800fffc5fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:06.031527 (XEN) 0000000000000047 0000000000000000 0000000000000000 0000000000010107 Oct 4 01:51:06.031583 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.043516 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.043572 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.055491 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.055525 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.067579 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.067644 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.079513 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.091498 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.091554 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.103506 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.103562 (XEN) Xen call trace: Oct 4 01:51:06.103605 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:06.115533 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:06.115592 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:06.127511 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:06.127563 (XEN) Oct 4 01:51:06.127602 (XEN) *** Dumping CPU72 host state: *** Oct 4 01:51:06.139493 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:06.139550 (XEN) CPU: 72 Oct 4 01:51:06.139591 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:06.151501 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:06.151549 (XEN) SP: 0000800fffc57e60 Oct 4 01:51:06.151592 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:06.163554 (XEN) X0: 0000000000000000 X1: 0000760fff9ac000 X2: 0000800fffcc4048 Oct 4 01:51:06.163619 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:06.175502 (XEN) X6: 00000a000034e5b0 X7: 0000800fffcdcd90 X8: 0000000000000012 Oct 4 01:51:06.175567 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Oct 4 01:51:06.187625 (XEN) X12: 0000000000000001 X13: 00000000000002c0 X14: 00000000000002c0 Oct 4 01:51:06.187689 (XEN) X15: 00003d0900000000 X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:06.199525 (XEN) X18: ffff0000266b01a0 X19: 00000a000034e5b8 X20: 0000000000000048 Oct 4 01:51:06.211623 (XEN) X21: 00000a0000320380 X22: 0000000000000100 X23: 0000000000000048 Oct 4 01:51:06.211687 (XEN) X24: 0000000000000048 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:06.223539 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffc57e60 Oct 4 01:51:06.223605 (XEN) Oct 4 01:51:06.223647 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:06.235632 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:06.235695 (XEN) Oct 4 01:51:06.235735 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:06.235814 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:06.235861 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:06.247541 (XEN) Oct 4 01:51:06.247595 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:06.247640 (XEN) HPFAR_EL2: 0000000000030900 Oct 4 01:51:06.247683 (XEN) FAR_EL2: ffff80000b070100 Oct 4 01:51:06.247726 (XEN) Oct 4 01:51:06.259631 (XEN) Xen stack trace from sp=0000800fffc57e60: Oct 4 01:51:06.259694 (XEN) 0000800fffc57e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:06.259746 (XEN) 0000000000000048 0000000000000000 0000000000000000 0000000000010108 Oct 4 01:51:06.271532 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.283630 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.283694 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.295530 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.295593 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.307646 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.307709 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.319532 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.319566 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.331657 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.343547 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.343611 (XEN) Xen call trace: Oct 4 01:51:06.343655 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:06.355656 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:06.355720 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:06.367550 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:06.367611 (XEN) Oct 4 01:51:06.367652 (XEN) *** Dumping CPU73 host state: *** Oct 4 01:51:06.367697 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:06.379655 (XEN) CPU: 73 Oct 4 01:51:06.379711 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:06.391529 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:06.391589 (XEN) SP: 0000800fffc47e60 Oct 4 01:51:06.391635 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:06.391685 (XEN) X0: 0000000000000000 X1: 0000760fff9a8000 X2: 0000800fffcc0048 Oct 4 01:51:06.403621 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:06.415530 (XEN) X6: 00000a000034e5b0 X7: 0000800fffcc2280 X8: 0000000000000012 Oct 4 01:51:06.415595 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:06.427725 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:06.427789 (XEN) X15: ffff00002bdbd70c X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:06.439545 (XEN) X18: ffff8000101dbc58 X19: 00000a000034e5b8 X20: 0000000000000049 Oct 4 01:51:06.439610 (XEN) X21: 00000a0000320400 X22: 0000000000000200 X23: 0000000000000049 Oct 4 01:51:06.451660 (XEN) X24: 0000000000000049 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:06.463532 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800fffc47e60 Oct 4 01:51:06.463598 (XEN) Oct 4 01:51:06.463638 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:06.463683 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:06.475538 (XEN) Oct 4 01:51:06.475592 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:06.475637 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:06.475680 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:06.475722 (XEN) Oct 4 01:51:06.487570 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:06.487630 (XEN) HPFAR_EL2: 0000009010800900 Oct 4 01:51:06.487694 (XEN) FAR_EL2: ffff80000b090100 Oct 4 01:51:06.487741 (XEN) Oct 4 01:51:06.487780 (XEN) Xen stack trace from sp=0000800fffc47e60: Oct 4 01:51:06.499526 (XEN) 0000800fffc47e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:06.499582 (XEN) 0000000000000049 0000000000000000 0000000000000000 0000000000010109 Oct 4 01:51:06.511532 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.511587 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.523521 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.535516 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.535572 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.547503 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.547566 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.559654 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.559717 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.571530 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.583590 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.583655 (XEN) Xen call trace: Oct 4 01:51:06.583698 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:06.595609 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:06.595674 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:06.607602 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:06.607663 (XEN) Oct 4 01:51:06.607704 (XEN) *** Dumping CPU74 host state: *** Oct 4 01:51:06.607750 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:06.619512 (XEN) CPU: 74 Oct 4 01:51:06.619568 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:06.619618 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:06.631651 (XEN) SP: 0000800ffdfdfe60 Oct 4 01:51:06.631709 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:06.631761 (XEN) X0: 0000000000000000 X1: 0000760fff934000 X2: 0000800fffc4c048 Oct 4 01:51:06.643564 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:06.643628 (XEN) X6: 00000a000034e5b0 X7: 0000800fffcc2740 X8: 0000000000000012 Oct 4 01:51:06.655655 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Oct 4 01:51:06.667550 (XEN) X12: 0000000000000000 X13: 0000000000000000 X14: 0000000000000007 Oct 4 01:51:06.667614 (XEN) X15: 00000000001f3fc8 X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:06.679639 (XEN) X18: ffff0000266b01a0 X19: 00000a000034e5b8 X20: 000000000000004a Oct 4 01:51:06.679704 (XEN) X21: 00000a0000320480 X22: 0000000000000400 X23: 000000000000004a Oct 4 01:51:06.691551 (XEN) X24: 000000000000004a X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:06.691616 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdfdfe60 Oct 4 01:51:06.703665 (XEN) Oct 4 01:51:06.703720 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:06.703766 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:06.715486 (XEN) Oct 4 01:51:06.715540 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:06.715585 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:06.715629 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:06.715672 (XEN) Oct 4 01:51:06.715710 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:06.727618 (XEN) HPFAR_EL2: 0000009010801500 Oct 4 01:51:06.727678 (XEN) FAR_EL2: ffff80000b150100 Oct 4 01:51:06.727724 (XEN) Oct 4 01:51:06.727763 (XEN) Xen stack trace from sp=0000800ffdfdfe60: Oct 4 01:51:06.739529 (XEN) 0000800ffdfdfe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:06.739614 (XEN) 000000000000004a 0000000000000000 0000000000000000 000000000001010a Oct 4 01:51:06.751630 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.751694 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.763537 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.763601 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.775643 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.787527 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.787590 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.799639 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.799703 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.811524 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.811588 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.823643 (XEN) Xen call trace: Oct 4 01:51:06.823700 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:06.835568 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:06.835633 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:06.847499 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:06.847553 (XEN) Oct 4 01:51:06.847593 (XEN) *** Dumping CPU75 host state: *** Oct 4 01:51:06.847638 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:06.859525 (XEN) CPU: 75 Oct 4 01:51:06.859573 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:06.859622 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:06.871492 (XEN) SP: 0000800ffdfd7e60 Oct 4 01:51:06.871543 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:06.871594 (XEN) X0: 0000000000000000 X1: 0000760fff932000 X2: 0000800fffc4a048 Oct 4 01:51:06.883547 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:06.883604 (XEN) X6: 00000a000034e5b0 X7: 0000800fffcc2c00 X8: 0000000000000012 Oct 4 01:51:06.895488 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:06.895525 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:06.907455 (XEN) X15: ffff0000302ebe0c X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:06.919582 (XEN) X18: ffff800010043c58 X19: 00000a000034e5b8 X20: 000000000000004b Oct 4 01:51:06.919617 (XEN) X21: 00000a0000320500 X22: 0000000000000800 X23: 000000000000004b Oct 4 01:51:06.931507 (XEN) X24: 000000000000004b X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:06.931545 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdfd7e60 Oct 4 01:51:06.943582 (XEN) Oct 4 01:51:06.943648 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:06.943648 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:06.943648 (XEN) Oct 4 01:51:06.943648 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:06.955626 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:06.955663 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:06.955688 (XEN) Oct 4 01:51:06.955709 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:06.967677 (XEN) HPFAR_EL2: 0000000000030900 Oct 4 01:51:06.967708 (XEN) FAR_EL2: ffff80000b070100 Oct 4 01:51:06.967733 (XEN) Oct 4 01:51:06.967755 (XEN) Xen stack trace from sp=0000800ffdfd7e60: Oct 4 01:51:06.967780 (XEN) 0000800ffdfd7e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:06.979707 (XEN) 000000000000004b 0000000000000000 0000000000000000 000000000001010b Oct 4 01:51:06.991486 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:06.991577 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.003470 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.003559 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.015404 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.015404 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.027545 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.039632 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.039696 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.051644 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.051708 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.063630 (XEN) Xen call trace: Oct 4 01:51:07.063687 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:07.063739 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:07.075599 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:07.075654 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:07.087601 (XEN) Oct 4 01:51:07.087649 (XEN) *** Dumping CPU76 host state: *** Oct 4 01:51:07.087694 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:07.099572 (XEN) CPU: 76 Oct 4 01:51:07.099620 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:07.099668 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:07.099711 (XEN) SP: 0000800ffdfc7e60 Oct 4 01:51:07.111501 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:07.111567 (XEN) X0: 0000000000000000 X1: 0000760ffdcb6000 X2: 0000800ffdfce048 Oct 4 01:51:07.123510 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:07.123574 (XEN) X6: 00000a000034e5b0 X7: 0000800ffdfcd150 X8: 0000000000000012 Oct 4 01:51:07.135549 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:07.135613 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:07.147497 (XEN) X15: ffff00003079ca0c X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:07.147557 (XEN) X18: ffff80000cc83c58 X19: 00000a000034e5b8 X20: 000000000000004c Oct 4 01:51:07.159364 (XEN) X21: 00000a0000320580 X22: 0000000000001000 X23: 000000000000004c Oct 4 01:51:07.171488 (XEN) X24: 000000000000004c X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:07.171568 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdfc7e60 Oct 4 01:51:07.183470 (XEN) Oct 4 01:51:07.183533 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:07.183593 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:07.183643 (XEN) Oct 4 01:51:07.183656 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:07.195399 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:07.195399 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:07.195399 (XEN) Oct 4 01:51:07.195399 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:07.195399 (XEN) HPFAR_EL2: 0000009010802d00 Oct 4 01:51:07.207541 (XEN) FAR_EL2: ffff80000b2d0100 Oct 4 01:51:07.207571 (XEN) Oct 4 01:51:07.207571 (XEN) Xen stack trace from sp=0000800ffdfc7e60: Oct 4 01:51:07.207571 (XEN) 0000800ffdfc7e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:07.219589 (XEN) 000000000000004c 0000000000000000 0000000000000000 000000000001010c Oct 4 01:51:07.219667 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.231540 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.243549 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.243642 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.255512 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.255598 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.267534 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.267621 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.279534 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.291546 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.291613 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.303475 (XEN) Xen call trace: Oct 4 01:51:07.303475 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:07.303475 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:07.315535 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:07.315602 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:07.327374 (XEN) Oct 4 01:51:07.327374 (XEN) *** Dumping CPU77 host state: *** Oct 4 01:51:07.327374 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:07.327374 (XEN) CPU: 77 Oct 4 01:51:07.339548 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:07.339548 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:07.339548 (XEN) SP: 0000800ffdf5fe60 Oct 4 01:51:07.339548 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:07.351423 (XEN) X0: 0000000000000000 X1: 0000760ffdcb2000 X2: 0000800ffdfca048 Oct 4 01:51:07.363457 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:07.363524 (XEN) X6: 00000a000034e5b0 X7: 0000800ffdfcd590 X8: 0000000000000012 Oct 4 01:51:07.375441 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:07.375482 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:07.387524 (XEN) X15: ffff000021c1ff0c X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:07.387607 (XEN) X18: ffff80001016bc58 X19: 00000a000034e5b8 X20: 000000000000004d Oct 4 01:51:07.399603 (XEN) X21: 00000a0000320600 X22: 0000000000002000 X23: 000000000000004d Oct 4 01:51:07.399670 (XEN) X24: 000000000000004d X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:07.411626 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf5fe60 Oct 4 01:51:07.436123 (XEN) Oct 4 01:51:07.436123 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:07.436123 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:07.436123 (XEN) Oct 4 01:51:07.436123 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:07.436123 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:07.436123 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:07.436123 (XEN) Oct 4 01:51:07.436123 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:07.436123 (XEN) HPFAR_EL2: 0000000000030900 Oct 4 01:51:07.447581 (XEN) FAR_EL2: ffff80000b070100 Oct 4 01:51:07.447645 (XEN) Oct 4 01:51:07.447687 (XEN) Xen stack trace from sp=0000800ffdf5fe60: Oct 4 01:51:07.447733 (XEN) 0000800ffdf5fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:07.459551 (XEN) 000000000000004d 0000000000000000 0000000000000000 000000000001010d Oct 4 01:51:07.459607 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.471465 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.471495 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.483551 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.495489 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.495576 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.507407 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.507407 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.519605 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.519676 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.531515 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.543428 (XEN) Xen call trace: Oct 4 01:51:07.543428 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:07.543428 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:07.555499 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:07.555579 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:07.555660 (XEN) Oct 4 01:51:07.567440 (XEN) *** Dumping CPU78 host state: *** Oct 4 01:51:07.567440 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:07.567440 (XEN) CPU: 78 Oct 4 01:51:07.567440 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:07.579543 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:07.579543 (XEN) SP: 0000800ffdf4fe60 Oct 4 01:51:07.579543 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:07.591550 (XEN) X0: 0000000000000000 X1: 0000760ffdcb0000 X2: 0000800ffdfc8048 Oct 4 01:51:07.591613 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:07.603570 (XEN) X6: 00000a000034e5b0 X7: 0000800ffdfcda50 X8: 0000000000000012 Oct 4 01:51:07.615482 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Oct 4 01:51:07.615482 (XEN) X12: 0000000000000001 X13: 0000000000000132 X14: 0000000000000132 Oct 4 01:51:07.627535 (XEN) X15: ffff00002a7bd30c X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:07.627609 (XEN) X18: ffff80000c3f3c58 X19: 00000a000034e5b8 X20: 000000000000004e Oct 4 01:51:07.639491 (XEN) X21: 00000a0000320680 X22: 0000000000004000 X23: 000000000000004e Oct 4 01:51:07.639505 (XEN) X24: 000000000000004e X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:07.651495 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf4fe60 Oct 4 01:51:07.651519 (XEN) Oct 4 01:51:07.663548 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:07.663606 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:07.663638 (XEN) Oct 4 01:51:07.663638 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:07.663638 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:07.675552 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:07.675552 (XEN) Oct 4 01:51:07.675638 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:07.675719 (XEN) HPFAR_EL2: 0000009010804500 Oct 4 01:51:07.675734 (XEN) FAR_EL2: ffff80000b450100 Oct 4 01:51:07.687552 (XEN) Oct 4 01:51:07.687614 (XEN) Xen stack trace from sp=0000800ffdf4fe60: Oct 4 01:51:07.687676 (XEN) 0000800ffdf4fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:07.699575 (XEN) 000000000000004e 0000000000000000 0000000000000000 000000000001010e Oct 4 01:51:07.699654 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.711530 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.711595 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.723565 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.735472 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.735472 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.747456 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.747456 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.759542 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.759628 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.771556 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.771638 (XEN) Xen call trace: Oct 4 01:51:07.783504 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:07.783610 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:07.795553 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:07.795553 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:07.795642 (XEN) Oct 4 01:51:07.795716 (XEN) *** Dumping CPU79 host state: *** Oct 4 01:51:07.811641 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:07.811710 (XEN) CPU: 79 Oct 4 01:51:07.811754 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:07.811803 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:07.823503 (XEN) SP: 0000800ffdf47e60 Oct 4 01:51:07.823552 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:07.823602 (XEN) X0: 0000000000000000 X1: 0000760ffdc3c000 X2: 0000800ffdf54048 Oct 4 01:51:07.835475 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:07.847506 (XEN) X6: 00000a000034e5b0 X7: 0000800ffdf53010 X8: 0000000000000012 Oct 4 01:51:07.847562 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:07.859426 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:07.859457 (XEN) X15: ffff000023e8e10c X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:07.871445 (XEN) X18: ffff8000100d3c58 X19: 00000a000034e5b8 X20: 000000000000004f Oct 4 01:51:07.871499 (XEN) X21: 00000a0000320700 X22: 0000000000008000 X23: 000000000000004f Oct 4 01:51:07.883495 (XEN) X24: 000000000000004f X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:07.883549 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdf47e60 Oct 4 01:51:07.895421 (XEN) Oct 4 01:51:07.895446 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:07.895471 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:07.907392 (XEN) Oct 4 01:51:07.907392 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:07.907392 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:07.907392 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:07.907392 (XEN) Oct 4 01:51:07.907392 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:07.919551 (XEN) HPFAR_EL2: 0000000000030900 Oct 4 01:51:07.919551 (XEN) FAR_EL2: ffff80000b070100 Oct 4 01:51:07.919551 (XEN) Oct 4 01:51:07.919551 (XEN) Xen stack trace from sp=0000800ffdf47e60: Oct 4 01:51:07.931428 (XEN) 0000800ffdf47e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:07.931469 (XEN) 000000000000004f 0000000000000000 0000000000000000 000000000001010f Oct 4 01:51:07.943466 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.943466 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.955555 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.955623 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.967535 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.979589 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.979656 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.991577 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:07.991640 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.003609 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.003673 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.015581 (XEN) Xen call trace: Oct 4 01:51:08.015637 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:08.027614 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:08.027679 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:08.039567 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:08.039627 (XEN) Oct 4 01:51:08.039668 (XEN) *** Dumping CPU80 host state: *** Oct 4 01:51:08.039712 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:08.051538 (XEN) CPU: 80 Oct 4 01:51:08.051594 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:08.051644 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:08.063644 (XEN) SP: 0000800ffdedfe60 Oct 4 01:51:08.063702 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:08.063754 (XEN) X0: 0000000000000000 X1: 0000760ffdc38000 X2: 0000800ffdf50048 Oct 4 01:51:08.075535 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:08.075599 (XEN) X6: 00000a000034e5b0 X7: 0000800ffdf53410 X8: 0000000000000012 Oct 4 01:51:08.087630 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:08.099545 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:08.099609 (XEN) X15: ffff000025c27a0c X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:08.111589 (XEN) X18: ffff80000cc33c58 X19: 00000a000034e5b8 X20: 0000000000000050 Oct 4 01:51:08.111654 (XEN) X21: 00000a0000320780 X22: 0000000000010000 X23: 0000000000000050 Oct 4 01:51:08.123563 (XEN) X24: 0000000000000050 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:08.123626 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdedfe60 Oct 4 01:51:08.135531 (XEN) Oct 4 01:51:08.135577 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:08.135621 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:08.135665 (XEN) Oct 4 01:51:08.147573 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:08.147631 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:08.147677 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:08.147720 (XEN) Oct 4 01:51:08.147758 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:08.159505 (XEN) HPFAR_EL2: 0000009010805f00 Oct 4 01:51:08.159538 (XEN) FAR_EL2: ffff80000b5f0100 Oct 4 01:51:08.159562 (XEN) Oct 4 01:51:08.159583 (XEN) Xen stack trace from sp=0000800ffdedfe60: Oct 4 01:51:08.171496 (XEN) 0000800ffdedfe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:08.171560 (XEN) 0000000000000050 0000000000000000 0000000000000000 0000000000010200 Oct 4 01:51:08.183445 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.183501 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.195432 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.195485 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.207473 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.207528 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.219511 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.231505 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.231559 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.243508 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.243561 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.255575 (XEN) Xen call trace: Oct 4 01:51:08.255654 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:08.267571 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:08.267637 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:08.267687 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:08.279573 (XEN) Oct 4 01:51:08.279627 (XEN) *** Dumping CPU81 host state: *** Oct 4 01:51:08.279674 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:08.291575 (XEN) CPU: 81 Oct 4 01:51:08.291631 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:08.291680 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:08.291722 (XEN) SP: 0000800ffdecfe60 Oct 4 01:51:08.303573 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:08.303638 (XEN) X0: 0000000000000000 X1: 0000760ffdbbe000 X2: 0000800ffded6048 Oct 4 01:51:08.315575 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:08.315638 (XEN) X6: 00000a000034e5b0 X7: 0000800ffdf538d0 X8: 0000800ffc448000 Oct 4 01:51:08.327583 (XEN) X9: 0000000000000000 X10: ffff000002408170 X11: 0000000000000040 Oct 4 01:51:08.327646 (XEN) X12: 0000000000000001 X13: 0000000000000145 X14: 0000000000000145 Oct 4 01:51:08.339585 (XEN) X15: ffff000002dc8d58 X16: ffff80000a028000 X17: ffff80001663c000 Oct 4 01:51:08.351579 (XEN) X18: 0000000000000000 X19: 00000a000034e5b8 X20: 0000000000000051 Oct 4 01:51:08.351643 (XEN) X21: 00000a0000320800 X22: 0000000000020000 X23: 0000000000000051 Oct 4 01:51:08.363581 (XEN) X24: 0000000000000051 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:08.363644 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdecfe60 Oct 4 01:51:08.375577 (XEN) Oct 4 01:51:08.375630 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:08.375675 (XEN) VTTBR_EL2: 0002010720277000 Oct 4 01:51:08.375718 (XEN) Oct 4 01:51:08.375757 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:08.387577 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:08.387635 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:08.387679 (XEN) Oct 4 01:51:08.387718 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:08.387762 (XEN) HPFAR_EL2: 0000000000030700 Oct 4 01:51:08.399580 (XEN) FAR_EL2: ffff80000b050100 Oct 4 01:51:08.399638 (XEN) Oct 4 01:51:08.399678 (XEN) Xen stack trace from sp=0000800ffdecfe60: Oct 4 01:51:08.399724 (XEN) 0000800ffdecfe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:08.411603 (XEN) 0000000000000051 0000000000000000 0000000000000000 0000000000010201 Oct 4 01:51:08.423642 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.423706 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.435550 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.435614 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.447652 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.447716 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.459514 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.459577 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.471621 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.483472 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.483472 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.495470 (XEN) Xen call trace: Oct 4 01:51:08.495470 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:08.495470 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:08.507391 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:08.507391 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:08.519470 (XEN) Oct 4 01:51:08.519470 (XEN) *** Dumping CPU82 host state: *** Oct 4 01:51:08.519470 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:08.519470 (XEN) CPU: 82 Oct 4 01:51:08.531465 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:08.531465 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:08.531465 (XEN) SP: 0000800ffdec7e60 Oct 4 01:51:08.543474 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:08.543474 (XEN) X0: 0000000000000000 X1: 0000760ffdbba000 X2: 0000800ffded2048 Oct 4 01:51:08.555428 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:08.555428 (XEN) X6: 00000a000034e5b0 X7: 0000800ffdf53d90 X8: 0000000000000012 Oct 4 01:51:08.567446 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Oct 4 01:51:08.567446 (XEN) X12: 0000000000000001 X13: 0000000000000194 X14: 0000000000000194 Oct 4 01:51:08.579448 (XEN) X15: 00000000cbb2c614 X16: 000000007487c13d X17: ffff800009f155d0 Oct 4 01:51:08.579448 (XEN) X18: ffff80000c703d48 X19: 00000a000034e5b8 X20: 0000000000000052 Oct 4 01:51:08.591438 (XEN) X21: 00000a0000320880 X22: 0000000000040000 X23: 0000000000000052 Oct 4 01:51:08.603445 (XEN) X24: 0000000000000052 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:08.603445 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffdec7e60 Oct 4 01:51:08.615449 (XEN) Oct 4 01:51:08.615449 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:08.615449 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:08.615449 (XEN) Oct 4 01:51:08.615449 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:08.627469 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:08.627469 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:08.627469 (XEN) Oct 4 01:51:08.627469 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:08.627469 (XEN) HPFAR_EL2: 0000008010801700 Oct 4 01:51:08.639467 (XEN) FAR_EL2: ffff80000a970100 Oct 4 01:51:08.639467 (XEN) Oct 4 01:51:08.639467 (XEN) Xen stack trace from sp=0000800ffdec7e60: Oct 4 01:51:08.639467 (XEN) 0000800ffdec7e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:08.651466 (XEN) 0000000000000052 0000000000000000 0000000000000000 0000000000010202 Oct 4 01:51:08.651466 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.663468 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.675410 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.675410 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.687374 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.687374 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.699366 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.699366 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.711372 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.723383 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.723383 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.735381 (XEN) Xen call trace: Oct 4 01:51:08.735381 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:08.735381 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:08.747381 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:08.747381 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:08.759386 (XEN) Oct 4 01:51:08.759386 (XEN) *** Dumping CPU83 host state: *** Oct 4 01:51:08.759386 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:08.759386 (XEN) CPU: 83 Oct 4 01:51:08.759386 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:08.771422 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:08.771422 (XEN) SP: 0000800ffde77e60 Oct 4 01:51:08.771422 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:08.783468 (XEN) X0: 0000000000000000 X1: 0000760ffdb66000 X2: 0000800ffde7e048 Oct 4 01:51:08.783468 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:08.795474 (XEN) X6: 00000a000034e5b0 X7: 0000800ffded1280 X8: 0000000000000012 Oct 4 01:51:08.807480 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:08.807480 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:08.819471 (XEN) X15: ffff00003055910c X16: 0000000000000001 X17: 0000000000000212 Oct 4 01:51:08.819471 (XEN) X18: ffff80000da43c58 X19: 00000a000034e5b8 X20: 0000000000000053 Oct 4 01:51:08.831643 (XEN) X21: 00000a0000320900 X22: 0000000000080000 X23: 0000000000000053 Oct 4 01:51:08.831715 (XEN) X24: 0000000000000053 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:08.843593 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde77e60 Oct 4 01:51:08.855569 (XEN) Oct 4 01:51:08.855623 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:08.855668 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:08.855712 (XEN) Oct 4 01:51:08.855749 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:08.855791 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:08.867583 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:08.867641 (XEN) Oct 4 01:51:08.867681 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:08.867724 (XEN) HPFAR_EL2: 0000000000030700 Oct 4 01:51:08.867766 (XEN) FAR_EL2: ffff80000b050100 Oct 4 01:51:08.879576 (XEN) Oct 4 01:51:08.879629 (XEN) Xen stack trace from sp=0000800ffde77e60: Oct 4 01:51:08.879676 (XEN) 0000800ffde77e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:08.891515 (XEN) 0000000000000053 0000000000000000 0000000000000000 0000000000010203 Oct 4 01:51:08.891550 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.903577 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.903641 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.915584 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.927654 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.927718 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.939543 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.939606 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.951515 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.951579 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.963588 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:08.975573 (XEN) Xen call trace: Oct 4 01:51:08.975631 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:08.975682 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:08.987548 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:08.987611 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:08.987656 (XEN) Oct 4 01:51:08.987695 (XEN) *** Dumping CPU84 host state: *** Oct 4 01:51:08.999470 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:08.999524 (XEN) CPU: 84 Oct 4 01:51:08.999565 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:09.011505 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:09.011555 (XEN) SP: 0000800ffde6fe60 Oct 4 01:51:09.011598 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:09.023495 (XEN) X0: 0000000000000000 X1: 0000760ffdb64000 X2: 0000800ffde7c048 Oct 4 01:51:09.023559 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:09.035455 (XEN) X6: 00000a000034e5b0 X7: 0000800ffded1740 X8: 0000000000000012 Oct 4 01:51:09.035511 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:09.047443 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:09.059432 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:09.059485 (XEN) X18: 0000000000000000 X19: 00000a000034e5b8 X20: 0000000000000054 Oct 4 01:51:09.071432 (XEN) X21: 00000a0000320980 X22: 0000000000100000 X23: 0000000000000054 Oct 4 01:51:09.071485 (XEN) X24: 0000000000000054 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:09.083519 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde6fe60 Oct 4 01:51:09.083583 (XEN) Oct 4 01:51:09.083608 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:09.095467 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:09.095518 (XEN) Oct 4 01:51:09.095557 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:09.095600 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:09.107442 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:09.107492 (XEN) Oct 4 01:51:09.107531 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:09.107574 (XEN) HPFAR_EL2: 0000008010000200 Oct 4 01:51:09.107617 (XEN) FAR_EL2: ffff80000a380090 Oct 4 01:51:09.119463 (XEN) Oct 4 01:51:09.119506 (XEN) Xen stack trace from sp=0000800ffde6fe60: Oct 4 01:51:09.119552 (XEN) 0000800ffde6fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:09.131505 (XEN) 0000000000000054 0000000000000000 0000000000000000 0000000000010204 Oct 4 01:51:09.131557 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.143507 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.143562 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.155580 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.155643 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.167507 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.179486 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.179549 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.191469 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.191525 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.203484 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.203541 (XEN) Xen call trace: Oct 4 01:51:09.215451 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:09.215508 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:09.227528 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:09.227564 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:09.227589 (XEN) Oct 4 01:51:09.227611 (XEN) *** Dumping CPU85 host state: *** Oct 4 01:51:09.239460 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:09.239518 (XEN) CPU: 85 Oct 4 01:51:09.239561 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:09.251448 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:09.251497 (XEN) SP: 0000800ffde67e60 Oct 4 01:51:09.251541 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:09.263476 (XEN) X0: 0000000000000000 X1: 0000760ffdb60000 X2: 0000800ffde78048 Oct 4 01:51:09.263562 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:09.275462 (XEN) X6: 00000a000034e5b0 X7: 0000800ffded1c00 X8: 0000000000000012 Oct 4 01:51:09.275519 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:09.287521 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:09.287552 (XEN) X15: 2d7473616369746c X16: 00000000deadbeef X17: 3030303046464646 Oct 4 01:51:09.299558 (XEN) X18: 0000000000000000 X19: 00000a000034e5b8 X20: 0000000000000055 Oct 4 01:51:09.311541 (XEN) X21: 00000a0000320a00 X22: 0000000000200000 X23: 0000000000000055 Oct 4 01:51:09.311604 (XEN) X24: 0000000000000055 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:09.323553 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffde67e60 Oct 4 01:51:09.323618 (XEN) Oct 4 01:51:09.323659 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:09.335571 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:09.335629 (XEN) Oct 4 01:51:09.335670 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:09.335714 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:09.335757 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:09.347582 (XEN) Oct 4 01:51:09.347636 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:09.347682 (XEN) HPFAR_EL2: 0000000000030300 Oct 4 01:51:09.347725 (XEN) FAR_EL2: ffff80000b010100 Oct 4 01:51:09.359574 (XEN) Oct 4 01:51:09.359630 (XEN) Xen stack trace from sp=0000800ffde67e60: Oct 4 01:51:09.359679 (XEN) 0000800ffde67e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:09.359729 (XEN) 0000000000000055 0000000000000000 0000000000000000 0000000000010205 Oct 4 01:51:09.371593 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.383575 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.383640 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.395577 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.395642 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.407582 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.407646 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.419545 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.431526 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.431588 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.443535 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.443597 (XEN) Xen call trace: Oct 4 01:51:09.443641 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:09.455540 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:09.455603 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:09.467532 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:09.467592 (XEN) Oct 4 01:51:09.467632 (XEN) *** Dumping CPU86 host state: *** Oct 4 01:51:09.479549 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:09.479624 (XEN) CPU: 86 Oct 4 01:51:09.479666 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:09.491570 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:09.491628 (XEN) SP: 0000800ffd9f7e60 Oct 4 01:51:09.491673 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:09.503568 (XEN) X0: 0000000000000000 X1: 0000760ffd6e6000 X2: 0000800ffd9fe048 Oct 4 01:51:09.503633 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:09.515581 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd9fc150 X8: 0000000000000012 Oct 4 01:51:09.515665 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:09.527587 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:09.527650 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:09.539592 (XEN) X18: 0000000000000000 X19: 00000a000034e5b8 X20: 0000000000000056 Oct 4 01:51:09.539655 (XEN) X21: 00000a0000320a80 X22: 0000000000400000 X23: 0000000000000056 Oct 4 01:51:09.551585 (XEN) X24: 0000000000000056 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:09.563576 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd9f7e60 Oct 4 01:51:09.563641 (XEN) Oct 4 01:51:09.563681 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:09.563725 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:09.575563 (XEN) Oct 4 01:51:09.575616 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:09.575662 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:09.575705 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:09.587482 (XEN) Oct 4 01:51:09.587528 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:09.587571 (XEN) HPFAR_EL2: 0000008010804700 Oct 4 01:51:09.587613 (XEN) FAR_EL2: ffff80000ac70100 Oct 4 01:51:09.587656 (XEN) Oct 4 01:51:09.587694 (XEN) Xen stack trace from sp=0000800ffd9f7e60: Oct 4 01:51:09.599589 (XEN) 0000800ffd9f7e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:09.599653 (XEN) 0000000000000056 0000000000000000 0000000000000000 0000000000010206 Oct 4 01:51:09.611512 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.611575 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.623502 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.635447 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.635502 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.647436 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.647490 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.659432 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.659485 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.671440 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.683494 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.683529 (XEN) Xen call trace: Oct 4 01:51:09.683553 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:09.695412 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:09.695412 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:09.707380 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:09.707380 (XEN) Oct 4 01:51:09.707380 (XEN) *** Dumping CPU87 host state: *** Oct 4 01:51:09.707380 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:09.719375 (XEN) CPU: 87 Oct 4 01:51:09.719375 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:09.719375 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:09.731400 (XEN) SP: 0000800ffd9efe60 Oct 4 01:51:09.731400 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:09.731400 (XEN) X0: 0000000000000000 X1: 0000760ffd6e2000 X2: 0000800ffd9fa048 Oct 4 01:51:09.743405 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:09.755400 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd9fc590 X8: 0000000000000012 Oct 4 01:51:09.755400 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000000 Oct 4 01:51:09.767398 (XEN) X12: 0000000000000001 X13: 0000000000000066 X14: 0000000000000066 Oct 4 01:51:09.767398 (XEN) X15: ffff0000296fdd58 X16: 0000000000000001 X17: 0000000000000000 Oct 4 01:51:09.779398 (XEN) X18: ffff0000266b01a0 X19: 00000a000034e5b8 X20: 0000000000000057 Oct 4 01:51:09.779398 (XEN) X21: 00000a0000320b00 X22: 0000000000800000 X23: 0000000000000057 Oct 4 01:51:09.791407 (XEN) X24: 0000000000000057 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:09.791407 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd9efe60 Oct 4 01:51:09.803366 (XEN) Oct 4 01:51:09.803366 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:09.803366 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:09.815444 (XEN) Oct 4 01:51:09.815444 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:09.815444 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:09.815444 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:09.815444 (XEN) Oct 4 01:51:09.815444 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:09.827444 (XEN) HPFAR_EL2: 0000000000030700 Oct 4 01:51:09.827444 (XEN) FAR_EL2: ffff80000b050100 Oct 4 01:51:09.827444 (XEN) Oct 4 01:51:09.827444 (XEN) Xen stack trace from sp=0000800ffd9efe60: Oct 4 01:51:09.839469 (XEN) 0000800ffd9efe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:09.839469 (XEN) 0000000000000057 0000000000000000 0000000000000000 0000000000010207 Oct 4 01:51:09.851457 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.851457 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.863468 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.863468 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.875454 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.887451 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.887451 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.899411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.899411 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.911367 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.911367 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:09.923441 (XEN) Xen call trace: Oct 4 01:51:09.923441 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:09.935437 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:09.935437 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:09.947469 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:09.947469 (XEN) Oct 4 01:51:09.947469 (XEN) *** Dumping CPU88 host state: *** Oct 4 01:51:09.947469 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:09.959477 (XEN) CPU: 88 Oct 4 01:51:09.959477 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:09.959477 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:09.971476 (XEN) SP: 0000800ffd97fe60 Oct 4 01:51:09.971476 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:09.971476 (XEN) X0: 0000000000000000 X1: 0000760ffd6ce000 X2: 0000800ffd9e6048 Oct 4 01:51:09.983486 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:09.983486 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd9fca50 X8: 0000000000000012 Oct 4 01:51:09.995427 (XEN) X9: 0000000000000080 X10: 0000000000000000 X11: 0000000000000086 Oct 4 01:51:10.007577 (XEN) X12: 0000000000000000 X13: 0000000000000082 X14: 00000000000001a7 Oct 4 01:51:10.007645 (XEN) X15: 0000ffffd865ea88 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:10.019466 (XEN) X18: 0000000000000000 X19: 00000a000034e5b8 X20: 0000000000000058 Oct 4 01:51:10.019542 (XEN) X21: 00000a0000320b80 X22: 0000000001000000 X23: 0000000000000058 Oct 4 01:51:10.031374 (XEN) X24: 0000000000000058 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:10.031374 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd97fe60 Oct 4 01:51:10.043471 (XEN) Oct 4 01:51:10.043523 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:10.043567 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:10.043610 (XEN) Oct 4 01:51:10.055436 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:10.055485 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:10.055528 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:10.055570 (XEN) Oct 4 01:51:10.055608 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:10.067457 (XEN) HPFAR_EL2: 0000008010805f00 Oct 4 01:51:10.067506 (XEN) FAR_EL2: ffff80000adf0100 Oct 4 01:51:10.067549 (XEN) Oct 4 01:51:10.067587 (XEN) Xen stack trace from sp=0000800ffd97fe60: Oct 4 01:51:10.079503 (XEN) 0000800ffd97fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:10.079559 (XEN) 0000000000000058 0000000000000000 0000000000000000 0000000000010208 Oct 4 01:51:10.091480 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.091547 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.103384 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.103384 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.115368 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.127375 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.127375 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.139368 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.139368 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.151364 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.151364 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.163376 (XEN) Xen call trace: Oct 4 01:51:10.163376 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:10.175362 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:10.175362 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:10.175362 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:10.187390 (XEN) Oct 4 01:51:10.187390 (XEN) *** Dumping CPU89 host state: *** Oct 4 01:51:10.187390 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:10.199394 (XEN) CPU: 89 Oct 4 01:51:10.199394 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:10.199394 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:10.199394 (XEN) SP: 0000800ffd977e60 Oct 4 01:51:10.211451 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:10.211451 (XEN) X0: 0000000000000000 X1: 0000760ffd6cc000 X2: 0000800ffd9e4048 Oct 4 01:51:10.223474 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:10.223474 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd9e2010 X8: 0000000000000012 Oct 4 01:51:10.235449 (XEN) X9: 0000000000000000 X10: 00000000000009d0 X11: 0000000000000001 Oct 4 01:51:10.235449 (XEN) X12: 0000000000000001 X13: 0000000000000111 X14: 0000000000000111 Oct 4 01:51:10.247370 (XEN) X15: 0000000000000000 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:10.259363 (XEN) X18: 0000000000000000 X19: 00000a000034e5b8 X20: 0000000000000059 Oct 4 01:51:10.259363 (XEN) X21: 00000a0000320c00 X22: 0000000002000000 X23: 0000000000000059 Oct 4 01:51:10.271389 (XEN) X24: 0000000000000059 X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:10.271389 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd977e60 Oct 4 01:51:10.283411 (XEN) Oct 4 01:51:10.283411 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:10.283411 (XEN) VTTBR_EL2: 0002010720277000 Oct 4 01:51:10.283411 (XEN) Oct 4 01:51:10.283529 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:10.295397 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:10.295397 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:10.295397 (XEN) Oct 4 01:51:10.295397 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:10.295397 (XEN) HPFAR_EL2: 0000000000030700 Oct 4 01:51:10.307527 (XEN) FAR_EL2: ffff80000b050100 Oct 4 01:51:10.307565 (XEN) Oct 4 01:51:10.307565 (XEN) Xen stack trace from sp=0000800ffd977e60: Oct 4 01:51:10.307565 (XEN) 0000800ffd977e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:10.319601 (XEN) 0000000000000059 0000000000000000 0000000000000000 0000000000010209 Oct 4 01:51:10.331573 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.331636 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.343581 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.343644 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.355580 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.355643 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.367589 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.379566 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.379631 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.391615 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.391678 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.403598 (XEN) Xen call trace: Oct 4 01:51:10.403655 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:10.403705 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:10.415480 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:10.415535 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:10.427403 (XEN) Oct 4 01:51:10.427403 (XEN) *** Dumping CPU90 host state: *** Oct 4 01:51:10.427403 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:10.439508 (XEN) CPU: 90 Oct 4 01:51:10.439533 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:10.439533 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:10.439533 (XEN) SP: 0000800ffd967e60 Oct 4 01:51:10.451542 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:10.451607 (XEN) X0: 0000000000000000 X1: 0000760ffd6c8000 X2: 0000800ffd9e0048 Oct 4 01:51:10.463358 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:10.463358 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd9e2410 X8: 0000000000000012 Oct 4 01:51:10.475505 (XEN) X9: 0000000000000080 X10: 0000000000000000 X11: 0000000000000021 Oct 4 01:51:10.475572 (XEN) X12: 0000000000000000 X13: 00000000000001e9 X14: ffff80000dfabc98 Oct 4 01:51:10.487380 (XEN) X15: 0000ffffc5b48528 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:10.487380 (XEN) X18: 0000000000000000 X19: 00000a000034e5b8 X20: 000000000000005a Oct 4 01:51:10.499374 (XEN) X21: 00000a0000320c80 X22: 0000000004000000 X23: 000000000000005a Oct 4 01:51:10.511361 (XEN) X24: 000000000000005a X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:10.511361 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd967e60 Oct 4 01:51:10.523354 (XEN) Oct 4 01:51:10.523354 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:10.523354 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:10.523354 (XEN) Oct 4 01:51:10.523354 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:10.535413 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:10.535413 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:10.535413 (XEN) Oct 4 01:51:10.535413 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:10.535413 (XEN) HPFAR_EL2: 0000009010801700 Oct 4 01:51:10.547472 (XEN) FAR_EL2: ffff80000b170100 Oct 4 01:51:10.547472 (XEN) Oct 4 01:51:10.547472 (XEN) Xen stack trace from sp=0000800ffd967e60: Oct 4 01:51:10.547472 (XEN) 0000800ffd967e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:10.559469 (XEN) 000000000000005a 0000000000000000 0000000000000000 000000000001020a Oct 4 01:51:10.559469 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.571468 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.583486 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.583486 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.595465 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.595465 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.607438 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.607438 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.619398 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.631417 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.631417 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.643431 (XEN) Xen call trace: Oct 4 01:51:10.643431 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:10.643431 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:10.655469 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:10.655469 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:10.667431 (XEN) Oct 4 01:51:10.667431 (XEN) *** Dumping CPU91 host state: *** Oct 4 01:51:10.667431 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:10.667431 (XEN) CPU: 91 Oct 4 01:51:10.679438 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:10.679438 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:10.679438 (XEN) SP: 0000800ffd8ffe60 Oct 4 01:51:10.679438 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:10.691403 (XEN) X0: 0000000000000000 X1: 0000760ffd654000 X2: 0000800ffd96c048 Oct 4 01:51:10.691403 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:10.703504 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd9e28d0 X8: 0000000000000012 Oct 4 01:51:10.715424 (XEN) X9: 0000000000000080 X10: 00000000000009d0 X11: 0000000000000001 Oct 4 01:51:10.715424 (XEN) X12: 0000000000000001 X13: 00000000000000db X14: 00000000000000db Oct 4 01:51:10.727444 (XEN) X15: 0000fffff816cda8 X16: 0000000000000000 X17: 0000000000000000 Oct 4 01:51:10.727444 (XEN) X18: 0000000000000000 X19: 00000a000034e5b8 X20: 000000000000005b Oct 4 01:51:10.739468 (XEN) X21: 00000a0000320d00 X22: 0000000008000000 X23: 000000000000005b Oct 4 01:51:10.739468 (XEN) X24: 000000000000005b X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:10.751468 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd8ffe60 Oct 4 01:51:10.763431 (XEN) Oct 4 01:51:10.763431 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:10.763431 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:10.763431 (XEN) Oct 4 01:51:10.763431 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:10.763431 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:10.775470 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:10.775470 (XEN) Oct 4 01:51:10.775470 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:10.775470 (XEN) HPFAR_EL2: 0000000000030700 Oct 4 01:51:10.787470 (XEN) FAR_EL2: ffff80000b050100 Oct 4 01:51:10.787470 (XEN) Oct 4 01:51:10.787470 (XEN) Xen stack trace from sp=0000800ffd8ffe60: Oct 4 01:51:10.787470 (XEN) 0000800ffd8ffe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:10.799435 (XEN) 000000000000005b 0000000000000000 0000000000000000 000000000001020b Oct 4 01:51:10.799435 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.811391 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.811391 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.823409 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.835441 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.835441 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.847506 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.847506 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.859407 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.859407 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.871369 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:10.883348 (XEN) Xen call trace: Oct 4 01:51:10.883348 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:10.883348 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:10.895368 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:10.895368 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:10.895368 (XEN) Oct 4 01:51:10.895368 (XEN) *** Dumping CPU92 host state: *** Oct 4 01:51:10.907363 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:10.907363 (XEN) CPU: 92 Oct 4 01:51:10.907363 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:10.919368 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:10.919368 (XEN) SP: 0000800ffd8f7e60 Oct 4 01:51:10.919368 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:10.931370 (XEN) X0: 0000000000000000 X1: 0000760ffd652000 X2: 0000800ffd96a048 Oct 4 01:51:10.931370 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:10.943407 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd9e2d90 X8: 0000000000000012 Oct 4 01:51:10.943407 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:10.955413 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:10.967641 (XEN) X15: ffff00002e38850c X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:10.967711 (XEN) X18: ffff80001045bc58 X19: 00000a000034e5b8 X20: 000000000000005c Oct 4 01:51:10.979483 (XEN) X21: 00000a0000320d80 X22: 0000000010000000 X23: 000000000000005c Oct 4 01:51:10.979548 (XEN) X24: 000000000000005c X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:10.991583 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd8f7e60 Oct 4 01:51:10.991649 (XEN) Oct 4 01:51:10.991689 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:11.003508 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:11.003540 (XEN) Oct 4 01:51:11.003562 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:11.003617 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:11.015577 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:11.015636 (XEN) Oct 4 01:51:11.015676 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:11.015719 (XEN) HPFAR_EL2: 0000009010802f00 Oct 4 01:51:11.015762 (XEN) FAR_EL2: ffff80000b2f0100 Oct 4 01:51:11.027612 (XEN) Oct 4 01:51:11.027666 (XEN) Xen stack trace from sp=0000800ffd8f7e60: Oct 4 01:51:11.027716 (XEN) 0000800ffd8f7e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:11.039588 (XEN) 000000000000005c 0000000000000000 0000000000000000 000000000001020c Oct 4 01:51:11.039651 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.051522 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.051556 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.063617 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.063680 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.075577 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.087574 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.087637 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.099590 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.099655 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.111601 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.111664 (XEN) Xen call trace: Oct 4 01:51:11.123577 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:11.123644 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:11.135566 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:11.135630 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:11.135678 (XEN) Oct 4 01:51:11.135717 (XEN) *** Dumping CPU93 host state: *** Oct 4 01:51:11.147572 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:11.147635 (XEN) CPU: 93 Oct 4 01:51:11.147677 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:11.159583 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:11.159639 (XEN) SP: 0000800ffd8e7e60 Oct 4 01:51:11.159683 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:11.171580 (XEN) X0: 0000000000000000 X1: 0000760ffd5d6000 X2: 0000800ffd8ee048 Oct 4 01:51:11.171644 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:11.183574 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd968280 X8: 0000800ffc448000 Oct 4 01:51:11.183639 (XEN) X9: 0000000000000000 X10: ffff000002408170 X11: 0000000000000040 Oct 4 01:51:11.195603 (XEN) X12: 0000000000000000 X13: 0000000000000000 X14: 0000000000000001 Oct 4 01:51:11.195667 (XEN) X15: ffff80000a05ba10 X16: ffff80000a028000 X17: ffff80001663c000 Oct 4 01:51:11.207602 (XEN) X18: ffffffffffffffff X19: 00000a000034e5b8 X20: 000000000000005d Oct 4 01:51:11.219577 (XEN) X21: 00000a0000320e00 X22: 0000000020000000 X23: 000000000000005d Oct 4 01:51:11.219640 (XEN) X24: 000000000000005d X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:11.231580 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd8e7e60 Oct 4 01:51:11.231645 (XEN) Oct 4 01:51:11.231685 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:11.243562 (XEN) VTTBR_EL2: 000201071e5fd000 Oct 4 01:51:11.243620 (XEN) Oct 4 01:51:11.243660 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:11.243703 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:11.243746 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:11.255579 (XEN) Oct 4 01:51:11.255632 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:11.255677 (XEN) HPFAR_EL2: 0000000000030700 Oct 4 01:51:11.255720 (XEN) FAR_EL2: ffff80000b050100 Oct 4 01:51:11.267573 (XEN) Oct 4 01:51:11.267628 (XEN) Xen stack trace from sp=0000800ffd8e7e60: Oct 4 01:51:11.267676 (XEN) 0000800ffd8e7e70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:11.267725 (XEN) 000000000000005d 0000000000000000 0000000000000000 000000000001020d Oct 4 01:51:11.279644 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.291475 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.291475 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.303473 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.303473 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.315473 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.315473 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.327475 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.339472 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.339472 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.351479 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.351479 (XEN) Xen call trace: Oct 4 01:51:11.351479 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:11.363563 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:11.363631 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:11.375480 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:11.375480 (XEN) Oct 4 01:51:11.375480 (XEN) *** Dumping CPU94 host state: *** Oct 4 01:51:11.387475 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:11.387475 (XEN) CPU: 94 Oct 4 01:51:11.387475 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:11.399479 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:11.399479 (XEN) SP: 0000800ffd87fe60 Oct 4 01:51:11.399479 (XEN) CPSR: 0000000000000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:11.411479 (XEN) X0: 0000000000000000 X1: 0000760ffd5d2000 X2: 0000800ffd8ea048 Oct 4 01:51:11.411479 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:11.423477 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd968740 X8: 0000000000000012 Oct 4 01:51:11.423477 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:11.435547 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:11.435615 (XEN) X15: ffff00002cec3d0c X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:11.447585 (XEN) X18: ffff800010153c58 X19: 00000a000034e5b8 X20: 000000000000005e Oct 4 01:51:11.447650 (XEN) X21: 00000a0000320e80 X22: 0000000040000000 X23: 000000000000005e Oct 4 01:51:11.459596 (XEN) X24: 000000000000005e X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:11.471575 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd87fe60 Oct 4 01:51:11.471638 (XEN) Oct 4 01:51:11.471679 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:11.471722 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:11.483561 (XEN) Oct 4 01:51:11.483590 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:11.483614 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:11.483638 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:11.495575 (XEN) Oct 4 01:51:11.495629 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:11.495674 (XEN) HPFAR_EL2: 0000009010804700 Oct 4 01:51:11.495717 (XEN) FAR_EL2: ffff80000b470100 Oct 4 01:51:11.495759 (XEN) Oct 4 01:51:11.495797 (XEN) Xen stack trace from sp=0000800ffd87fe60: Oct 4 01:51:11.507580 (XEN) 0000800ffd87fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:11.507644 (XEN) 000000000000005e 0000000000000000 0000000000000000 000000000001020e Oct 4 01:51:11.519581 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.531567 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.531652 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.543564 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.543616 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.555578 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.555640 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.567581 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.567643 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.579580 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.591522 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.591585 (XEN) Xen call trace: Oct 4 01:51:11.591628 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:11.603585 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:11.603634 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:11.615582 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:11.615643 (XEN) Oct 4 01:51:11.615684 (XEN) *** Dumping CPU95 host state: *** Oct 4 01:51:11.615729 (XEN) ----[ Xen-4.20-unstable arm64 debug=y Not tainted ]---- Oct 4 01:51:11.627583 (XEN) CPU: 95 Oct 4 01:51:11.627639 (XEN) PC: 00000a000025d1cc domain.c#idle_loop+0x128/0x198 Oct 4 01:51:11.627690 (XEN) LR: 00000a000025d1b0 Oct 4 01:51:11.639580 (XEN) SP: 0000800ffd86fe60 Oct 4 01:51:11.639638 (XEN) CPSR: 0000000080000249 MODE:64-bit EL2h (Hypervisor, handler) Oct 4 01:51:11.639689 (XEN) X0: 0000000000000000 X1: 0000760ffd5d0000 X2: 0000800ffd8e8048 Oct 4 01:51:11.651585 (XEN) X3: ffffffffffffff9e X4: 0000000000000000 X5: 00000a000034e5a8 Oct 4 01:51:11.663574 (XEN) X6: 00000a000034e5b0 X7: 0000800ffd968c00 X8: 0000000000000012 Oct 4 01:51:11.663627 (XEN) X9: 0000000000000080 X10: 7f7f7f7f7f7f7f7f X11: 0101010101010101 Oct 4 01:51:11.675579 (XEN) X12: 0000000000000008 X13: 0000000000000020 X14: 0000000000000000 Oct 4 01:51:11.675643 (XEN) X15: fffffc0000d8fb40 X16: ffff8000092a1238 X17: 0000000000000000 Oct 4 01:51:11.687583 (XEN) X18: ffff80000cf7bc58 X19: 00000a000034e5b8 X20: 000000000000005f Oct 4 01:51:11.687647 (XEN) X21: 00000a0000320f00 X22: 0000000080000000 X23: 000000000000005f Oct 4 01:51:11.699573 (XEN) X24: 000000000000005f X25: 0000000000000000 X26: 0000000000000000 Oct 4 01:51:11.699636 (XEN) X27: 0000000000000000 X28: 0000000000000000 FP: 0000800ffd86fe60 Oct 4 01:51:11.711593 (XEN) Oct 4 01:51:11.711647 (XEN) VTCR_EL2: 00000000800d3590 Oct 4 01:51:11.711692 (XEN) VTTBR_EL2: 00010107fd864000 Oct 4 01:51:11.723574 (XEN) Oct 4 01:51:11.723628 (XEN) SCTLR_EL2: 0000000030cd183d Oct 4 01:51:11.723654 (XEN) HCR_EL2: 00000000807c663f Oct 4 01:51:11.723701 (XEN) TTBR0_EL2: 000001071e477000 Oct 4 01:51:11.723744 (XEN) Oct 4 01:51:11.723782 (XEN) ESR_EL2: 0000000007e00000 Oct 4 01:51:11.735574 (XEN) HPFAR_EL2: 0000000000030700 Oct 4 01:51:11.735633 (XEN) FAR_EL2: ffff80000b050100 Oct 4 01:51:11.735679 (XEN) Oct 4 01:51:11.735718 (XEN) Xen stack trace from sp=0000800ffd86fe60: Oct 4 01:51:11.747579 (XEN) 0000800ffd86fe70 00000a0000268ef4 00000a0000319320 00000a000034e5d8 Oct 4 01:51:11.747644 (XEN) 000000000000005f 0000000000000000 0000000000000000 000000000001020f Oct 4 01:51:11.759579 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.759643 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.771584 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.783567 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.783658 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.795574 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.795638 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.807582 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.807646 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.819584 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.819649 (XEN) 0000000000000000 0000000000000000 0000000000000000 0000000000000000 Oct 4 01:51:11.831608 (XEN) Xen call trace: Oct 4 01:51:11.831666 (XEN) [<00000a000025d1cc>] domain.c#idle_loop+0x128/0x198 (PC) Oct 4 01:51:11.843610 (XEN) [<00000a000025d1b0>] domain.c#idle_loop+0x10c/0x198 (LR) Oct 4 01:51:11.843677 (XEN) [<00000a0000268ef4>] start_secondary+0x21c/0x220 Oct 4 01:51:11.855545 (XEN) [<00000a000034e5d8>] 00000a000034e5d8 Oct 4 01:51:11.855606 (XEN) Oct 4 01:51:11.855647 Oct 4 01:51:17.651812 (XEN) 'q' pressed -> dumping domain info (now = 1403335108300) Oct 4 01:51:17.675671 (XEN) General information for domain 0: Oct 4 01:51:17.675671 (XEN) refcnt=3 dying=0 p Oct 4 01:51:17.677964 ause_count=0 Oct 4 01:51:17.687386 (XEN) nr_pages=131072 xenheap_pages=3 dirty_cpus={} max_pages=131072 Oct 4 01:51:17.687386 (XEN) handle=00000000-0000-0000-0000-000000000000 vm_assist=00000020 Oct 4 01:51:17.697458 (XEN) p2m mappings for domain 0 (vmid 1): Oct 4 01:51:17.697523 (XEN) 1G mappings: 4984 (shattered 3) Oct 4 01:51:17.697568 (XEN) 2M mappings: 1444446 (shattered 104) Oct 4 01:51:17.711464 (XEN) 4K mappings: 53265 Oct 4 01:51:17.711464 (XEN) Rangesets belonging to domain 0: Oct 4 01:51:17.711464 (XEN) Interrupts { 32, 38, 48-51 } Oct 4 01:51:17.711464 (XEN) I/O Memory { 802000000-808000000, 810000000-820000000, 838000000-844000000, 846000000-848002000, 849000000-849002000, 84a000000-84a002000, 84b000000-84b002000, 868000000-880000000, 88001f000-880058000, 881010000-883000010, 902000000-908000000, 910000000-920000000, 938000000-944000000, 946000000-948002000, 949000000-949002000, 94a000000-94a002000, 94b000000-94b002000, 968000000-980000000 } Oct 4 01:51:17.751465 (XEN) NODE affinity for domain 0: [0] Oct 4 01:51:17.751465 (XEN) VCPU information and callbacks for domain 0: Oct 4 01:51:17.763466 (XEN) UNIT0 affinities: hard={0-95} soft={0-95} Oct 4 01:51:17.763466 (XEN) VCPU0: CPU17 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:17.775440 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:17.775440 (XEN) GICH_LRs (vcpu 0) mask=0 Oct 4 01:51:17.775440 (XEN) VCPU_LR[0]=0 Oct 4 01:51:17.775440 (XEN) VCPU_LR[1]=0 Oct 4 01:51:17.775440 (XEN) VCPU_LR[2]=0 Oct 4 01:51:17.787415 (XEN) VCPU_LR[3]=0 Oct 4 01:51:17.787415 (XEN) VCPU_LR[4]=0 Oct 4 01:51:17.787415 (XEN) VCPU_LR[5]=0 Oct 4 01:51:17.787415 (XEN) VCPU_LR[6]=0 Oct 4 01:51:17.787415 (XEN) VCPU_LR[7]=0 Oct 4 01:51:17.787415 (XEN) VCPU_LR[8]=0 Oct 4 01:51:17.799469 (XEN) VCPU_LR[9]=0 Oct 4 01:51:17.799469 (XEN) VCPU_LR[10]=0 Oct 4 01:51:17.799469 (XEN) VCPU_LR[11]=0 Oct 4 01:51:17.799469 (XEN) VCPU_LR[12]=0 Oct 4 01:51:17.799469 (XEN) VCPU_LR[13]=0 Oct 4 01:51:17.811463 (XEN) VCPU_LR[14]=0 Oct 4 01:51:17.811463 (XEN) VCPU_LR[15]=0 Oct 4 01:51:17.811463 (XEN) No periodic timer Oct 4 01:51:17.811463 (XEN) UNIT1 affinities: hard={0-95} soft={0-95} Oct 4 01:51:17.811463 (XEN) VCPU1: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:17.823467 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:17.823467 (XEN) GICH_LRs (vcpu 1) mask=0 Oct 4 01:51:17.823467 (XEN) VCPU_LR[0]=0 Oct 4 01:51:17.835393 (XEN) VCPU_LR[1]=0 Oct 4 01:51:17.835393 (XEN) VCPU_LR[2]=0 Oct 4 01:51:17.835393 (XEN) VCPU_LR[3]=0 Oct 4 01:51:17.835393 (XEN) VCPU_LR[4]=0 Oct 4 01:51:17.835393 (XEN) VCPU_LR[5]=0 Oct 4 01:51:17.835393 (XEN) VCPU_LR[6]=0 Oct 4 01:51:17.847410 (XEN) VCPU_LR[7]=0 Oct 4 01:51:17.847410 (XEN) VCPU_LR[8]=0 Oct 4 01:51:17.847410 (XEN) VCPU_LR[9]=0 Oct 4 01:51:17.847410 (XEN) VCPU_LR[10]=0 Oct 4 01:51:17.847410 (XEN) VCPU_LR[11]=0 Oct 4 01:51:17.847410 (XEN) VCPU_LR[12]=0 Oct 4 01:51:17.859389 (XEN) VCPU_LR[13]=0 Oct 4 01:51:17.859389 (XEN) VCPU_LR[14]=0 Oct 4 01:51:17.859389 (XEN) VCPU_LR[15]=0 Oct 4 01:51:17.859389 (XEN) No periodic timer Oct 4 01:51:17.859389 (XEN) UNIT2 affinities: hard={0-95} soft={0-95} Oct 4 01:51:17.871387 (XEN) VCPU2: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:17.871387 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:17.871387 (XEN) GICH_LRs (vcpu 2) mask=0 Oct 4 01:51:17.883392 (XEN) VCPU_LR[0]=0 Oct 4 01:51:17.883392 (XEN) VCPU_LR[1]=0 Oct 4 01:51:17.883392 (XEN) VCPU_LR[2]=0 Oct 4 01:51:17.883392 (XEN) VCPU_LR[3]=0 Oct 4 01:51:17.895469 (XEN) VCPU_LR[4]=0 Oct 4 01:51:17.895469 (XEN) VCPU_LR[5]=0 Oct 4 01:51:17.895469 (XEN) VCPU_LR[6]=0 Oct 4 01:51:17.895469 (XEN) VCPU_LR[7]=0 Oct 4 01:51:17.895469 (XEN) VCPU_LR[8]=0 Oct 4 01:51:17.895469 (XEN) VCPU_LR[9]=0 Oct 4 01:51:17.907470 (XEN) VCPU_LR[10]=0 Oct 4 01:51:17.907470 (XEN) VCPU_LR[11]=0 Oct 4 01:51:17.907470 (XEN) VCPU_LR[12]=0 Oct 4 01:51:17.907470 (XEN) VCPU_LR[13]=0 Oct 4 01:51:17.907470 (XEN) VCPU_LR[14]=0 Oct 4 01:51:17.907470 (XEN) VCPU_LR[15]=0 Oct 4 01:51:17.919469 (XEN) No periodic timer Oct 4 01:51:17.919469 (XEN) UNIT3 affinities: hard={0-95} soft={0-95} Oct 4 01:51:17.919469 (XEN) VCPU3: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:17.931474 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:17.931474 (XEN) GICH_LRs (vcpu 3) mask=0 Oct 4 01:51:17.931474 (XEN) VCPU_LR[0]=0 Oct 4 01:51:17.931474 (XEN) VCPU_LR[1]=0 Oct 4 01:51:17.931474 (XEN) VCPU_LR[2]=0 Oct 4 01:51:17.943597 (XEN) VCPU_LR[3]=0 Oct 4 01:51:17.943618 (XEN) VCPU_LR[4]=0 Oct 4 01:51:17.943713 (XEN) VCPU_LR[5]=0 Oct 4 01:51:17.943757 (XEN) VCPU_LR[6]=0 Oct 4 01:51:17.943800 (XEN) VCPU_LR[7]=0 Oct 4 01:51:17.943813 (XEN) VCPU_LR[8]=0 Oct 4 01:51:17.955470 (XEN) VCPU_LR[9]=0 Oct 4 01:51:17.955470 (XEN) VCPU_LR[10]=0 Oct 4 01:51:17.955470 (XEN) VCPU_LR[11]=0 Oct 4 01:51:17.955470 (XEN) VCPU_LR[12]=0 Oct 4 01:51:17.955470 (XEN) VCPU_LR[13]=0 Oct 4 01:51:17.955470 (XEN) VCPU_LR[14]=0 Oct 4 01:51:17.967470 (XEN) VCPU_LR[15]=0 Oct 4 01:51:17.967470 (XEN) No periodic timer Oct 4 01:51:17.967470 (XEN) UNIT4 affinities: hard={0-95} soft={0-95} Oct 4 01:51:17.967470 (XEN) VCPU4: CPU72 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:17.979479 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:17.979479 (XEN) GICH_LRs (vcpu 4) mask=0 Oct 4 01:51:17.979479 (XEN) VCPU_LR[0]=0 Oct 4 01:51:17.991509 (XEN) VCPU_LR[1]=0 Oct 4 01:51:17.991548 (XEN) VCPU_LR[2]=0 Oct 4 01:51:17.991548 (XEN) VCPU_LR[3]=0 Oct 4 01:51:17.991548 (XEN) VCPU_LR[4]=0 Oct 4 01:51:17.991548 (XEN) VCPU_LR[5]=0 Oct 4 01:51:17.991548 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.003458 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.003458 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.003458 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.003458 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.003458 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.003458 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.015523 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.015594 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.015621 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.015621 (XEN) No periodic timer Oct 4 01:51:18.015621 (XEN) UNIT5 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.027603 (XEN) VCPU5: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.027699 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.039581 (XEN) GICH_LRs (vcpu 5) mask=0 Oct 4 01:51:18.039639 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.039681 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.039722 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.039762 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.039802 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.051574 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.051629 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.051672 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.051712 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.051753 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.051793 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.063572 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.063628 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.063671 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.063712 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.063760 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.075572 (XEN) No periodic timer Oct 4 01:51:18.075629 (XEN) UNIT6 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.075678 (XEN) VCPU6: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.087577 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.087636 (XEN) GICH_LRs (vcpu 6) mask=0 Oct 4 01:51:18.087680 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.087722 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.087762 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.099573 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.099630 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.099671 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.099712 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.099752 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.099791 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.111539 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.111595 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.111638 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.111678 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.111718 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.111759 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.123580 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.123636 (XEN) No periodic timer Oct 4 01:51:18.123679 (XEN) UNIT7 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.123726 (XEN) VCPU7: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.135608 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.135666 (XEN) GICH_LRs (vcpu 7) mask=0 Oct 4 01:51:18.147470 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.147470 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.147470 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.147470 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.147470 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.147470 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.159475 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.159475 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.159475 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.159475 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.159475 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.159475 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.171407 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.171407 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.171407 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.171407 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.171407 (XEN) No periodic timer Oct 4 01:51:18.171407 (XEN) UNIT8 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.183484 (XEN) VCPU8: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.183484 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.195476 (XEN) GICH_LRs (vcpu 8) mask=0 Oct 4 01:51:18.195476 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.195476 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.195476 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.195476 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.195476 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.207546 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.207566 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.207566 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.207566 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.207566 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.207566 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.219526 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.219589 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.219613 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.219613 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.219613 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.219613 (XEN) No periodic timer Oct 4 01:51:18.231620 (XEN) UNIT9 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.231687 (XEN) VCPU9: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.243600 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.243659 (XEN) GICH_LRs (vcpu 9) mask=0 Oct 4 01:51:18.243704 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.243746 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.243795 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.255695 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.255753 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.255796 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.255837 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.255878 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.255918 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.267471 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.267471 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.267471 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.267471 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.267471 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.279411 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.279411 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.279411 (XEN) No periodic timer Oct 4 01:51:18.279411 (XEN) UNIT10 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.279411 (XEN) VCPU10: CPU29 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.291373 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.291373 (XEN) GICH_LRs (vcpu 10) mask=0 Oct 4 01:51:18.303393 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.303393 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.303393 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.303393 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.303393 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.303393 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.303393 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.315449 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.315449 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.315449 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.315449 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.315449 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.327451 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.327451 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.327451 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.327451 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.327451 (XEN) No periodic timer Oct 4 01:51:18.327451 (XEN) UNIT11 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.339452 (XEN) VCPU11: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.339452 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.351452 (XEN) GICH_LRs (vcpu 11) mask=0 Oct 4 01:51:18.351452 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.351452 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.351452 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.351452 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.351452 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.363446 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.363446 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.363446 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.363446 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.363446 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.363446 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.375449 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.375449 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.375449 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.375449 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.375449 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.387472 (XEN) No periodic timer Oct 4 01:51:18.387472 (XEN) UNIT12 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.387472 (XEN) VCPU12: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.399478 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.399478 (XEN) GICH_LRs (vcpu 12) mask=0 Oct 4 01:51:18.399478 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.399478 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.411478 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.411478 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.411478 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.411478 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.411478 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.411478 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.423530 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.423566 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.423566 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.423566 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.423566 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.423566 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.435521 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.435589 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.435609 (XEN) No periodic timer Oct 4 01:51:18.435609 (XEN) UNIT13 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.435609 (XEN) VCPU13: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.447603 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.447666 (XEN) GICH_LRs (vcpu 13) mask=0 Oct 4 01:51:18.459570 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.459627 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.459669 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.459710 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.459751 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.459791 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.471590 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.471646 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.471689 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.471731 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.471771 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.471812 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.483579 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.483635 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.483679 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.483720 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.483761 (XEN) No periodic timer Oct 4 01:51:18.483810 (XEN) UNIT14 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.495579 (XEN) VCPU14: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.495643 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.507583 (XEN) GICH_LRs (vcpu 14) mask=0 Oct 4 01:51:18.507643 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.507686 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.507728 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.507769 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.507810 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.519571 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.519627 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.519670 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.519711 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.519750 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.531580 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.531636 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.531679 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.531719 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.531759 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.543589 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.543646 (XEN) No periodic timer Oct 4 01:51:18.543690 (XEN) UNIT15 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.543736 (XEN) VCPU15: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.555627 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.555686 (XEN) GICH_LRs (vcpu 15) mask=0 Oct 4 01:51:18.555731 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.555772 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.567496 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.567553 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.567596 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.567637 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.567676 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.567716 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.579573 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.579629 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.579671 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.579711 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.579752 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.579792 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.591575 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.591631 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.591674 (XEN) No periodic timer Oct 4 01:51:18.591716 (XEN) UNIT16 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.603572 (XEN) VCPU16: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.603636 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.603681 (XEN) GICH_LRs (vcpu 16) mask=0 Oct 4 01:51:18.615582 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.615638 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.615681 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.615721 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.615761 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.615802 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.627577 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.627633 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.627695 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.627739 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.627781 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.627821 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.639580 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.639637 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.639682 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.639724 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.639765 (XEN) No periodic timer Oct 4 01:51:18.639808 (XEN) UNIT17 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.651574 (XEN) VCPU17: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.651641 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.663582 (XEN) GICH_LRs (vcpu 17) mask=0 Oct 4 01:51:18.663642 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.663686 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.663730 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.675570 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.675628 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.675672 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.675714 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.675755 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.675796 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.687538 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.687598 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.687642 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.687683 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.687725 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.687766 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.699611 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.699668 (XEN) No periodic timer Oct 4 01:51:18.699713 (XEN) UNIT18 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.699761 (XEN) VCPU18: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.711464 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.711464 (XEN) GICH_LRs (vcpu 18) mask=0 Oct 4 01:51:18.711464 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.711464 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.723471 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.723471 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.723471 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.723471 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.723471 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.723471 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.735478 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.735478 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.735478 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.735478 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.735478 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.735478 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.747473 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.747473 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.747473 (XEN) No periodic timer Oct 4 01:51:18.747473 (XEN) UNIT19 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.759476 (XEN) VCPU19: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.759476 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.759476 (XEN) GICH_LRs (vcpu 19) mask=0 Oct 4 01:51:18.771463 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.771463 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.771463 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.771463 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.771463 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.783470 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.783470 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.783470 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.783470 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.783470 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.783470 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.795472 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.795472 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.795472 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.795472 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.795472 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.795472 (XEN) No periodic timer Oct 4 01:51:18.807478 (XEN) UNIT20 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.807478 (XEN) VCPU20: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.819475 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.819475 (XEN) GICH_LRs (vcpu 20) mask=0 Oct 4 01:51:18.819475 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.819475 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.819475 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.831470 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.831470 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.831470 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.831470 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.831470 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.831470 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.843479 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.843479 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.843479 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.843479 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.843479 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.843479 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.855473 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.855473 (XEN) No periodic timer Oct 4 01:51:18.855473 (XEN) UNIT21 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.855473 (XEN) VCPU21: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.867479 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.867479 (XEN) GICH_LRs (vcpu 21) mask=0 Oct 4 01:51:18.867479 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.879472 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.879472 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.879472 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.879472 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.879472 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.879472 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.891476 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.891476 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.891476 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.891476 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.891476 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.891476 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.903464 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.903464 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.903464 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.903464 (XEN) No periodic timer Oct 4 01:51:18.903464 (XEN) UNIT22 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.915462 (XEN) VCPU22: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.915462 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.927472 (XEN) GICH_LRs (vcpu 22) mask=0 Oct 4 01:51:18.927472 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.927472 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.927472 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.927472 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.927472 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.939479 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.939479 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.939479 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.939479 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.939479 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.939479 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.951475 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.951475 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.951475 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.951475 (XEN) VCPU_LR[14]=0 Oct 4 01:51:18.951475 (XEN) VCPU_LR[15]=0 Oct 4 01:51:18.951475 (XEN) No periodic timer Oct 4 01:51:18.963467 (XEN) UNIT23 affinities: hard={0-95} soft={0-95} Oct 4 01:51:18.963467 (XEN) VCPU23: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:18.975483 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:18.975483 (XEN) GICH_LRs (vcpu 23) mask=0 Oct 4 01:51:18.975483 (XEN) VCPU_LR[0]=0 Oct 4 01:51:18.975483 (XEN) VCPU_LR[1]=0 Oct 4 01:51:18.975483 (XEN) VCPU_LR[2]=0 Oct 4 01:51:18.987484 (XEN) VCPU_LR[3]=0 Oct 4 01:51:18.987484 (XEN) VCPU_LR[4]=0 Oct 4 01:51:18.987484 (XEN) VCPU_LR[5]=0 Oct 4 01:51:18.987484 (XEN) VCPU_LR[6]=0 Oct 4 01:51:18.987484 (XEN) VCPU_LR[7]=0 Oct 4 01:51:18.987484 (XEN) VCPU_LR[8]=0 Oct 4 01:51:18.999482 (XEN) VCPU_LR[9]=0 Oct 4 01:51:18.999482 (XEN) VCPU_LR[10]=0 Oct 4 01:51:18.999482 (XEN) VCPU_LR[11]=0 Oct 4 01:51:18.999482 (XEN) VCPU_LR[12]=0 Oct 4 01:51:18.999482 (XEN) VCPU_LR[13]=0 Oct 4 01:51:18.999482 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.011482 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.011482 (XEN) No periodic timer Oct 4 01:51:19.011482 (XEN) UNIT24 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.011482 (XEN) VCPU24: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.023467 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.023467 (XEN) GICH_LRs (vcpu 24) mask=0 Oct 4 01:51:19.035470 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.035470 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.035470 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.035470 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.035470 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.035470 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.047479 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.047479 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.047479 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.047479 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.047479 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.047479 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.059474 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.059474 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.059474 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.059474 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.059474 (XEN) No periodic timer Oct 4 01:51:19.059474 (XEN) UNIT25 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.071479 (XEN) VCPU25: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.071479 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.083472 (XEN) GICH_LRs (vcpu 25) mask=0 Oct 4 01:51:19.083472 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.083472 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.083472 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.083472 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.083472 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.095475 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.095475 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.095475 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.095475 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.095475 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.095475 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.107470 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.107470 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.107470 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.107470 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.107470 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.119471 (XEN) No periodic timer Oct 4 01:51:19.119471 (XEN) UNIT26 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.119471 (XEN) VCPU26: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.131473 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.131473 (XEN) GICH_LRs (vcpu 26) mask=0 Oct 4 01:51:19.131473 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.131473 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.131473 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.143473 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.143473 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.143473 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.143473 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.143473 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.143473 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.155462 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.155462 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.155462 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.155462 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.155462 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.167471 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.167471 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.167471 (XEN) No periodic timer Oct 4 01:51:19.167471 (XEN) UNIT27 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.179469 (XEN) VCPU27: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.179469 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.179469 (XEN) GICH_LRs (vcpu 27) mask=0 Oct 4 01:51:19.191473 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.191473 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.191473 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.191473 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.191473 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.191473 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.203567 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.203628 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.203670 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.203712 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.203751 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.203791 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.215470 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.215470 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.215470 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.215470 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.215470 (XEN) No periodic timer Oct 4 01:51:19.215470 (XEN) UNIT28 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.227473 (XEN) VCPU28: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.227473 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.239472 (XEN) GICH_LRs (vcpu 28) mask=0 Oct 4 01:51:19.239472 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.239472 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.239472 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.239472 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.251472 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.251472 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.251472 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.251472 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.251472 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.251472 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.263467 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.263467 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.263467 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.263467 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.263467 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.263467 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.275473 (XEN) No periodic timer Oct 4 01:51:19.275473 (XEN) UNIT29 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.275473 (XEN) VCPU29: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.287460 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.287460 (XEN) GICH_LRs (vcpu 29) mask=0 Oct 4 01:51:19.287460 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.287460 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.299470 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.299470 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.299470 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.299470 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.299470 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.299470 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.311482 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.311482 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.311482 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.311482 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.311482 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.311482 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.323524 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.323548 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.323548 (XEN) No periodic timer Oct 4 01:51:19.323548 (XEN) UNIT30 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.335462 (XEN) VCPU30: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.335638 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.335677 (XEN) GICH_LRs (vcpu 30) mask=0 Oct 4 01:51:19.347566 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.347566 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.347566 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.347566 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.347566 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.347566 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.359543 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.359543 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.359639 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.359720 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.359744 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.359744 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.371471 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.371630 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.371662 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.371662 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.371662 (XEN) No periodic timer Oct 4 01:51:19.371662 (XEN) UNIT31 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.383597 (XEN) VCPU31: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.383666 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.395619 (XEN) GICH_LRs (vcpu 31) mask=0 Oct 4 01:51:19.395678 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.395721 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.395762 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.395803 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.407565 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.407623 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.407666 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.407707 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.407749 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.419584 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.419640 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.419683 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.419725 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.419786 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.419830 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.431576 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.431634 (XEN) No periodic timer Oct 4 01:51:19.431678 (XEN) UNIT32 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.431726 (XEN) VCPU32: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.443604 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.443664 (XEN) GICH_LRs (vcpu 32) mask=0 Oct 4 01:51:19.443709 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.443749 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.455554 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.455610 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.455653 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.455695 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.455735 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.455775 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.467640 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.467696 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.467739 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.467780 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.467868 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.467911 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.479534 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.479589 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.479633 (XEN) No periodic timer Oct 4 01:51:19.479676 (XEN) UNIT33 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.491648 (XEN) VCPU33: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.491715 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.491760 (XEN) GICH_LRs (vcpu 33) mask=0 Oct 4 01:51:19.503479 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.503479 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.503479 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.503479 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.503479 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.503479 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.515473 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.515473 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.515473 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.515473 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.515473 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.515473 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.527475 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.527475 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.527475 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.527475 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.527475 (XEN) No periodic timer Oct 4 01:51:19.539463 (XEN) UNIT34 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.539463 (XEN) VCPU34: CPU73 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.551483 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.551483 (XEN) GICH_LRs (vcpu 34) mask=0 Oct 4 01:51:19.551483 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.551483 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.551483 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.563480 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.563589 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.563589 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.563589 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.563589 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.563589 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.575549 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.575612 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.575630 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.575630 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.575630 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.575630 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.587594 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.587655 (XEN) No periodic timer Oct 4 01:51:19.587698 (XEN) UNIT35 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.587746 (XEN) VCPU35: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.599588 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.599647 (XEN) GICH_LRs (vcpu 35) mask=0 Oct 4 01:51:19.599691 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.611580 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.611637 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.611681 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.611723 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.611764 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.611805 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.623584 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.623661 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.623708 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.623750 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.623792 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.623839 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.635572 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.635628 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.635672 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.635713 (XEN) No periodic timer Oct 4 01:51:19.635755 (XEN) UNIT36 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.647577 (XEN) VCPU36: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.647642 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.647688 (XEN) GICH_LRs (vcpu 36) mask=0 Oct 4 01:51:19.659575 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.659631 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.659674 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.659716 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.659756 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.671576 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.671632 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.671675 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.671716 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.671757 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.671797 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.683578 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.683635 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.683678 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.683719 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.683760 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.695570 (XEN) No periodic timer Oct 4 01:51:19.695629 (XEN) UNIT37 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.695677 (XEN) VCPU37: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.707584 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.707643 (XEN) GICH_LRs (vcpu 37) mask=0 Oct 4 01:51:19.707687 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.707729 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.707769 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.719585 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.719641 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.719684 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.719724 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.719764 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.719805 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.731589 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.731645 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.731688 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.731729 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.731770 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.731810 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.743577 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.743633 (XEN) No periodic timer Oct 4 01:51:19.743676 (XEN) UNIT38 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.743722 (XEN) VCPU38: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.755587 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.755646 (XEN) GICH_LRs (vcpu 38) mask=0 Oct 4 01:51:19.755691 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.767573 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.767629 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.767672 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.767713 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.767754 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.767794 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.779574 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.779630 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.779673 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.779714 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.779755 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.779795 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.791566 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.791622 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.791665 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.791705 (XEN) No periodic timer Oct 4 01:51:19.791746 (XEN) UNIT39 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.803582 (XEN) VCPU39: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.803646 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.815575 (XEN) GICH_LRs (vcpu 39) mask=0 Oct 4 01:51:19.815634 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.815676 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.815717 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.815775 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.815820 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.827552 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.827609 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.827652 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.827693 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.827733 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.827774 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.839579 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.839635 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.839678 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.839720 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.839760 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.851477 (XEN) No periodic timer Oct 4 01:51:19.851477 (XEN) UNIT40 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.851477 (XEN) VCPU40: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.863466 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.863466 (XEN) GICH_LRs (vcpu 40) mask=0 Oct 4 01:51:19.863466 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.863466 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.863466 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.875480 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.875480 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.875480 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.875480 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.875480 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.875480 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.887474 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.887474 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.887474 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.887474 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.887474 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.887474 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.899477 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.899477 (XEN) No periodic timer Oct 4 01:51:19.899477 (XEN) UNIT41 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.899477 (XEN) VCPU41: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.911469 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.911469 (XEN) GICH_LRs (vcpu 41) mask=0 Oct 4 01:51:19.911469 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.923459 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.923459 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.923459 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.923459 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.923459 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.935473 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.935473 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.935473 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.935473 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.935473 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.935473 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.947540 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.947540 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.947540 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.947540 (XEN) VCPU_LR[15]=0 Oct 4 01:51:19.947540 (XEN) No periodic timer Oct 4 01:51:19.947540 (XEN) UNIT42 affinities: hard={0-95} soft={0-95} Oct 4 01:51:19.959635 (XEN) VCPU42: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:19.959653 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:19.971609 (XEN) GICH_LRs (vcpu 42) mask=0 Oct 4 01:51:19.971681 (XEN) VCPU_LR[0]=0 Oct 4 01:51:19.971722 (XEN) VCPU_LR[1]=0 Oct 4 01:51:19.971728 (XEN) VCPU_LR[2]=0 Oct 4 01:51:19.971728 (XEN) VCPU_LR[3]=0 Oct 4 01:51:19.983604 (XEN) VCPU_LR[4]=0 Oct 4 01:51:19.983628 (XEN) VCPU_LR[5]=0 Oct 4 01:51:19.983628 (XEN) VCPU_LR[6]=0 Oct 4 01:51:19.983628 (XEN) VCPU_LR[7]=0 Oct 4 01:51:19.983628 (XEN) VCPU_LR[8]=0 Oct 4 01:51:19.983628 (XEN) VCPU_LR[9]=0 Oct 4 01:51:19.995569 (XEN) VCPU_LR[10]=0 Oct 4 01:51:19.995622 (XEN) VCPU_LR[11]=0 Oct 4 01:51:19.995663 (XEN) VCPU_LR[12]=0 Oct 4 01:51:19.995732 (XEN) VCPU_LR[13]=0 Oct 4 01:51:19.995758 (XEN) VCPU_LR[14]=0 Oct 4 01:51:19.995758 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.007579 (XEN) No periodic timer Oct 4 01:51:20.007637 (XEN) UNIT43 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.007675 (XEN) VCPU43: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.019468 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.019468 (XEN) GICH_LRs (vcpu 43) mask=0 Oct 4 01:51:20.019468 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.019468 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.019468 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.031487 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.031487 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.031487 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.031487 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.031487 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.031487 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.043465 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.043465 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.043465 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.043465 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.043465 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.055489 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.055489 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.055489 (XEN) No periodic timer Oct 4 01:51:20.055489 (XEN) UNIT44 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.067488 (XEN) VCPU44: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.067488 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.067488 (XEN) GICH_LRs (vcpu 44) mask=0 Oct 4 01:51:20.079484 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.079484 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.079484 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.079484 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.079484 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.079484 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.091478 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.091478 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.091478 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.091478 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.091478 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.091478 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.103460 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.103460 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.103460 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.103460 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.103460 (XEN) No periodic timer Oct 4 01:51:20.103460 (XEN) UNIT45 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.115464 (XEN) VCPU45: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.115464 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.127470 (XEN) GICH_LRs (vcpu 45) mask=0 Oct 4 01:51:20.127470 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.127470 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.127470 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.127470 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.139472 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.139472 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.139472 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.139472 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.139472 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.139472 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.151477 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.151477 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.151477 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.151477 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.151477 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.151477 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.163471 (XEN) No periodic timer Oct 4 01:51:20.163471 (XEN) UNIT46 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.163471 (XEN) VCPU46: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.175467 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.175467 (XEN) GICH_LRs (vcpu 46) mask=0 Oct 4 01:51:20.175467 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.187475 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.187633 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.187704 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.187734 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.187734 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.187734 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.199474 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.199474 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.199474 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.199474 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.199474 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.199474 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.211476 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.211476 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.211476 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.211476 (XEN) No periodic timer Oct 4 01:51:20.211476 (XEN) UNIT47 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.223434 (XEN) VCPU47: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.223503 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.223548 (XEN) GICH_LRs (vcpu 47) mask=0 Oct 4 01:51:20.235478 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.235478 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.235478 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.235478 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.235478 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.235478 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.247474 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.247474 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.247474 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.247474 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.247474 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.247474 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.259475 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.259475 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.259475 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.259475 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.259475 (XEN) No periodic timer Oct 4 01:51:20.271478 (XEN) UNIT48 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.271478 (XEN) VCPU48: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.271478 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.283483 (XEN) GICH_LRs (vcpu 48) mask=0 Oct 4 01:51:20.283483 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.283483 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.283483 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.283483 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.295472 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.295472 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.295472 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.295472 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.295472 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.307473 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.307473 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.307473 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.307473 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.307473 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.307473 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.319476 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.319476 (XEN) No periodic timer Oct 4 01:51:20.319476 (XEN) UNIT49 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.319476 (XEN) VCPU49: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.331478 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.331478 (XEN) GICH_LRs (vcpu 49) mask=0 Oct 4 01:51:20.331478 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.343468 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.343468 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.343468 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.343468 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.343468 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.343468 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.355473 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.355473 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.355473 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.355473 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.355473 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.355473 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.367477 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.367477 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.367477 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.367477 (XEN) No periodic timer Oct 4 01:51:20.367477 (XEN) UNIT50 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.379485 (XEN) VCPU50: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.379485 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.379485 (XEN) GICH_LRs (vcpu 50) mask=0 Oct 4 01:51:20.391480 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.391480 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.391480 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.391480 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.391480 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.403482 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.403482 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.403482 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.403482 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.403482 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.403482 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.415471 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.415471 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.415471 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.415471 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.415471 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.415471 (XEN) No periodic timer Oct 4 01:51:20.427472 (XEN) UNIT51 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.427472 (XEN) VCPU51: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.439474 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.439474 (XEN) GICH_LRs (vcpu 51) mask=0 Oct 4 01:51:20.439474 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.439474 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.439474 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.451477 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.451477 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.451477 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.451477 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.451477 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.451477 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.463460 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.463460 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.463460 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.463460 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.463460 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.463460 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.475473 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.475473 (XEN) No periodic timer Oct 4 01:51:20.475473 (XEN) UNIT52 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.475473 (XEN) VCPU52: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.487480 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.487480 (XEN) GICH_LRs (vcpu 52) mask=0 Oct 4 01:51:20.487480 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.499472 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.499472 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.499472 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.499472 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.499472 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.499472 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.511474 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.511474 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.511474 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.511474 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.511474 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.511474 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.523474 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.523474 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.523474 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.523474 (XEN) No periodic timer Oct 4 01:51:20.523474 (XEN) UNIT53 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.535472 (XEN) VCPU53: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.535472 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.535472 (XEN) GICH_LRs (vcpu 53) mask=0 Oct 4 01:51:20.547458 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.547458 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.547458 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.547458 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.547458 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.559464 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.559464 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.559464 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.559464 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.559464 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.571481 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.571481 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.571481 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.571481 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.571481 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.571481 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.583481 (XEN) No periodic timer Oct 4 01:51:20.583481 (XEN) UNIT54 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.583481 (XEN) VCPU54: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.595458 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.595458 (XEN) GICH_LRs (vcpu 54) mask=0 Oct 4 01:51:20.595458 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.595458 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.595458 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.607433 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.607433 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.607433 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.607433 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.607433 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.607433 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.619475 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.619475 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.619475 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.619475 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.619475 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.631479 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.631479 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.631479 (XEN) No periodic timer Oct 4 01:51:20.631479 (XEN) UNIT55 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.631479 (XEN) VCPU55: CPU36 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.643471 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.643471 (XEN) GICH_LRs (vcpu 55) mask=0 Oct 4 01:51:20.643471 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.655472 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.655472 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.655472 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.655472 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.655472 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.655472 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.667496 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.667496 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.667496 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.667496 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.667496 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.667496 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.679465 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.679465 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.679465 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.679465 (XEN) No periodic timer Oct 4 01:51:20.679465 (XEN) UNIT56 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.691471 (XEN) VCPU56: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.691471 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.703479 (XEN) GICH_LRs (vcpu 56) mask=0 Oct 4 01:51:20.703479 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.703479 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.703479 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.703479 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.715471 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.715471 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.715471 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.715471 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.715471 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.715471 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.727492 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.727492 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.727492 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.727492 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.727492 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.727492 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.739485 (XEN) No periodic timer Oct 4 01:51:20.739485 (XEN) UNIT57 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.739485 (XEN) VCPU57: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.751478 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.751478 (XEN) GICH_LRs (vcpu 57) mask=0 Oct 4 01:51:20.751478 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.751478 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.763475 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.763475 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.763475 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.763475 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.763475 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.763475 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.775481 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.775481 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.775481 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.775481 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.775481 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.775481 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.787448 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.787448 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.787448 (XEN) No periodic timer Oct 4 01:51:20.787448 (XEN) UNIT58 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.787448 (XEN) VCPU58: CPU79 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.799477 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.799477 (XEN) GICH_LRs (vcpu 58) mask=0 Oct 4 01:51:20.799477 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.811471 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.811471 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.811471 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.811471 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.811471 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.823397 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.823397 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.823397 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.823397 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.823397 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.823397 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.835459 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.835459 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.835459 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.835459 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.835459 (XEN) No periodic timer Oct 4 01:51:20.847443 (XEN) UNIT59 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.847443 (XEN) VCPU59: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.847443 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.859473 (XEN) GICH_LRs (vcpu 59) mask=0 Oct 4 01:51:20.859473 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.859473 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.859473 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.859473 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.871483 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.871483 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.871483 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.871483 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.871483 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.871483 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.883470 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.883470 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.883470 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.883470 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.883470 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.883470 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.895478 (XEN) No periodic timer Oct 4 01:51:20.895478 (XEN) UNIT60 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.895478 (XEN) VCPU60: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.907439 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.907439 (XEN) GICH_LRs (vcpu 60) mask=0 Oct 4 01:51:20.907439 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.907439 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.919472 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.919472 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.919472 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.919472 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.919472 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.919472 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.931470 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.931470 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.931470 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.931470 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.931470 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.943468 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.943468 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.943468 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.943468 (XEN) No periodic timer Oct 4 01:51:20.943468 (XEN) UNIT61 affinities: hard={0-95} soft={0-95} Oct 4 01:51:20.955621 (XEN) VCPU61: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:20.955672 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:20.955672 (XEN) GICH_LRs (vcpu 61) mask=0 Oct 4 01:51:20.967498 (XEN) VCPU_LR[0]=0 Oct 4 01:51:20.967498 (XEN) VCPU_LR[1]=0 Oct 4 01:51:20.967498 (XEN) VCPU_LR[2]=0 Oct 4 01:51:20.967498 (XEN) VCPU_LR[3]=0 Oct 4 01:51:20.967498 (XEN) VCPU_LR[4]=0 Oct 4 01:51:20.967498 (XEN) VCPU_LR[5]=0 Oct 4 01:51:20.979489 (XEN) VCPU_LR[6]=0 Oct 4 01:51:20.979489 (XEN) VCPU_LR[7]=0 Oct 4 01:51:20.979489 (XEN) VCPU_LR[8]=0 Oct 4 01:51:20.979489 (XEN) VCPU_LR[9]=0 Oct 4 01:51:20.979489 (XEN) VCPU_LR[10]=0 Oct 4 01:51:20.979489 (XEN) VCPU_LR[11]=0 Oct 4 01:51:20.991490 (XEN) VCPU_LR[12]=0 Oct 4 01:51:20.991490 (XEN) VCPU_LR[13]=0 Oct 4 01:51:20.991490 (XEN) VCPU_LR[14]=0 Oct 4 01:51:20.991490 (XEN) VCPU_LR[15]=0 Oct 4 01:51:20.991490 (XEN) No periodic timer Oct 4 01:51:21.003488 (XEN) UNIT62 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.003488 (XEN) VCPU62: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.003488 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.015484 (XEN) GICH_LRs (vcpu 62) mask=0 Oct 4 01:51:21.015484 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.015484 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.015484 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.015484 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.027487 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.027487 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.027487 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.027487 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.027487 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.027487 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.039493 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.039493 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.039493 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.039493 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.039493 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.039493 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.051490 (XEN) No periodic timer Oct 4 01:51:21.051490 (XEN) UNIT63 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.051490 (XEN) VCPU63: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.063476 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.063476 (XEN) GICH_LRs (vcpu 63) mask=0 Oct 4 01:51:21.063476 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.075495 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.075495 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.075495 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.075495 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.075495 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.075495 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.087467 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.087467 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.087467 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.087467 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.087467 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.087467 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.099485 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.099485 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.099485 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.099485 (XEN) No periodic timer Oct 4 01:51:21.099485 (XEN) UNIT64 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.111486 (XEN) VCPU64: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.111486 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.111486 (XEN) GICH_LRs (vcpu 64) mask=0 Oct 4 01:51:21.123484 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.123484 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.123484 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.123484 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.123484 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.135482 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.135482 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.135482 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.135482 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.135482 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.135482 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.147480 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.147480 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.147480 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.147480 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.147480 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.147480 (XEN) No periodic timer Oct 4 01:51:21.159484 (XEN) UNIT65 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.159484 (XEN) VCPU65: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.159484 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.171492 (XEN) GICH_LRs (vcpu 65) mask=0 Oct 4 01:51:21.171492 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.171492 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.171492 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.171492 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.183477 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.183477 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.183477 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.183477 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.183477 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.195491 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.195491 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.195491 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.195491 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.195491 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.195491 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.207468 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.207468 (XEN) No periodic timer Oct 4 01:51:21.207468 (XEN) UNIT66 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.207468 (XEN) VCPU66: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.219484 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.219484 (XEN) GICH_LRs (vcpu 66) mask=0 Oct 4 01:51:21.219484 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.231488 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.231488 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.231488 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.231488 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.231488 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.231488 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.243486 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.243486 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.243486 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.243486 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.243486 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.243486 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.255491 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.255491 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.255491 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.255491 (XEN) No periodic timer Oct 4 01:51:21.255491 (XEN) UNIT67 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.267485 (XEN) VCPU67: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.267485 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.267485 (XEN) GICH_LRs (vcpu 67) mask=0 Oct 4 01:51:21.279493 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.279493 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.279493 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.279493 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.279493 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.291493 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.291493 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.291493 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.291493 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.291493 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.291493 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.303485 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.303485 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.303485 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.303485 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.303485 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.303485 (XEN) No periodic timer Oct 4 01:51:21.315470 (XEN) UNIT68 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.315470 (XEN) VCPU68: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.327496 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.327496 (XEN) GICH_LRs (vcpu 68) mask=0 Oct 4 01:51:21.327496 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.327496 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.339486 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.339486 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.339486 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.339486 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.339486 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.339486 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.351489 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.351489 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.351489 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.351489 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.351489 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.351489 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.363486 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.363486 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.363486 (XEN) No periodic timer Oct 4 01:51:21.363486 (XEN) UNIT69 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.363486 (XEN) VCPU69: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.375487 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.375487 (XEN) GICH_LRs (vcpu 69) mask=0 Oct 4 01:51:21.375487 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.387485 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.387485 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.387485 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.387485 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.387485 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.387485 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.399488 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.399488 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.399488 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.399488 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.399488 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.399488 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.411486 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.411486 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.411486 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.411486 (XEN) No periodic timer Oct 4 01:51:21.411486 (XEN) UNIT70 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.423484 (XEN) VCPU70: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.423484 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.435486 (XEN) GICH_LRs (vcpu 70) mask=0 Oct 4 01:51:21.435486 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.435486 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.435486 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.435486 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.435486 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.447475 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.447475 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.447475 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.447475 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.447475 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.459540 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.459540 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.459540 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.459540 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.459540 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.459540 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.471616 (XEN) No periodic timer Oct 4 01:51:21.471672 (XEN) UNIT71 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.471718 (XEN) VCPU71: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.483555 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.483632 (XEN) GICH_LRs (vcpu 71) mask=0 Oct 4 01:51:21.483645 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.483645 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.495479 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.495479 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.495479 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.495479 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.495479 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.495479 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.507486 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.507486 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.507486 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.507486 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.507486 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.507486 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.519485 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.519485 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.519485 (XEN) No periodic timer Oct 4 01:51:21.519485 (XEN) UNIT72 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.519485 (XEN) VCPU72: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.531483 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.531483 (XEN) GICH_LRs (vcpu 72) mask=0 Oct 4 01:51:21.531483 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.543490 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.543490 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.543490 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.543490 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.543490 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.543490 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.555491 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.555491 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.555491 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.555491 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.555491 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.567478 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.567478 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.567478 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.567478 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.567478 (XEN) No periodic timer Oct 4 01:51:21.579485 (XEN) UNIT73 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.579485 (XEN) VCPU73: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.579485 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.591491 (XEN) GICH_LRs (vcpu 73) mask=0 Oct 4 01:51:21.591491 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.591491 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.591491 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.591491 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.603486 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.603486 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.603486 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.603486 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.603486 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.603486 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.615472 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.615472 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.615472 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.615472 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.615472 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.615472 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.627483 (XEN) No periodic timer Oct 4 01:51:21.627483 (XEN) UNIT74 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.627483 (XEN) VCPU74: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.639487 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.639487 (XEN) GICH_LRs (vcpu 74) mask=0 Oct 4 01:51:21.639487 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.639487 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.651485 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.651485 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.651485 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.651485 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.651485 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.651485 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.663480 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.663480 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.663480 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.663480 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.663480 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.663480 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.675487 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.675487 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.675487 (XEN) No periodic timer Oct 4 01:51:21.675487 (XEN) UNIT75 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.675487 (XEN) VCPU75: CPU50 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.687476 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.687476 (XEN) GICH_LRs (vcpu 75) mask=0 Oct 4 01:51:21.699488 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.699488 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.699488 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.699488 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.699488 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.711489 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.711489 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.711489 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.711489 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.711489 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.711489 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.723556 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.723619 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.723662 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.723702 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.723742 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.723782 (XEN) No periodic timer Oct 4 01:51:21.735603 (XEN) UNIT76 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.735666 (XEN) VCPU76: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.735718 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.747597 (XEN) GICH_LRs (vcpu 76) mask=0 Oct 4 01:51:21.747660 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.747684 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.747724 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.747765 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.759589 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.759645 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.759687 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.759729 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.759770 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.759810 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.771594 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.771650 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.771693 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.771734 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.771776 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.783585 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.783644 (XEN) No periodic timer Oct 4 01:51:21.783688 (XEN) UNIT77 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.783735 (XEN) VCPU77: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.795604 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.795663 (XEN) GICH_LRs (vcpu 77) mask=0 Oct 4 01:51:21.795707 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.795750 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.807594 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.807650 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.807708 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.807752 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.807793 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.807835 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.819582 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.819639 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.819682 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.819724 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.819765 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.831589 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.831645 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.831688 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.831730 (XEN) No periodic timer Oct 4 01:51:21.831771 (XEN) UNIT78 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.843592 (XEN) VCPU78: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.843657 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.843702 (XEN) GICH_LRs (vcpu 78) mask=0 Oct 4 01:51:21.855533 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.855533 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.855533 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.855533 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.855533 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.867603 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.867664 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.867709 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.867732 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.867754 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.867776 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.879587 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.879644 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.879687 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.879729 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.879770 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.879810 (XEN) No periodic timer Oct 4 01:51:21.891599 (XEN) UNIT79 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.891661 (XEN) VCPU79: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.891713 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.903601 (XEN) GICH_LRs (vcpu 79) mask=0 Oct 4 01:51:21.903660 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.903703 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.903745 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.915582 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.915640 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.915684 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.915725 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.915767 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.915807 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.927595 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.927653 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.927696 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.927737 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.927759 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.927781 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.939592 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.939649 (XEN) No periodic timer Oct 4 01:51:21.939692 (XEN) UNIT80 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.939740 (XEN) VCPU80: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.951584 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:21.951644 (XEN) GICH_LRs (vcpu 80) mask=0 Oct 4 01:51:21.951690 (XEN) VCPU_LR[0]=0 Oct 4 01:51:21.963603 (XEN) VCPU_LR[1]=0 Oct 4 01:51:21.963661 (XEN) VCPU_LR[2]=0 Oct 4 01:51:21.963704 (XEN) VCPU_LR[3]=0 Oct 4 01:51:21.963746 (XEN) VCPU_LR[4]=0 Oct 4 01:51:21.963788 (XEN) VCPU_LR[5]=0 Oct 4 01:51:21.963828 (XEN) VCPU_LR[6]=0 Oct 4 01:51:21.975598 (XEN) VCPU_LR[7]=0 Oct 4 01:51:21.975654 (XEN) VCPU_LR[8]=0 Oct 4 01:51:21.975697 (XEN) VCPU_LR[9]=0 Oct 4 01:51:21.975738 (XEN) VCPU_LR[10]=0 Oct 4 01:51:21.975779 (XEN) VCPU_LR[11]=0 Oct 4 01:51:21.975821 (XEN) VCPU_LR[12]=0 Oct 4 01:51:21.987603 (XEN) VCPU_LR[13]=0 Oct 4 01:51:21.987660 (XEN) VCPU_LR[14]=0 Oct 4 01:51:21.987702 (XEN) VCPU_LR[15]=0 Oct 4 01:51:21.987753 (XEN) No periodic timer Oct 4 01:51:21.987777 (XEN) UNIT81 affinities: hard={0-95} soft={0-95} Oct 4 01:51:21.999597 (XEN) VCPU81: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:21.999662 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.011594 (XEN) GICH_LRs (vcpu 81) mask=0 Oct 4 01:51:22.011675 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.011722 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.011764 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.011805 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.011845 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.023588 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.023645 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.023687 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.023729 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.023769 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.023810 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.035592 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.035648 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.035691 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.035733 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.035773 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.035814 (XEN) No periodic timer Oct 4 01:51:22.047564 (XEN) UNIT82 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.047626 (XEN) VCPU82: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.059479 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.059529 (XEN) GICH_LRs (vcpu 82) mask=0 Oct 4 01:51:22.059574 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.059615 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.059656 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.071485 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.071538 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.071580 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.071624 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.071666 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.071707 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.083470 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.083518 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.083559 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.083600 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.083640 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.095479 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.095528 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.095569 (XEN) No periodic timer Oct 4 01:51:22.095610 (XEN) UNIT83 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.095657 (XEN) VCPU83: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.107469 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.107521 (XEN) GICH_LRs (vcpu 83) mask=0 Oct 4 01:51:22.107565 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.119479 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.119527 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.119569 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.119610 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.119651 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.119691 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.131482 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.131529 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.131570 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.131611 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.131652 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.131692 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.143419 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.143419 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.143419 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.143419 (XEN) No periodic timer Oct 4 01:51:22.143419 (XEN) UNIT84 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.155493 (XEN) VCPU84: CPU6 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.155554 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.167477 (XEN) GICH_LRs (vcpu 84) mask=0 Oct 4 01:51:22.167527 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.167568 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.167609 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.167649 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.167690 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.179471 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.179517 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.179558 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.179603 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.179644 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.179684 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.191482 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.191531 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.191572 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.191613 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.191659 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.191702 (XEN) No periodic timer Oct 4 01:51:22.203519 (XEN) UNIT85 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.203602 (XEN) VCPU85: CPU34 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.212783 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.212833 (XEN) GICH_LRs (vcpu 85) mask=0 Oct 4 01:51:22.212876 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.224777 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.224825 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.224867 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.224907 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.224948 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.224989 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.236799 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.236847 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.236888 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.236929 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.236970 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.237010 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.248775 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.248822 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.248864 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.248905 (XEN) No periodic timer Oct 4 01:51:22.248951 (XEN) UNIT86 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.260787 (XEN) VCPU86: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.260840 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.260885 (XEN) GICH_LRs (vcpu 86) mask=0 Oct 4 01:51:22.272774 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.272821 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.272862 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.272903 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.272943 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.284771 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.284819 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.284863 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.284904 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.284945 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.284985 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.296784 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.296832 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.296873 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.296914 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.296954 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.296994 (XEN) No periodic timer Oct 4 01:51:22.308778 (XEN) UNIT87 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.308830 (XEN) VCPU87: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.320781 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.320831 (XEN) GICH_LRs (vcpu 87) mask=0 Oct 4 01:51:22.320874 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.320915 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.320955 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.332766 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.332813 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.332853 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.332894 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.332934 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.344782 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.344831 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.344872 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.344918 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.344961 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.345002 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.356776 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.356822 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.356863 (XEN) No periodic timer Oct 4 01:51:22.356904 (XEN) UNIT88 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.356950 (XEN) VCPU88: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.368798 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.368853 (XEN) GICH_LRs (vcpu 88) mask=0 Oct 4 01:51:22.368897 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.380768 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.380814 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.380855 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.380896 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.380936 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.380976 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.392786 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.392833 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.392875 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.392915 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.392956 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.392996 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.404780 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.404861 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.404905 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.404946 (XEN) No periodic timer Oct 4 01:51:22.404986 (XEN) UNIT89 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.416788 (XEN) VCPU89: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.416842 (XEN) pause_count=0 pause_flags=0 Oct 4 01:51:22.428771 (XEN) GICH_LRs (vcpu 89) mask=0 Oct 4 01:51:22.428820 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.428861 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.428901 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.428941 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.428981 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.440776 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.440824 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.440865 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.440906 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.440946 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.440987 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.452784 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.452831 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.452872 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.452913 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.452953 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.452993 (XEN) No periodic timer Oct 4 01:51:22.464781 (XEN) UNIT90 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.464833 (XEN) VCPU90: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.476780 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.476830 (XEN) GICH_LRs (vcpu 90) mask=0 Oct 4 01:51:22.476873 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.476914 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.488780 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.488829 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.488870 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.488911 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.488951 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.488991 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.500803 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.500852 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.500893 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.500935 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.500975 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.501016 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.512824 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.512881 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.512924 (XEN) No periodic timer Oct 4 01:51:22.512966 (XEN) UNIT91 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.513012 (XEN) VCPU91: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.524796 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.524846 (XEN) GICH_LRs (vcpu 91) mask=0 Oct 4 01:51:22.536768 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.536815 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.536856 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.536898 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.536939 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.536979 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.548792 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.548840 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.548881 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.548922 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.548961 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.549001 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.560771 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.560818 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.560860 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.560900 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.560941 (XEN) No periodic timer Oct 4 01:51:22.560982 (XEN) UNIT92 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.572790 (XEN) VCPU92: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.572847 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.584764 (XEN) GICH_LRs (vcpu 92) mask=0 Oct 4 01:51:22.584813 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.584854 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.584894 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.584934 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.596769 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.596815 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.596856 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.596896 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.596936 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.597012 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.608784 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.608832 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.608874 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.608915 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.608955 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.608996 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.620780 (XEN) No periodic timer Oct 4 01:51:22.620828 (XEN) UNIT93 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.620875 (XEN) VCPU93: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.632798 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.632848 (XEN) GICH_LRs (vcpu 93) mask=0 Oct 4 01:51:22.632891 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.632932 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.644730 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.644757 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.644779 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.644802 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.644824 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.644849 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.656886 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.656942 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.656985 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.657025 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.657066 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.657106 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.668880 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.668936 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.668978 (XEN) No periodic timer Oct 4 01:51:22.669021 (XEN) UNIT94 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.680874 (XEN) VCPU94: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.680940 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.680985 (XEN) GICH_LRs (vcpu 94) mask=0 Oct 4 01:51:22.692834 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.692891 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.692934 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.692975 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.693016 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.693056 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.704719 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.704750 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.704774 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.704797 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.704819 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.704841 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.716833 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.716889 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.716932 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.716973 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.717014 (XEN) No periodic timer Oct 4 01:51:22.728812 (XEN) UNIT95 affinities: hard={0-95} soft={0-95} Oct 4 01:51:22.728892 (XEN) VCPU95: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 01:51:22.728946 (XEN) pause_count=0 pause_flags=1 Oct 4 01:51:22.740797 (XEN) GICH_LRs (vcpu 95) mask=0 Oct 4 01:51:22.740848 (XEN) VCPU_LR[0]=0 Oct 4 01:51:22.740890 (XEN) VCPU_LR[1]=0 Oct 4 01:51:22.740931 (XEN) VCPU_LR[2]=0 Oct 4 01:51:22.740972 (XEN) VCPU_LR[3]=0 Oct 4 01:51:22.752780 (XEN) VCPU_LR[4]=0 Oct 4 01:51:22.752828 (XEN) VCPU_LR[5]=0 Oct 4 01:51:22.752869 (XEN) VCPU_LR[6]=0 Oct 4 01:51:22.752910 (XEN) VCPU_LR[7]=0 Oct 4 01:51:22.752950 (XEN) VCPU_LR[8]=0 Oct 4 01:51:22.752990 (XEN) VCPU_LR[9]=0 Oct 4 01:51:22.764880 (XEN) VCPU_LR[10]=0 Oct 4 01:51:22.764936 (XEN) VCPU_LR[11]=0 Oct 4 01:51:22.764979 (XEN) VCPU_LR[12]=0 Oct 4 01:51:22.765020 (XEN) VCPU_LR[13]=0 Oct 4 01:51:22.765060 (XEN) VCPU_LR[14]=0 Oct 4 01:51:22.776867 (XEN) VCPU_LR[15]=0 Oct 4 01:51:22.776924 (XEN) No periodic timer Oct 4 01:51:22.776968 (XEN) Notifying guest 0:0 (virq 1, port 0) Oct 4 01:51:22.777013 (XEN) Notifying guest 0:1 (virq 1, port 0) Oct 4 01:51:22.788877 (XEN) Notifying guest 0:2 (virq 1, port 0) Oct 4 01:51:22.788939 (XEN) Notifying guest 0:3 (virq 1, port 0) Oct 4 01:51:22.788985 (XEN) Notifying guest 0:4 (virq 1, port 0) Oct 4 01:51:22.789029 (XEN) Notifying guest 0:5 (virq 1, port 0) Oct 4 01:51:22.800884 (XEN) Notifying guest 0:6 (virq 1, port 0) Oct 4 01:51:22.800944 (XEN) Notifying guest 0:7 (virq 1, port 0) Oct 4 01:51:22.801014 (XEN) Notifying guest 0:8 (virq 1, port 0) Oct 4 01:51:22.812888 (XEN) Notifying guest 0:9 (virq 1, port 0) Oct 4 01:51:22.812947 (XEN) Notifying guest 0:10 (virq 1, port 0) Oct 4 01:51:22.812993 (XEN) Notifying guest 0:11 (virq 1, port 0) Oct 4 01:51:22.824884 (XEN) Notifying guest 0:12 (virq 1, port 0) Oct 4 01:51:22.824943 (XEN) Notifying guest 0:13 (virq 1, port 0) Oct 4 01:51:22.824989 (XEN) Notifying guest 0:14 (virq 1, port 0) Oct 4 01:51:22.836896 (XEN) Notifying guest 0:15 (virq 1, port 0) Oct 4 01:51:22.836956 (XEN) Notifying guest 0:16 (virq 1, port 0) Oct 4 01:51:22.837002 (XEN) Notifying guest 0:17 (virq 1, port 0) Oct 4 01:51:22.848877 (XEN) Notifying guest 0:18 (virq 1, port 0) Oct 4 01:51:22.848936 (XEN) Notifying guest 0:19 (virq 1, port 0) Oct 4 01:51:22.848981 (XEN) Notifying guest 0:20 (virq 1, port 0) Oct 4 01:51:22.860866 (XEN) Notifying guest 0:21 (virq 1, port 0) Oct 4 01:51:22.860925 (XEN) Notifying guest 0:22 (virq 1, port 0) Oct 4 01:51:22.860970 (XEN) Notifying guest 0:23 (virq 1, port 0) Oct 4 01:51:22.872894 (XEN) Notifying guest 0:24 (virq 1, port 0) Oct 4 01:51:22.872953 (XEN) Notifying guest 0:25 (virq 1, port 0) Oct 4 01:51:22.872999 (XEN) Notifying guest 0:26 (virq 1, port 0) Oct 4 01:51:22.884870 (XEN) Notifying guest 0:27 (virq 1, port 0) Oct 4 01:51:22.884930 (XEN) Notifying guest 0:28 (virq 1, port 0) Oct 4 01:51:22.884975 (XEN) Notifying guest 0:29 (virq 1, port 0) Oct 4 01:51:22.896891 (XEN) Notifying guest 0:30 (virq 1, port 0) Oct 4 01:51:22.896951 (XEN) Notifying guest 0:31 (virq 1, port 0) Oct 4 01:51:22.896996 (XEN) Notifying guest 0:32 (virq 1, port 0) Oct 4 01:51:22.908886 (XEN) Notifying guest 0:33 (virq 1, port 0) Oct 4 01:51:22.908946 (XEN) Notifying guest 0:34 (virq 1, port 0) Oct 4 01:51:22.908991 (XEN) Notifying guest 0:35 (virq 1, port 0) Oct 4 01:51:22.920877 (XEN) Notifying guest 0:36 (virq 1, port 0) Oct 4 01:51:22.920937 (XEN) Notifying guest 0:37 (virq 1, port 0) Oct 4 01:51:22.920983 (XEN) Notifying guest 0:38 (virq 1, port 0) Oct 4 01:51:22.932880 (XEN) Notifying guest 0:39 (virq 1, port 0) Oct 4 01:51:22.932940 (XEN) Notifying guest 0:40 (virq 1, port 0) Oct 4 01:51:22.932987 (XEN) Notifying guest 0:41 (virq 1, port 0) Oct 4 01:51:22.944904 (XEN) Notifying guest 0:42 (virq 1, port 0) Oct 4 01:51:22.945009 (XEN) Notifying guest 0:43 (virq 1, port 0) Oct 4 01:51:22.945039 (XEN) Notifying guest 0:44 (virq 1, port 0) Oct 4 01:51:22.956848 (XEN) Notifying guest 0:45 (virq 1, port 0) Oct 4 01:51:22.956908 (XEN) Notifying guest 0:46 (virq 1, port 0) Oct 4 01:51:22.956954 (XEN) Notifying guest 0:47 (virq 1, port 0) Oct 4 01:51:22.968902 (XEN) Notifying guest 0:48 (virq 1, port 0) Oct 4 01:51:22.968962 (XEN) Notifying guest 0:49 (virq 1, port 0) Oct 4 01:51:22.969009 (XEN) Notifying guest 0:50 (virq 1, port 0) Oct 4 01:51:22.980883 (XEN) Notifying guest 0:51 (virq 1, port 0) Oct 4 01:51:22.980937 (XEN) Notifying guest 0:52 (virq 1, port 0) Oct 4 01:51:22.980982 (XEN) Notifying guest 0:53 (virq 1, port 0) Oct 4 01:51:22.992887 (XEN) Notifying guest 0:54 (virq 1, port 0) Oct 4 01:51:22.992940 (XEN) Notifying guest 0:55 (virq 1, port 0) Oct 4 01:51:22.992990 (XEN) Notifying guest 0:56 (virq 1, port 0) Oct 4 01:51:23.004806 (XEN) Notifying guest 0:57 (virq 1, port 0) Oct 4 01:51:23.004842 (XEN) Notifying guest 0:58 (virq 1, port 0) Oct 4 01:51:23.004874 (XEN) Notifying guest 0:59 (virq 1, port 0) Oct 4 01:51:23.016786 (XEN) Notifying guest 0:60 (virq 1, port 0) Oct 4 01:51:23.016869 (XEN) Notifying guest 0:61 (virq 1, port 0) Oct 4 01:51:23.016883 (XEN) Notifying guest 0:62 (virq 1, port 0) Oct 4 01:51:23.028815 (XEN) Notifying guest 0:63 (virq 1, port 0) Oct 4 01:51:23.028870 (XEN) Notifying guest 0:64 (virq 1, port 0) Oct 4 01:51:23.028915 (XEN) Notifying guest 0:65 (virq 1, port 0) Oct 4 01:51:23.040813 (XEN) Notifying guest 0:66 (virq 1, port 0) Oct 4 01:51:23.040865 (XEN) Notifying guest 0:67 (virq 1, port 0) Oct 4 01:51:23.040935 (XEN) Notifying guest 0:68 (virq 1, port 0) Oct 4 01:51:23.052804 (XEN) Notifying guest 0:69 (virq 1, port 0) Oct 4 01:51:23.052859 (XEN) Notifying guest 0:70 (virq 1, port 0) Oct 4 01:51:23.052906 (XEN) Notifying guest 0:71 (virq 1, port 0) Oct 4 01:51:23.064792 (XEN) Notifying guest 0:72 (virq 1, port 0) Oct 4 01:51:23.064841 (XEN) Notifying guest 0:73 (virq 1, port 0) Oct 4 01:51:23.064887 (XEN) Notifying guest 0:74 (virq 1, port 0) Oct 4 01:51:23.064931 (XEN) Notifying guest 0:75 (virq 1, port 0) Oct 4 01:51:23.076788 (XEN) Notifying guest 0:76 (virq 1, port 0) Oct 4 01:51:23.076840 (XEN) Notifying guest 0:77 (virq 1, port 0) Oct 4 01:51:23.076885 (XEN) Notifying guest 0:78 (virq 1, port 0) Oct 4 01:51:23.088826 (XEN) Notifying guest 0:79 (virq 1, port 0) Oct 4 01:51:23.088878 (XEN) Notifying guest 0:80 (virq 1, port 0) Oct 4 01:51:23.088923 (XEN) Notifying guest 0:81 (virq 1, port 0) Oct 4 01:51:23.100789 (XEN) Notifying guest 0:82 (virq 1, port 0) Oct 4 01:51:23.100845 (XEN) Notifying guest 0:83 (virq 1, port 0) Oct 4 01:51:23.112794 (XEN) Notifying guest 0:84 (virq 1, port 0) Oct 4 01:51:23.112845 (XEN) Notifying guest 0:85 (virq 1, port 0) Oct 4 01:51:23.112890 (XEN) Notifying guest 0:86 (virq 1, port 0) Oct 4 01:51:23.124810 (XEN) Notifying guest 0:87 (virq 1, port 0) Oct 4 01:51:23.124861 (XEN) Notifying guest 0:88 (virq 1, port 0) Oct 4 01:51:23.124904 (XEN) Notifying guest 0:89 (virq 1, port 0) Oct 4 01:51:23.136787 (XEN) Notifying guest 0:90 (virq 1, port 0) Oct 4 01:51:23.136836 (XEN) Notifying guest 0:91 (virq 1, port 0) Oct 4 01:51:23.136881 (XEN) Notifying guest 0:92 (virq 1, port 0) Oct 4 01:51:23.148799 (XEN) Notifying guest 0:93 (virq 1, port 0) Oct 4 01:51:23.148851 (XEN) Notifying guest 0:94 (virq 1, port 0) Oct 4 01:51:23.148896 (XEN) Notifying guest 0:95 (virq 1, port 0) Oct 4 01:51:23.148940 Oct 4 01:51:29.656088 (XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input) Oct 4 01:51:29.677993 Oct 4 01:51:29.679559