Oct 4 07:24:50.391108 (XEN) VCPU information and callbacks for domain 0: Oct 4 07:24:50.391402 (XEN) UNIT0 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.400719 (XEN) VCPU0: CPU28 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.400719 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.412663 (XEN) GICH_LRs (vcpu 0) mask=0 Oct 4 07:24:50.412663 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.412663 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.412663 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.412663 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.412663 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.424706 (XEN) VCPU_LR[5]=0 Oct 4 07:24:50.424706 (XEN) VCPU_LR[6]=0 Oct 4 07:24:50.424706 (XEN) VCPU_LR[7]=0 Oct 4 07:24:50.424706 (XEN) VCPU_LR[8]=0 Oct 4 07:24:50.424706 (XEN) VCPU_LR[9]=0 Oct 4 07:24:50.424706 (XEN) VCPU_LR[10]=0 Oct 4 07:24:50.436658 (XEN) VCPU_LR[11]=0 Oct 4 07:24:50.436658 (XEN) VCPU_LR[12]=0 Oct 4 07:24:50.436658 (XEN) VCPU_LR[13]=0 Oct 4 07:24:50.436658 (XEN) VCPU_LR[14]=0 Oct 4 07:24:50.448663 (XEN) VCPU_LR[15]=0 Oct 4 07:24:50.448663 (XEN) No periodic timer Oct 4 07:24:50.448663 (XEN) UNIT1 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.448663 (XEN) VCPU1: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.460661 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.460661 (XEN) GICH_LRs (vcpu 1) mask=0 Oct 4 07:24:50.460661 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.460661 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.472660 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.472660 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.472660 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.472660 (XEN) VCPU_LR[5]=0 Oct 4 07:24:50.472660 (XEN) VCPU_LR[6]=0 Oct 4 07:24:50.472660 (XEN) VCPU_LR[7]=0 Oct 4 07:24:50.484663 (XEN) VCPU_LR[8]=0 Oct 4 07:24:50.484663 (XEN) VCPU_LR[9]=0 Oct 4 07:24:50.484663 (XEN) VCPU_LR[10]=0 Oct 4 07:24:50.484663 (XEN) VCPU_LR[11]=0 Oct 4 07:24:50.484663 (XEN) VCPU_LR[12]=0 Oct 4 07:24:50.484663 (XEN) VCPU_LR[13]=0 Oct 4 07:24:50.496659 (XEN) VCPU_LR[14]=0 Oct 4 07:24:50.496659 (XEN) VCPU_LR[15]=0 Oct 4 07:24:50.496659 (XEN) No periodic timer Oct 4 07:24:50.496659 (XEN) UNIT2 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.496659 (XEN) VCPU2: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.508658 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.508658 (XEN) GICH_LRs (vcpu 2) mask=0 Oct 4 07:24:50.520663 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.520663 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.520663 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.520663 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.520663 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.520663 (XEN) VCPU_LR[5]=0 Oct 4 07:24:50.532662 (XEN) VCPU_LR[6]=0 Oct 4 07:24:50.532662 (XEN) VCPU_LR[7]=0 Oct 4 07:24:50.532662 (XEN) VCPU_LR[8]=0 Oct 4 07:24:50.532662 (XEN) VCPU_LR[9]=0 Oct 4 07:24:50.532662 (XEN) VCPU_LR[10]=0 Oct 4 07:24:50.532662 (XEN) VCPU_LR[11]=0 Oct 4 07:24:50.544661 (XEN) VCPU_LR[12]=0 Oct 4 07:24:50.544661 (XEN) VCPU_LR[13]=0 Oct 4 07:24:50.544661 (XEN) VCPU_LR[14]=0 Oct 4 07:24:50.544661 (XEN) VCPU_LR[15]=0 Oct 4 07:24:50.544661 (XEN) No periodic timer Oct 4 07:24:50.544661 (XEN) UNIT3 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.556660 (XEN) VCPU3: CPU84 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.556660 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.568653 (XEN) GICH_LRs (vcpu 3) mask=0 Oct 4 07:24:50.568653 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.568653 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.568653 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.568653 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.580663 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.580663 (XEN) VCPU_LR[5]=0 Oct 4 07:24:50.580663 (XEN) VCPU_LR[6]=0 Oct 4 07:24:50.580663 (XEN) VCPU_LR[7]=0 Oct 4 07:24:50.580663 (XEN) VCPU_LR[8]=0 Oct 4 07:24:50.580663 (XEN) VCPU_LR[9]=0 Oct 4 07:24:50.592663 (XEN) VCPU_LR[10]=0 Oct 4 07:24:50.592663 (XEN) VCPU_LR[11]=0 Oct 4 07:24:50.592663 (XEN) VCPU_LR[12]=0 Oct 4 07:24:50.592663 (XEN) VCPU_LR[13]=0 Oct 4 07:24:50.592663 (XEN) VCPU_LR[14]=0 Oct 4 07:24:50.592663 (XEN) VCPU_LR[15]=0 Oct 4 07:24:50.604662 (XEN) No periodic timer Oct 4 07:24:50.604662 (XEN) UNIT4 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.604662 (XEN) VCPU4: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.616661 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.616661 (XEN) GICH_LRs (vcpu 4) mask=0 Oct 4 07:24:50.616661 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.616661 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.628660 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.628660 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.628660 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.628660 (XEN) VCPU_LR[5]=0 Oct 4 07:24:50.628660 (XEN) VCPU_LR[6]=0 Oct 4 07:24:50.628660 (XEN) VCPU_LR[7]=0 Oct 4 07:24:50.640716 (XEN) VCPU_LR[8]=0 Oct 4 07:24:50.640716 (XEN) VCPU_LR[9]=0 Oct 4 07:24:50.640716 (XEN) VCPU_LR[10]=0 Oct 4 07:24:50.640716 (XEN) VCPU_LR[11]=0 Oct 4 07:24:50.640716 (XEN) VCPU_LR[12]=0 Oct 4 07:24:50.640716 (XEN) VCPU_LR[13]=0 Oct 4 07:24:50.652928 (XEN) VCPU_LR[14]=0 Oct 4 07:24:50.652990 (XEN) VCPU_LR[15]=0 Oct 4 07:24:50.653032 (XEN) No periodic timer Oct 4 07:24:50.653098 (XEN) UNIT5 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.653146 (XEN) VCPU5: CPU49 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.664903 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.664962 (XEN) GICH_LRs (vcpu 5) mask=0 Oct 4 07:24:50.665007 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.676915 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.676971 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.677014 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.677056 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.677098 (XEN) VCPU_LR[5]=0 Oct 4 07:24:50.677163 (XEN) VCPU_LR[6]=0 Oct 4 07:24:50.688918 (XEN) VCPU_LR[7]=0 Oct 4 07:24:50.688974 (XEN) VCPU_LR[8]=0 Oct 4 07:24:50.689016 (XEN) VCPU_LR[9]=0 Oct 4 07:24:50.689057 (XEN) VCPU_LR[10]=0 Oct 4 07:24:50.689121 (XEN) VCPU_LR[11]=0 Oct 4 07:24:50.700908 (XEN) VCPU_LR[12]=0 Oct 4 07:24:50.700965 (XEN) VCPU_LR[13]=0 Oct 4 07:24:50.701008 (XEN) VCPU_LR[14]=0 Oct 4 07:24:50.701050 (XEN) VCPU_LR[15]=0 Oct 4 07:24:50.701113 (XEN) No periodic timer Oct 4 07:24:50.712917 (XEN) UNIT6 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.712979 (XEN) VCPU6: CPU2 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.713031 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.724920 (XEN) GICH_LRs (vcpu 6) mask=0 Oct 4 07:24:50.725002 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.725046 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.725089 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.725131 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.736919 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.736997 (XEN) VCPU_LR[5]=0 Oct 4 07:24:50.737042 (XEN) VCPU_LR[6]=0 Oct 4 07:24:50.737084 (XEN) VCPU_LR[7]=0 Oct 4 07:24:50.737125 (XEN) VCPU_LR[8]=0 Oct 4 07:24:50.737167 (XEN) VCPU_LR[9]=0 Oct 4 07:24:50.748927 (XEN) VCPU_LR[10]=0 Oct 4 07:24:50.748984 (XEN) VCPU_LR[11]=0 Oct 4 07:24:50.749027 (XEN) VCPU_LR[12]=0 Oct 4 07:24:50.749068 (XEN) VCPU_LR[13]=0 Oct 4 07:24:50.749110 (XEN) VCPU_LR[14]=0 Oct 4 07:24:50.749173 (XEN) VCPU_LR[15]=0 Oct 4 07:24:50.760921 (XEN) No periodic timer Oct 4 07:24:50.760978 (XEN) UNIT7 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.761026 (XEN) VCPU7: CPU24 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.772919 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.773000 (XEN) GICH_LRs (vcpu 7) mask=0 Oct 4 07:24:50.773046 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.773089 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.784917 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.784975 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.785041 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.785083 (XEN) VCPU_LR[5]=0 Oct 4 07:24:50.785125 (XEN) VCPU_LR[6]=0 Oct 4 07:24:50.785185 (XEN) VCPU_LR[7]=0 Oct 4 07:24:50.796916 (XEN) VCPU_LR[8]=0 Oct 4 07:24:50.796998 (XEN) VCPU_LR[9]=0 Oct 4 07:24:50.797043 (XEN) VCPU_LR[10]=0 Oct 4 07:24:50.797084 (XEN) VCPU_LR[11]=0 Oct 4 07:24:50.797126 (XEN) VCPU_LR[12]=0 Oct 4 07:24:50.797166 (XEN) VCPU_LR[13]=0 Oct 4 07:24:50.808913 (XEN) VCPU_LR[14]=0 Oct 4 07:24:50.808992 (XEN) VCPU_LR[15]=0 Oct 4 07:24:50.809037 (XEN) No periodic timer Oct 4 07:24:50.809080 (XEN) UNIT8 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.809127 (XEN) VCPU8: CPU35 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.820930 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.821010 (XEN) GICH_LRs (vcpu 8) mask=0 Oct 4 07:24:50.832916 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.832973 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.833016 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.833059 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.833122 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.833165 (XEN) VCPU_LR[5]=0 Oct 4 07:24:50.844917 (XEN) VCPU_LR[6]=0 Oct 4 07:24:50.844973 (XEN) VCPU_LR[7]=0 Oct 4 07:24:50.845015 (XEN) VCPU_LR[8]=0 Oct 4 07:24:50.845080 (XEN) VCPU_LR[9]=0 Oct 4 07:24:50.845123 (XEN) VCPU_LR[10]=0 Oct 4 07:24:50.845164 (XEN) VCPU_LR[11]=0 Oct 4 07:24:50.856920 (XEN) VCPU_LR[12]=0 Oct 4 07:24:50.856975 (XEN) VCPU_LR[13]=0 Oct 4 07:24:50.857041 (XEN) VCPU_LR[14]=0 Oct 4 07:24:50.857085 (XEN) VCPU_LR[15]=0 Oct 4 07:24:50.857127 (XEN) No periodic timer Oct 4 07:24:50.857170 (XEN) UNIT9 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.868938 (XEN) VCPU9: CPU51 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.869023 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.880914 (XEN) GICH_LRs (vcpu 9) mask=0 Oct 4 07:24:50.880972 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.881014 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.881055 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.881096 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.892920 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.892976 (XEN) VCPU_LR[5]=0 Oct 4 07:24:50.893019 (XEN) VCPU_LR[6]=0 Oct 4 07:24:50.893060 (XEN) VCPU_LR[7]=0 Oct 4 07:24:50.893102 (XEN) VCPU_LR[8]=0 Oct 4 07:24:50.893143 (XEN) VCPU_LR[9]=0 Oct 4 07:24:50.904922 (XEN) VCPU_LR[10]=0 Oct 4 07:24:50.904979 (XEN) VCPU_LR[11]=0 Oct 4 07:24:50.905022 (XEN) VCPU_LR[12]=0 Oct 4 07:24:50.905064 (XEN) VCPU_LR[13]=0 Oct 4 07:24:50.905105 (XEN) VCPU_LR[14]=0 Oct 4 07:24:50.905147 (XEN) VCPU_LR[15]=0 Oct 4 07:24:50.916918 (XEN) No periodic timer Oct 4 07:24:50.916975 (XEN) UNIT10 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.917024 (XEN) VCPU10: CPU66 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.928922 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.928982 (XEN) GICH_LRs (vcpu 10) mask=0 Oct 4 07:24:50.929027 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.929069 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.929110 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.940923 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.940978 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.941020 (XEN) VCPU_LR[5]=0 Oct 4 07:24:50.941062 (XEN) VCPU_LR[6]=0 Oct 4 07:24:50.941104 (XEN) VCPU_LR[7]=0 Oct 4 07:24:50.941144 (XEN) VCPU_LR[8]=0 Oct 4 07:24:50.952913 (XEN) VCPU_LR[9]=0 Oct 4 07:24:50.952969 (XEN) VCPU_LR[10]=0 Oct 4 07:24:50.953011 (XEN) VCPU_LR[11]=0 Oct 4 07:24:50.953052 (XEN) VCPU_LR[12]=0 Oct 4 07:24:50.953093 (XEN) VCPU_LR[13]=0 Oct 4 07:24:50.964923 (XEN) VCPU_LR[14]=0 Oct 4 07:24:50.964978 (XEN) VCPU_LR[15]=0 Oct 4 07:24:50.965021 (XEN) No periodic timer Oct 4 07:24:50.965063 (XEN) UNIT11 affinities: hard={0-95} soft={0-95} Oct 4 07:24:50.976924 (XEN) VCPU11: CPU82 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:50.976989 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:50.977034 (XEN) GICH_LRs (vcpu 11) mask=0 Oct 4 07:24:50.988928 (XEN) VCPU_LR[0]=0 Oct 4 07:24:50.988984 (XEN) VCPU_LR[1]=0 Oct 4 07:24:50.989027 (XEN) VCPU_LR[2]=0 Oct 4 07:24:50.989085 (XEN) VCPU_LR[3]=0 Oct 4 07:24:50.989130 (XEN) VCPU_LR[4]=0 Oct 4 07:24:50.989171 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.000924 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.000980 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.001023 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.001066 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.001108 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.001149 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.012922 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.012978 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.013021 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.013062 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.013103 (XEN) No periodic timer Oct 4 07:24:51.013145 (XEN) UNIT12 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.024937 (XEN) VCPU12: CPU8 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.025001 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.036925 (XEN) GICH_LRs (vcpu 12) mask=0 Oct 4 07:24:51.036984 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.037027 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.037068 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.037109 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.048919 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.048975 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.049018 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.049059 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.049099 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.049140 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.060916 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.060973 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.061016 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.061057 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.061099 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.061140 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.072898 (XEN) No periodic timer Oct 4 07:24:51.072955 (XEN) UNIT13 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.073003 (XEN) VCPU13: CPU86 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.084921 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.084979 (XEN) GICH_LRs (vcpu 13) mask=0 Oct 4 07:24:51.085024 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.096921 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.096978 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.097021 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.097062 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.097103 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.097144 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.108915 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.108974 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.109016 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.109058 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.109099 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.109139 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.120926 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.120983 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.121026 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.121068 (XEN) No periodic timer Oct 4 07:24:51.121110 (XEN) UNIT14 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.132918 (XEN) VCPU14: CPU38 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.132983 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.133028 (XEN) GICH_LRs (vcpu 14) mask=0 Oct 4 07:24:51.144916 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.144972 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.145015 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.145056 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.145097 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.145138 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.156926 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.156982 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.157024 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.157065 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.157105 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.157146 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.168923 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.168978 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.169021 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.169061 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.169103 (XEN) No periodic timer Oct 4 07:24:51.180920 (XEN) UNIT15 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.180982 (XEN) VCPU15: CPU53 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.181034 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.192940 (XEN) GICH_LRs (vcpu 15) mask=0 Oct 4 07:24:51.193000 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.193042 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.193083 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.193123 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.204911 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.204967 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.205009 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.205050 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.205091 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.216920 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.216976 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.217018 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.217059 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.217100 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.217141 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.228924 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.228980 (XEN) No periodic timer Oct 4 07:24:51.229023 (XEN) UNIT16 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.229070 (XEN) VCPU16: CPU67 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.240927 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.240985 (XEN) GICH_LRs (vcpu 16) mask=0 Oct 4 07:24:51.241030 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.252918 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.252974 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.253016 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.253057 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.253099 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.253139 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.264925 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.264982 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.265025 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.265066 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.265107 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.265148 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.276921 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.276978 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.277021 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.277062 (XEN) No periodic timer Oct 4 07:24:51.277104 (XEN) UNIT17 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.288925 (XEN) VCPU17: CPU83 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.288990 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.289035 (XEN) GICH_LRs (vcpu 17) mask=0 Oct 4 07:24:51.300922 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.300978 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.301020 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.301061 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.301102 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.312916 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.312973 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.313016 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.313057 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.313098 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.313139 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.324910 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.324967 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.325009 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.325051 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.325092 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.336909 (XEN) No periodic timer Oct 4 07:24:51.336967 (XEN) UNIT18 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.337015 (XEN) VCPU18: CPU6 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.348931 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.348990 (XEN) GICH_LRs (vcpu 18) mask=0 Oct 4 07:24:51.349035 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.349076 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.349117 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.360922 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.360977 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.361019 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.361060 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.361101 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.361141 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.372926 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.372982 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.373024 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.373065 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.373106 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.373147 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.384915 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.384971 (XEN) No periodic timer Oct 4 07:24:51.385031 (XEN) UNIT19 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.385082 (XEN) VCPU19: CPU23 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.396925 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.396983 (XEN) GICH_LRs (vcpu 19) mask=0 Oct 4 07:24:51.397028 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.408918 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.408974 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.409017 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.409058 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.409098 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.409138 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.420916 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.420971 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.421014 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.421055 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.421097 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.421137 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.432919 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.432974 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.433017 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.433058 (XEN) No periodic timer Oct 4 07:24:51.433099 (XEN) UNIT20 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.444917 (XEN) VCPU20: CPU37 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.444981 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.445026 (XEN) GICH_LRs (vcpu 20) mask=0 Oct 4 07:24:51.456905 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.456961 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.457004 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.457044 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.468929 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.468986 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.469029 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.469070 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.469111 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.469151 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.480917 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.480973 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.481016 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.481057 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.481097 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.481136 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.492919 (XEN) No periodic timer Oct 4 07:24:51.492976 (XEN) UNIT21 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.493024 (XEN) VCPU21: CPU54 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.504919 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.504978 (XEN) GICH_LRs (vcpu 21) mask=0 Oct 4 07:24:51.505023 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.505064 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.505105 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.516918 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.516973 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.517016 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.517057 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.517098 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.517138 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.528919 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.528975 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.529018 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.529058 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.529099 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.540919 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.540977 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.541019 (XEN) No periodic timer Oct 4 07:24:51.541061 (XEN) UNIT22 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.541108 (XEN) VCPU22: CPU68 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.552924 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.552982 (XEN) GICH_LRs (vcpu 22) mask=0 Oct 4 07:24:51.553026 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.564925 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.564980 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.565022 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.565063 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.565104 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.565144 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.576917 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.576972 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.577015 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.577056 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.577097 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.577156 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.588908 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.588964 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.589006 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.589047 (XEN) No periodic timer Oct 4 07:24:51.589087 (XEN) UNIT23 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.600932 (XEN) VCPU23: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.600996 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.612921 (XEN) GICH_LRs (vcpu 23) mask=0 Oct 4 07:24:51.612979 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.613021 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.613062 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.613102 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.624927 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.624983 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.625025 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.625066 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.625107 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.625148 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.636914 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.636970 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.637013 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.637054 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.637094 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.637135 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.648917 (XEN) No periodic timer Oct 4 07:24:51.648973 (XEN) UNIT24 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.649021 (XEN) VCPU24: CPU10 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.660925 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.660983 (XEN) GICH_LRs (vcpu 24) mask=0 Oct 4 07:24:51.661028 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.661069 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.672916 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.672973 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.673016 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.673056 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.673096 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.673136 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.684911 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.684969 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.685012 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.685053 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.685094 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.685134 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.696917 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.696973 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.697016 (XEN) No periodic timer Oct 4 07:24:51.697058 (XEN) UNIT25 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.697104 (XEN) VCPU25: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.708922 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.708980 (XEN) GICH_LRs (vcpu 25) mask=0 Oct 4 07:24:51.720921 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.720977 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.721019 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.721060 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.721101 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.721141 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.732922 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.732977 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.733019 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.733061 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.733101 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.733142 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.744914 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.744970 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.745013 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.745054 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.745095 (XEN) No periodic timer Oct 4 07:24:51.756924 (XEN) UNIT26 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.756987 (XEN) VCPU26: CPU43 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.757039 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.768924 (XEN) GICH_LRs (vcpu 26) mask=0 Oct 4 07:24:51.768982 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.769025 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.769065 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.769106 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.780922 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.780978 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.781020 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.781061 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.781119 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.781163 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.792919 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.792976 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.793018 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.793059 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.793100 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.793141 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.804922 (XEN) No periodic timer Oct 4 07:24:51.804978 (XEN) UNIT27 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.805026 (XEN) VCPU27: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.816929 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.816988 (XEN) GICH_LRs (vcpu 27) mask=0 Oct 4 07:24:51.817033 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.817075 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.828917 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.828973 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.829016 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.829057 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.829097 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.829138 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.840908 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.840964 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.841006 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.841048 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.841089 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.852918 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.852974 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.853017 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.853058 (XEN) No periodic timer Oct 4 07:24:51.853099 (XEN) UNIT28 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.864912 (XEN) VCPU28: CPU69 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.864977 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.865022 (XEN) GICH_LRs (vcpu 28) mask=0 Oct 4 07:24:51.876926 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.876983 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.877025 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.877066 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.877107 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.877147 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.888923 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.888978 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.889020 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.889060 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.889101 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.889141 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.900918 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.900974 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.901016 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.901057 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.901099 (XEN) No periodic timer Oct 4 07:24:51.912920 (XEN) UNIT29 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.912982 (XEN) VCPU29: CPU90 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.913033 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.924922 (XEN) GICH_LRs (vcpu 29) mask=0 Oct 4 07:24:51.924981 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.925023 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.925064 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.925104 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.936920 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.936976 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.937019 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.937059 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.937099 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.937140 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.948917 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.948972 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.949015 (XEN) VCPU_LR[12]=0 Oct 4 07:24:51.949056 (XEN) VCPU_LR[13]=0 Oct 4 07:24:51.949097 (XEN) VCPU_LR[14]=0 Oct 4 07:24:51.949138 (XEN) VCPU_LR[15]=0 Oct 4 07:24:51.960925 (XEN) No periodic timer Oct 4 07:24:51.960982 (XEN) UNIT30 affinities: hard={0-95} soft={0-95} Oct 4 07:24:51.961030 (XEN) VCPU30: CPU11 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:51.972932 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:51.972990 (XEN) GICH_LRs (vcpu 30) mask=0 Oct 4 07:24:51.973035 (XEN) VCPU_LR[0]=0 Oct 4 07:24:51.984921 (XEN) VCPU_LR[1]=0 Oct 4 07:24:51.984977 (XEN) VCPU_LR[2]=0 Oct 4 07:24:51.985038 (XEN) VCPU_LR[3]=0 Oct 4 07:24:51.985082 (XEN) VCPU_LR[4]=0 Oct 4 07:24:51.985123 (XEN) VCPU_LR[5]=0 Oct 4 07:24:51.985163 (XEN) VCPU_LR[6]=0 Oct 4 07:24:51.996926 (XEN) VCPU_LR[7]=0 Oct 4 07:24:51.996982 (XEN) VCPU_LR[8]=0 Oct 4 07:24:51.997025 (XEN) VCPU_LR[9]=0 Oct 4 07:24:51.997067 (XEN) VCPU_LR[10]=0 Oct 4 07:24:51.997108 (XEN) VCPU_LR[11]=0 Oct 4 07:24:51.997148 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.008925 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.008982 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.009024 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.009066 (XEN) No periodic timer Oct 4 07:24:52.009108 (XEN) UNIT31 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.020915 (XEN) VCPU31: CPU87 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.020980 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.021025 (XEN) GICH_LRs (vcpu 31) mask=0 Oct 4 07:24:52.032915 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.032971 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.033013 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.033054 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.033095 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.044912 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.044969 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.045011 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.045052 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.045093 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.045134 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.056918 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.056974 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.057017 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.057058 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.057099 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.057140 (XEN) No periodic timer Oct 4 07:24:52.068915 (XEN) UNIT32 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.068976 (XEN) VCPU32: CPU39 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.069028 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.080922 (XEN) GICH_LRs (vcpu 32) mask=0 Oct 4 07:24:52.080980 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.081022 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.081063 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.081104 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.092901 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.092957 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.092999 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.093039 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.093080 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.104874 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.104904 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.104927 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.104949 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.104972 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.104994 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.116907 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.116962 (XEN) No periodic timer Oct 4 07:24:52.117006 (XEN) UNIT33 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.117052 (XEN) VCPU33: CPU57 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.128936 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.128994 (XEN) GICH_LRs (vcpu 33) mask=0 Oct 4 07:24:52.129039 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.140913 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.140969 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.141012 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.141053 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.141094 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.141135 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.152917 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.152973 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.153014 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.153055 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.153096 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.153138 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.164919 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.164975 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.165018 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.165058 (XEN) No periodic timer Oct 4 07:24:52.165100 (XEN) UNIT34 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.176923 (XEN) VCPU34: CPU70 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.176987 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.177050 (XEN) GICH_LRs (vcpu 34) mask=0 Oct 4 07:24:52.188923 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.188979 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.189021 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.189062 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.189102 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.200918 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.200974 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.201016 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.201058 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.201098 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.201140 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.212922 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.212978 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.213021 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.213062 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.213104 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.213145 (XEN) No periodic timer Oct 4 07:24:52.224911 (XEN) UNIT35 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.224972 (XEN) VCPU35: CPU18 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.236923 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.236982 (XEN) GICH_LRs (vcpu 35) mask=0 Oct 4 07:24:52.237026 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.237068 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.237109 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.248834 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.248834 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.248834 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.248834 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.248834 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.248834 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.260942 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.261002 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.261044 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.261086 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.261127 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.272918 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.272974 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.273017 (XEN) No periodic timer Oct 4 07:24:52.273059 (XEN) UNIT36 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.273106 (XEN) VCPU36: CPU88 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.284928 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.284987 (XEN) GICH_LRs (vcpu 36) mask=0 Oct 4 07:24:52.285032 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.296924 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.296979 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.297021 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.297062 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.297102 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.297143 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.308916 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.308972 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.309014 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.309055 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.309096 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.309137 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.320811 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.320842 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.320865 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.320887 (XEN) No periodic timer Oct 4 07:24:52.320910 (XEN) UNIT37 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.332817 (XEN) VCPU37: CPU19 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.332874 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.344839 (XEN) GICH_LRs (vcpu 37) mask=0 Oct 4 07:24:52.344871 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.344895 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.344917 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.344940 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.356877 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.356933 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.356976 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.357017 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.357058 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.357098 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.368865 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.368921 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.368963 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.369004 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.369045 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.369085 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.380903 (XEN) No periodic timer Oct 4 07:24:52.380986 (XEN) UNIT38 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.381037 (XEN) VCPU38: CPU40 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.392857 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.392915 (XEN) GICH_LRs (vcpu 38) mask=0 Oct 4 07:24:52.392961 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.393002 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.404853 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.404910 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.404953 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.404994 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.405035 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.405075 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.416856 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.416912 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.416954 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.416996 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.417036 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.417077 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.428858 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.428914 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.428956 (XEN) No periodic timer Oct 4 07:24:52.428998 (XEN) UNIT39 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.429045 (XEN) VCPU39: CPU55 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.440864 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.440922 (XEN) GICH_LRs (vcpu 39) mask=0 Oct 4 07:24:52.440966 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.452865 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.452920 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.452962 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.453004 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.453044 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.453084 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.464917 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.464973 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.465015 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.465055 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.465096 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.476902 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.476960 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.477003 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.477044 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.477084 (XEN) No periodic timer Oct 4 07:24:52.488911 (XEN) UNIT40 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.488972 (XEN) VCPU40: CPU71 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.489023 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.500877 (XEN) GICH_LRs (vcpu 40) mask=0 Oct 4 07:24:52.500935 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.500977 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.501018 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.501059 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.512915 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.512970 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.513012 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.513054 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.513094 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.513135 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.524913 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.524969 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.525012 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.525053 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.525093 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.525134 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.536913 (XEN) No periodic timer Oct 4 07:24:52.536969 (XEN) UNIT41 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.537017 (XEN) VCPU41: CPU89 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.548918 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.548976 (XEN) GICH_LRs (vcpu 41) mask=0 Oct 4 07:24:52.549021 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.549062 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.560915 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.560971 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.561013 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.561054 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.561094 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.561135 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.572873 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.572930 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.572972 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.573013 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.573054 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.573112 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.584915 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.584971 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.585013 (XEN) No periodic timer Oct 4 07:24:52.585055 (XEN) UNIT42 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.585101 (XEN) VCPU42: CPU12 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.596918 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.596977 (XEN) GICH_LRs (vcpu 42) mask=0 Oct 4 07:24:52.608880 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.608935 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.608977 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.609019 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.609059 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.620917 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.620974 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.621016 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.621057 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.621098 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.621138 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.632914 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.632971 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.633013 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.633055 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.633096 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.633137 (XEN) No periodic timer Oct 4 07:24:52.644906 (XEN) UNIT43 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.644968 (XEN) VCPU43: CPU25 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.645019 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.656911 (XEN) GICH_LRs (vcpu 43) mask=0 Oct 4 07:24:52.656969 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.657012 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.657053 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.657093 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.668917 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.668973 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.669015 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.669055 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.669096 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.669137 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.680825 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.680856 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.680879 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.680901 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.680923 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.692863 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.692921 (XEN) No periodic timer Oct 4 07:24:52.692964 (XEN) UNIT44 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.693012 (XEN) VCPU44: CPU41 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.704929 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.704987 (XEN) GICH_LRs (vcpu 44) mask=0 Oct 4 07:24:52.705032 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.705074 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.716917 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.716972 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.717014 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.717055 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.717095 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.717135 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.728872 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.728928 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.728970 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.729012 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.729052 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.740877 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.740933 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.740975 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.741017 (XEN) No periodic timer Oct 4 07:24:52.741058 (XEN) UNIT45 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.752926 (XEN) VCPU45: CPU56 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.752992 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.753039 (XEN) GICH_LRs (vcpu 45) mask=0 Oct 4 07:24:52.764918 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.764973 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.765016 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.765057 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.765098 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.776911 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.776967 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.777010 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.777068 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.777112 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.777153 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.788916 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.788972 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.789015 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.789056 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.789096 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.789137 (XEN) No periodic timer Oct 4 07:24:52.800917 (XEN) UNIT46 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.800979 (XEN) VCPU46: CPU72 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.801030 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.812918 (XEN) GICH_LRs (vcpu 46) mask=0 Oct 4 07:24:52.812976 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.813018 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.813059 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.824915 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.824972 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.825015 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.825056 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.825097 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.825137 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.836913 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.836971 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.837013 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.837055 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.837096 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.837136 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.848913 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.848970 (XEN) No periodic timer Oct 4 07:24:52.849013 (XEN) UNIT47 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.849060 (XEN) VCPU47: CPU91 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.860915 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.860973 (XEN) GICH_LRs (vcpu 47) mask=0 Oct 4 07:24:52.861018 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.872921 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.872976 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.873019 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.873060 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.873100 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.873141 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.884914 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.884969 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.885012 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.885052 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.885093 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.885134 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.896926 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.896983 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.897025 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.897066 (XEN) No periodic timer Oct 4 07:24:52.897108 (XEN) UNIT48 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.908919 (XEN) VCPU48: CPU13 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.908983 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.920920 (XEN) GICH_LRs (vcpu 48) mask=0 Oct 4 07:24:52.920980 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.921023 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.921063 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.921104 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.921144 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.932925 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.932981 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.933023 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.933064 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.933105 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.933146 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.944920 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.944976 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.945018 (XEN) VCPU_LR[13]=0 Oct 4 07:24:52.945060 (XEN) VCPU_LR[14]=0 Oct 4 07:24:52.945100 (XEN) VCPU_LR[15]=0 Oct 4 07:24:52.945141 (XEN) No periodic timer Oct 4 07:24:52.956903 (XEN) UNIT49 affinities: hard={0-95} soft={0-95} Oct 4 07:24:52.956965 (XEN) VCPU49: CPU27 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:52.968925 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:52.968984 (XEN) GICH_LRs (vcpu 49) mask=0 Oct 4 07:24:52.969029 (XEN) VCPU_LR[0]=0 Oct 4 07:24:52.969070 (XEN) VCPU_LR[1]=0 Oct 4 07:24:52.969110 (XEN) VCPU_LR[2]=0 Oct 4 07:24:52.980913 (XEN) VCPU_LR[3]=0 Oct 4 07:24:52.980986 (XEN) VCPU_LR[4]=0 Oct 4 07:24:52.981032 (XEN) VCPU_LR[5]=0 Oct 4 07:24:52.981074 (XEN) VCPU_LR[6]=0 Oct 4 07:24:52.981114 (XEN) VCPU_LR[7]=0 Oct 4 07:24:52.992921 (XEN) VCPU_LR[8]=0 Oct 4 07:24:52.992977 (XEN) VCPU_LR[9]=0 Oct 4 07:24:52.993020 (XEN) VCPU_LR[10]=0 Oct 4 07:24:52.993062 (XEN) VCPU_LR[11]=0 Oct 4 07:24:52.993102 (XEN) VCPU_LR[12]=0 Oct 4 07:24:52.993143 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.004924 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.004980 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.005022 (XEN) No periodic timer Oct 4 07:24:53.005064 (XEN) UNIT50 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.005111 (XEN) VCPU50: CPU42 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.016934 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.016992 (XEN) GICH_LRs (vcpu 50) mask=0 Oct 4 07:24:53.017037 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.028923 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.028979 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.029021 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.029061 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.029102 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.029143 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.040923 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.040979 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.041021 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.041062 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.041103 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.041144 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.052921 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.052977 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.053019 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.053060 (XEN) No periodic timer Oct 4 07:24:53.053102 (XEN) UNIT51 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.064926 (XEN) VCPU51: CPU85 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.064990 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.076913 (XEN) GICH_LRs (vcpu 51) mask=0 Oct 4 07:24:53.076972 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.077015 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.077056 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.077096 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.077136 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.088919 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.088975 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.089017 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.089057 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.089097 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.089137 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.100925 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.100981 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.101023 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.101064 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.101105 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.101146 (XEN) No periodic timer Oct 4 07:24:53.112910 (XEN) UNIT52 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.112971 (XEN) VCPU52: CPU73 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.124928 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.124986 (XEN) GICH_LRs (vcpu 52) mask=0 Oct 4 07:24:53.125031 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.125072 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.136920 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.136976 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.137018 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.137059 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.137099 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.137140 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.148914 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.148970 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.149013 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.149054 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.149095 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.149136 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.160917 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.160973 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.161015 (XEN) No periodic timer Oct 4 07:24:53.161057 (XEN) UNIT53 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.161103 (XEN) VCPU53: CPU52 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.172930 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.173007 (XEN) GICH_LRs (vcpu 53) mask=0 Oct 4 07:24:53.184916 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.184973 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.185015 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.185056 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.185096 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.185137 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.196916 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.196973 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.197015 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.197056 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.197096 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.197136 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.208919 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.208975 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.209018 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.209059 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.209101 (XEN) No periodic timer Oct 4 07:24:53.209143 (XEN) UNIT54 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.220925 (XEN) VCPU54: CPU14 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.220989 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.232909 (XEN) GICH_LRs (vcpu 54) mask=0 Oct 4 07:24:53.232968 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.233010 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.233051 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.233091 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.244918 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.244974 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.245016 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.245058 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.245098 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.245139 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.256928 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.256984 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.257026 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.257067 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.257108 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.257149 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.268927 (XEN) No periodic timer Oct 4 07:24:53.268983 (XEN) UNIT55 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.269032 (XEN) VCPU55: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.280925 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.280984 (XEN) GICH_LRs (vcpu 55) mask=0 Oct 4 07:24:53.281029 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.281070 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.292918 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.292974 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.293016 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.293057 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.293097 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.293138 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.304918 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.304974 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.305016 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.305057 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.305098 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.305139 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.316930 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.316986 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.317028 (XEN) No periodic timer Oct 4 07:24:53.317070 (XEN) UNIT56 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.328918 (XEN) VCPU56: CPU44 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.328982 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.329027 (XEN) GICH_LRs (vcpu 56) mask=0 Oct 4 07:24:53.340923 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.340980 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.341022 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.341063 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.341104 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.341145 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.352922 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.352978 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.353020 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.353061 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.353101 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.353142 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.364910 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.364966 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.365008 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.365050 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.365091 (XEN) No periodic timer Oct 4 07:24:53.376926 (XEN) UNIT57 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.377004 (XEN) VCPU57: CPU58 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.377059 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.388927 (XEN) GICH_LRs (vcpu 57) mask=0 Oct 4 07:24:53.388985 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.389028 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.389069 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.389110 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.400917 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.400972 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.401014 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.401055 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.401096 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.401137 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.412922 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.412978 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.413021 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.413062 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.413103 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.424912 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.424969 (XEN) No periodic timer Oct 4 07:24:53.425012 (XEN) UNIT58 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.425059 (XEN) VCPU58: CPU74 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.436930 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.436988 (XEN) GICH_LRs (vcpu 58) mask=0 Oct 4 07:24:53.437033 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.437074 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.448914 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.448970 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.449013 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.449053 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.449095 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.449135 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.460930 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.460986 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.461029 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.461070 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.461111 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.461151 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.472919 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.472975 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.473017 (XEN) No periodic timer Oct 4 07:24:53.473060 (XEN) UNIT59 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.484920 (XEN) VCPU59: CPU92 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.484985 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.485030 (XEN) GICH_LRs (vcpu 59) mask=0 Oct 4 07:24:53.496921 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.496977 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.497019 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.497060 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.497101 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.508924 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.508980 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.509023 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.509064 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.509104 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.509145 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.520924 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.520980 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.521022 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.521063 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.521103 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.521143 (XEN) No periodic timer Oct 4 07:24:53.532926 (XEN) UNIT60 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.532988 (XEN) VCPU60: CPU15 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.544911 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.544970 (XEN) GICH_LRs (vcpu 60) mask=0 Oct 4 07:24:53.545015 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.545057 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.545098 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.556923 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.556980 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.557022 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.557063 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.557104 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.557144 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.568925 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.568981 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.569024 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.569064 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.569129 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.569173 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.580918 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.580974 (XEN) No periodic timer Oct 4 07:24:53.581018 (XEN) UNIT61 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.581065 (XEN) VCPU61: CPU30 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.592919 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.592977 (XEN) GICH_LRs (vcpu 61) mask=0 Oct 4 07:24:53.593022 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.593062 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.604924 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.604980 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.605022 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.605063 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.605103 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.605144 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.616905 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.616960 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.617003 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.617044 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.617085 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.628935 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.628991 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.629033 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.629075 (XEN) No periodic timer Oct 4 07:24:53.629116 (XEN) UNIT62 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.640932 (XEN) VCPU62: CPU45 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.640996 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.652915 (XEN) GICH_LRs (vcpu 62) mask=0 Oct 4 07:24:53.652974 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.653016 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.653058 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.653099 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.653139 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.664918 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.664974 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.665016 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.665057 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.665097 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.665138 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.676921 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.676977 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.677020 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.677061 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.677101 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.677142 (XEN) No periodic timer Oct 4 07:24:53.688929 (XEN) UNIT63 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.688990 (XEN) VCPU63: CPU59 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.700921 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.700980 (XEN) GICH_LRs (vcpu 63) mask=0 Oct 4 07:24:53.701025 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.701067 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.701108 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.712916 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.712972 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.713014 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.713055 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.713096 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.713136 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.724921 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.724977 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.725019 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.725060 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.725101 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.725141 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.736924 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.736980 (XEN) No periodic timer Oct 4 07:24:53.737023 (XEN) UNIT64 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.737069 (XEN) VCPU64: CPU75 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.748917 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.748975 (XEN) GICH_LRs (vcpu 64) mask=0 Oct 4 07:24:53.760928 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.760984 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.761027 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.761068 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.761109 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.761149 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.772916 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.772972 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.773016 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.773075 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.773119 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.773160 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.784920 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.784977 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.785019 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.785060 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.785101 (XEN) No periodic timer Oct 4 07:24:53.785142 (XEN) UNIT65 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.796923 (XEN) VCPU65: CPU93 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.796987 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.808932 (XEN) GICH_LRs (vcpu 65) mask=0 Oct 4 07:24:53.808991 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.809034 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.809076 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.809116 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.809157 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.820877 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.820907 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.820930 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.820952 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.820974 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.820997 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.832924 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.832980 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.833022 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.833063 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.833104 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.844906 (XEN) No periodic timer Oct 4 07:24:53.844963 (XEN) UNIT66 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.845011 (XEN) VCPU66: CPU0 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.856923 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.856982 (XEN) GICH_LRs (vcpu 66) mask=0 Oct 4 07:24:53.857027 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.857069 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.857109 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.868911 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.868966 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.869008 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.869049 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.869089 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.880918 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.880974 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.881016 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.881057 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.881097 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.881138 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.892928 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.892984 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.893027 (XEN) No periodic timer Oct 4 07:24:53.893069 (XEN) UNIT67 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.904913 (XEN) VCPU67: CPU31 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.904979 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.905025 (XEN) GICH_LRs (vcpu 67) mask=0 Oct 4 07:24:53.916914 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.916970 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.917012 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.917053 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.917093 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.917133 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.928857 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.928914 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.928957 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.928998 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.929039 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.929079 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.940919 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.940976 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.941019 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.941060 (XEN) VCPU_LR[15]=0 Oct 4 07:24:53.941101 (XEN) No periodic timer Oct 4 07:24:53.941142 (XEN) UNIT68 affinities: hard={0-95} soft={0-95} Oct 4 07:24:53.952929 (XEN) VCPU68: CPU46 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:53.952993 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:53.964927 (XEN) GICH_LRs (vcpu 68) mask=0 Oct 4 07:24:53.964986 (XEN) VCPU_LR[0]=0 Oct 4 07:24:53.965029 (XEN) VCPU_LR[1]=0 Oct 4 07:24:53.965069 (XEN) VCPU_LR[2]=0 Oct 4 07:24:53.965110 (XEN) VCPU_LR[3]=0 Oct 4 07:24:53.976940 (XEN) VCPU_LR[4]=0 Oct 4 07:24:53.976999 (XEN) VCPU_LR[5]=0 Oct 4 07:24:53.977042 (XEN) VCPU_LR[6]=0 Oct 4 07:24:53.977083 (XEN) VCPU_LR[7]=0 Oct 4 07:24:53.977123 (XEN) VCPU_LR[8]=0 Oct 4 07:24:53.977164 (XEN) VCPU_LR[9]=0 Oct 4 07:24:53.988929 (XEN) VCPU_LR[10]=0 Oct 4 07:24:53.988987 (XEN) VCPU_LR[11]=0 Oct 4 07:24:53.989030 (XEN) VCPU_LR[12]=0 Oct 4 07:24:53.989071 (XEN) VCPU_LR[13]=0 Oct 4 07:24:53.989111 (XEN) VCPU_LR[14]=0 Oct 4 07:24:53.989153 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.000912 (XEN) No periodic timer Oct 4 07:24:54.000969 (XEN) UNIT69 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.001018 (XEN) VCPU69: CPU60 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.012923 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.012981 (XEN) GICH_LRs (vcpu 69) mask=0 Oct 4 07:24:54.013026 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.013068 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.024921 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.024977 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.025019 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.025060 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.025100 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.025141 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.036926 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.036982 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.037024 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.037065 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.037106 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.037146 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.048930 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.048986 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.049028 (XEN) No periodic timer Oct 4 07:24:54.049070 (XEN) UNIT70 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.060920 (XEN) VCPU70: CPU76 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.060984 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.061030 (XEN) GICH_LRs (vcpu 70) mask=0 Oct 4 07:24:54.072872 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.072902 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.072925 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.072948 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.072999 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.073040 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.084921 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.084974 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.084997 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.085019 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.085041 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.085064 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.096923 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.096979 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.097021 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.097063 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.097142 (XEN) No periodic timer Oct 4 07:24:54.097187 (XEN) UNIT71 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.108929 (XEN) VCPU71: CPU26 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.108993 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.120912 (XEN) GICH_LRs (vcpu 71) mask=0 Oct 4 07:24:54.120969 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.121047 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.121092 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.132911 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.132969 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.133011 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.133052 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.133093 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.133134 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.144920 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.144977 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.145019 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.145060 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.145101 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.145142 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.156912 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.156969 (XEN) No periodic timer Oct 4 07:24:54.157012 (XEN) UNIT72 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.157058 (XEN) VCPU72: CPU1 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.168932 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.168990 (XEN) GICH_LRs (vcpu 72) mask=0 Oct 4 07:24:54.169052 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.169096 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.180923 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.180979 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.181021 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.181062 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.181103 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.181144 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.192923 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.192979 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.193021 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.193062 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.193102 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.193143 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.204924 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.204979 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.205022 (XEN) No periodic timer Oct 4 07:24:54.205063 (XEN) UNIT73 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.216921 (XEN) VCPU73: CPU16 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.216985 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.217030 (XEN) GICH_LRs (vcpu 73) mask=0 Oct 4 07:24:54.228930 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.228986 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.229028 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.229069 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.229109 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.229149 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.240921 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.240976 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.241018 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.241059 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.241100 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.241140 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.252917 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.252973 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.253016 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.253057 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.253098 (XEN) No periodic timer Oct 4 07:24:54.264916 (XEN) UNIT74 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.264977 (XEN) VCPU74: CPU47 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.276919 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.276978 (XEN) GICH_LRs (vcpu 74) mask=0 Oct 4 07:24:54.277023 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.277065 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.277105 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.288924 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.288980 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.289022 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.289063 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.289104 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.289145 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.300924 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.300980 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.301022 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.301063 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.301103 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.301144 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.312917 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.312973 (XEN) No periodic timer Oct 4 07:24:54.313016 (XEN) UNIT75 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.313064 (XEN) VCPU75: CPU61 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.324938 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.324996 (XEN) GICH_LRs (vcpu 75) mask=0 Oct 4 07:24:54.325041 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.336908 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.336965 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.337008 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.337049 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.337090 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.337130 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.348927 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.348985 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.349028 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.349068 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.349109 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.349150 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.360912 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.360968 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.361011 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.361052 (XEN) No periodic timer Oct 4 07:24:54.361094 (XEN) UNIT76 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.372934 (XEN) VCPU76: CPU77 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.373000 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.373045 (XEN) GICH_LRs (vcpu 76) mask=0 Oct 4 07:24:54.384906 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.384962 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.385004 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.385045 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.385086 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.396921 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.396977 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.397019 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.397060 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.397100 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.397140 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.408921 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.408977 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.409019 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.409060 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.409101 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.409141 (XEN) No periodic timer Oct 4 07:24:54.420919 (XEN) UNIT77 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.420980 (XEN) VCPU77: CPU94 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.432919 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.432978 (XEN) GICH_LRs (vcpu 77) mask=0 Oct 4 07:24:54.433023 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.433064 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.433105 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.444922 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.444978 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.445020 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.445061 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.445102 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.445142 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.456923 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.456979 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.457021 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.457062 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.457103 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.457144 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.468923 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.468979 (XEN) No periodic timer Oct 4 07:24:54.469022 (XEN) UNIT78 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.469069 (XEN) VCPU78: CPU3 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.480926 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.480984 (XEN) GICH_LRs (vcpu 78) mask=0 Oct 4 07:24:54.481029 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.492923 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.492980 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.493022 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.493064 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.493104 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.493146 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.504909 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.504966 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.505008 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.505049 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.505090 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.516865 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.516921 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.516964 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.517005 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.517046 (XEN) No periodic timer Oct 4 07:24:54.517087 (XEN) UNIT79 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.528927 (XEN) VCPU79: CPU20 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.528991 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.540919 (XEN) GICH_LRs (vcpu 79) mask=0 Oct 4 07:24:54.540978 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.541020 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.541062 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.541102 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.541143 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.552921 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.552976 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.553018 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.553060 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.553100 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.553141 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.564924 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.564979 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.565021 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.565082 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.565126 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.576920 (XEN) No periodic timer Oct 4 07:24:54.576977 (XEN) UNIT80 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.577025 (XEN) VCPU80: CPU32 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.588927 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.588986 (XEN) GICH_LRs (vcpu 80) mask=0 Oct 4 07:24:54.589031 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.589072 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.589112 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.600923 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.600978 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.601020 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.601061 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.601103 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.601144 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.612914 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.612970 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.613012 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.613053 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.613094 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.613135 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.624917 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.624972 (XEN) No periodic timer Oct 4 07:24:54.625015 (XEN) UNIT81 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.625062 (XEN) VCPU81: CPU62 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.636913 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.636971 (XEN) GICH_LRs (vcpu 81) mask=0 Oct 4 07:24:54.648918 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.648974 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.649016 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.649057 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.649097 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.649138 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.660913 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.660970 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.661012 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.661052 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.661092 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.661133 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.672914 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.672970 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.673012 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.673053 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.673095 (XEN) No periodic timer Oct 4 07:24:54.673136 (XEN) UNIT82 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.684919 (XEN) VCPU82: CPU78 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.684983 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.696922 (XEN) GICH_LRs (vcpu 82) mask=0 Oct 4 07:24:54.696980 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.697022 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.697063 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.697104 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.708929 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.708985 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.709028 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.709068 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.709109 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.709150 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.720918 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.720975 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.721018 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.721059 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.721100 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.721140 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.732919 (XEN) No periodic timer Oct 4 07:24:54.732975 (XEN) UNIT83 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.733023 (XEN) VCPU83: CPU95 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.744917 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.744975 (XEN) GICH_LRs (vcpu 83) mask=0 Oct 4 07:24:54.745020 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.745061 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.745102 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.756922 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.756977 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.757019 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.757059 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.757100 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.768924 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.768999 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.769044 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.769085 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.769125 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.769165 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.780922 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.780977 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.781019 (XEN) No periodic timer Oct 4 07:24:54.781061 (XEN) UNIT84 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.792919 (XEN) VCPU84: CPU4 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.792983 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.793029 (XEN) GICH_LRs (vcpu 84) mask=0 Oct 4 07:24:54.804922 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.804978 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.805021 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.805062 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.805102 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.805143 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.816902 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.816958 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.817000 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.817041 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.817082 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.817124 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.828920 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.828975 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.829018 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.829058 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.829100 (XEN) No periodic timer Oct 4 07:24:54.829141 (XEN) UNIT85 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.840932 (XEN) VCPU85: CPU33 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.840996 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.852885 (XEN) GICH_LRs (vcpu 85) mask=0 Oct 4 07:24:54.852936 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.852978 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.853018 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.853059 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.864914 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.864970 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.865012 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.865053 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.865093 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.865133 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.876911 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.876968 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.877010 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.877052 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.877092 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.877133 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.888911 (XEN) No periodic timer Oct 4 07:24:54.888968 (XEN) UNIT86 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.889016 (XEN) VCPU86: CPU21 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.900927 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.900985 (XEN) GICH_LRs (vcpu 86) mask=0 Oct 4 07:24:54.901029 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.901071 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.912920 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.912975 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.913017 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.913058 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.913098 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.913140 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.924916 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.924971 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.925013 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.925054 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.925094 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.936918 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.936976 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.937018 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.937059 (XEN) No periodic timer Oct 4 07:24:54.937100 (XEN) UNIT87 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.948917 (XEN) VCPU87: CPU63 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.948981 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:54.949026 (XEN) GICH_LRs (vcpu 87) mask=0 Oct 4 07:24:54.960938 (XEN) VCPU_LR[0]=0 Oct 4 07:24:54.960994 (XEN) VCPU_LR[1]=0 Oct 4 07:24:54.961036 (XEN) VCPU_LR[2]=0 Oct 4 07:24:54.961077 (XEN) VCPU_LR[3]=0 Oct 4 07:24:54.961118 (XEN) VCPU_LR[4]=0 Oct 4 07:24:54.961178 (XEN) VCPU_LR[5]=0 Oct 4 07:24:54.972926 (XEN) VCPU_LR[6]=0 Oct 4 07:24:54.972981 (XEN) VCPU_LR[7]=0 Oct 4 07:24:54.973023 (XEN) VCPU_LR[8]=0 Oct 4 07:24:54.973064 (XEN) VCPU_LR[9]=0 Oct 4 07:24:54.973105 (XEN) VCPU_LR[10]=0 Oct 4 07:24:54.973146 (XEN) VCPU_LR[11]=0 Oct 4 07:24:54.984927 (XEN) VCPU_LR[12]=0 Oct 4 07:24:54.984983 (XEN) VCPU_LR[13]=0 Oct 4 07:24:54.985026 (XEN) VCPU_LR[14]=0 Oct 4 07:24:54.985066 (XEN) VCPU_LR[15]=0 Oct 4 07:24:54.985107 (XEN) No periodic timer Oct 4 07:24:54.996919 (XEN) UNIT88 affinities: hard={0-95} soft={0-95} Oct 4 07:24:54.996982 (XEN) VCPU88: CPU80 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:54.997033 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:55.008927 (XEN) GICH_LRs (vcpu 88) mask=0 Oct 4 07:24:55.008985 (XEN) VCPU_LR[0]=0 Oct 4 07:24:55.009027 (XEN) VCPU_LR[1]=0 Oct 4 07:24:55.009069 (XEN) VCPU_LR[2]=0 Oct 4 07:24:55.009109 (XEN) VCPU_LR[3]=0 Oct 4 07:24:55.020917 (XEN) VCPU_LR[4]=0 Oct 4 07:24:55.020973 (XEN) VCPU_LR[5]=0 Oct 4 07:24:55.021015 (XEN) VCPU_LR[6]=0 Oct 4 07:24:55.021056 (XEN) VCPU_LR[7]=0 Oct 4 07:24:55.021097 (XEN) VCPU_LR[8]=0 Oct 4 07:24:55.032921 (XEN) VCPU_LR[9]=0 Oct 4 07:24:55.032977 (XEN) VCPU_LR[10]=0 Oct 4 07:24:55.033019 (XEN) VCPU_LR[11]=0 Oct 4 07:24:55.033061 (XEN) VCPU_LR[12]=0 Oct 4 07:24:55.033101 (XEN) VCPU_LR[13]=0 Oct 4 07:24:55.033143 (XEN) VCPU_LR[14]=0 Oct 4 07:24:55.044924 (XEN) VCPU_LR[15]=0 Oct 4 07:24:55.044981 (XEN) No periodic timer Oct 4 07:24:55.045024 (XEN) UNIT89 affinities: hard={0-95} soft={0-95} Oct 4 07:24:55.045071 (XEN) VCPU89: CPU65 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:55.056925 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:55.056983 (XEN) GICH_LRs (vcpu 89) mask=0 Oct 4 07:24:55.057028 (XEN) VCPU_LR[0]=0 Oct 4 07:24:55.068866 (XEN) VCPU_LR[1]=0 Oct 4 07:24:55.068922 (XEN) VCPU_LR[2]=0 Oct 4 07:24:55.068965 (XEN) VCPU_LR[3]=0 Oct 4 07:24:55.069007 (XEN) VCPU_LR[4]=0 Oct 4 07:24:55.069048 (XEN) VCPU_LR[5]=0 Oct 4 07:24:55.069089 (XEN) VCPU_LR[6]=0 Oct 4 07:24:55.080929 (XEN) VCPU_LR[7]=0 Oct 4 07:24:55.080987 (XEN) VCPU_LR[8]=0 Oct 4 07:24:55.081041 (XEN) VCPU_LR[9]=0 Oct 4 07:24:55.081085 (XEN) VCPU_LR[10]=0 Oct 4 07:24:55.081128 (XEN) VCPU_LR[11]=0 Oct 4 07:24:55.081170 (XEN) VCPU_LR[12]=0 Oct 4 07:24:55.092918 (XEN) VCPU_LR[13]=0 Oct 4 07:24:55.092975 (XEN) VCPU_LR[14]=0 Oct 4 07:24:55.093018 (XEN) VCPU_LR[15]=0 Oct 4 07:24:55.093059 (XEN) No periodic timer Oct 4 07:24:55.093101 (XEN) UNIT90 affinities: hard={0-95} soft={0-95} Oct 4 07:24:55.104916 (XEN) VCPU90: CPU5 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:55.104980 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:55.105025 (XEN) GICH_LRs (vcpu 90) mask=0 Oct 4 07:24:55.116918 (XEN) VCPU_LR[0]=0 Oct 4 07:24:55.116974 (XEN) VCPU_LR[1]=0 Oct 4 07:24:55.117016 (XEN) VCPU_LR[2]=0 Oct 4 07:24:55.117057 (XEN) VCPU_LR[3]=0 Oct 4 07:24:55.117098 (XEN) VCPU_LR[4]=0 Oct 4 07:24:55.117138 (XEN) VCPU_LR[5]=0 Oct 4 07:24:55.128917 (XEN) VCPU_LR[6]=0 Oct 4 07:24:55.128972 (XEN) VCPU_LR[7]=0 Oct 4 07:24:55.129014 (XEN) VCPU_LR[8]=0 Oct 4 07:24:55.129055 (XEN) VCPU_LR[9]=0 Oct 4 07:24:55.129096 (XEN) VCPU_LR[10]=0 Oct 4 07:24:55.129137 (XEN) VCPU_LR[11]=0 Oct 4 07:24:55.140913 (XEN) VCPU_LR[12]=0 Oct 4 07:24:55.140968 (XEN) VCPU_LR[13]=0 Oct 4 07:24:55.141010 (XEN) VCPU_LR[14]=0 Oct 4 07:24:55.141051 (XEN) VCPU_LR[15]=0 Oct 4 07:24:55.141092 (XEN) No periodic timer Oct 4 07:24:55.152920 (XEN) UNIT91 affinities: hard={0-95} soft={0-95} Oct 4 07:24:55.152981 (XEN) VCPU91: CPU22 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:55.164913 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:55.164972 (XEN) GICH_LRs (vcpu 91) mask=0 Oct 4 07:24:55.165035 (XEN) VCPU_LR[0]=0 Oct 4 07:24:55.165080 (XEN) VCPU_LR[1]=0 Oct 4 07:24:55.165121 (XEN) VCPU_LR[2]=0 Oct 4 07:24:55.176921 (XEN) VCPU_LR[3]=0 Oct 4 07:24:55.176977 (XEN) VCPU_LR[4]=0 Oct 4 07:24:55.177019 (XEN) VCPU_LR[5]=0 Oct 4 07:24:55.177060 (XEN) VCPU_LR[6]=0 Oct 4 07:24:55.177101 (XEN) VCPU_LR[7]=0 Oct 4 07:24:55.177142 (XEN) VCPU_LR[8]=0 Oct 4 07:24:55.188922 (XEN) VCPU_LR[9]=0 Oct 4 07:24:55.188977 (XEN) VCPU_LR[10]=0 Oct 4 07:24:55.189020 (XEN) VCPU_LR[11]=0 Oct 4 07:24:55.189061 (XEN) VCPU_LR[12]=0 Oct 4 07:24:55.189102 (XEN) VCPU_LR[13]=0 Oct 4 07:24:55.189143 (XEN) VCPU_LR[14]=0 Oct 4 07:24:55.200929 (XEN) VCPU_LR[15]=0 Oct 4 07:24:55.200985 (XEN) No periodic timer Oct 4 07:24:55.201028 (XEN) UNIT92 affinities: hard={0-95} soft={0-95} Oct 4 07:24:55.201076 (XEN) VCPU92: CPU34 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:55.212932 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:55.212990 (XEN) GICH_LRs (vcpu 92) mask=0 Oct 4 07:24:55.213035 (XEN) VCPU_LR[0]=0 Oct 4 07:24:55.224924 (XEN) VCPU_LR[1]=0 Oct 4 07:24:55.224980 (XEN) VCPU_LR[2]=0 Oct 4 07:24:55.225022 (XEN) VCPU_LR[3]=0 Oct 4 07:24:55.225063 (XEN) VCPU_LR[4]=0 Oct 4 07:24:55.225104 (XEN) VCPU_LR[5]=0 Oct 4 07:24:55.225144 (XEN) VCPU_LR[6]=0 Oct 4 07:24:55.236921 (XEN) VCPU_LR[7]=0 Oct 4 07:24:55.236977 (XEN) VCPU_LR[8]=0 Oct 4 07:24:55.237020 (XEN) VCPU_LR[9]=0 Oct 4 07:24:55.237061 (XEN) VCPU_LR[10]=0 Oct 4 07:24:55.237101 (XEN) VCPU_LR[11]=0 Oct 4 07:24:55.237142 (XEN) VCPU_LR[12]=0 Oct 4 07:24:55.248919 (XEN) VCPU_LR[13]=0 Oct 4 07:24:55.248975 (XEN) VCPU_LR[14]=0 Oct 4 07:24:55.249018 (XEN) VCPU_LR[15]=0 Oct 4 07:24:55.249059 (XEN) No periodic timer Oct 4 07:24:55.249100 (XEN) UNIT93 affinities: hard={0-95} soft={0-95} Oct 4 07:24:55.260937 (XEN) VCPU93: CPU48 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:55.261001 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:55.261046 (XEN) GICH_LRs (vcpu 93) mask=0 Oct 4 07:24:55.272915 (XEN) VCPU_LR[0]=0 Oct 4 07:24:55.272971 (XEN) VCPU_LR[1]=0 Oct 4 07:24:55.273013 (XEN) VCPU_LR[2]=0 Oct 4 07:24:55.273053 (XEN) VCPU_LR[3]=0 Oct 4 07:24:55.273093 (XEN) VCPU_LR[4]=0 Oct 4 07:24:55.284926 (XEN) VCPU_LR[5]=0 Oct 4 07:24:55.284981 (XEN) VCPU_LR[6]=0 Oct 4 07:24:55.285023 (XEN) VCPU_LR[7]=0 Oct 4 07:24:55.285064 (XEN) VCPU_LR[8]=0 Oct 4 07:24:55.285106 (XEN) VCPU_LR[9]=0 Oct 4 07:24:55.285146 (XEN) VCPU_LR[10]=0 Oct 4 07:24:55.296923 (XEN) VCPU_LR[11]=0 Oct 4 07:24:55.296978 (XEN) VCPU_LR[12]=0 Oct 4 07:24:55.297020 (XEN) VCPU_LR[13]=0 Oct 4 07:24:55.297061 (XEN) VCPU_LR[14]=0 Oct 4 07:24:55.297102 (XEN) VCPU_LR[15]=0 Oct 4 07:24:55.308915 (XEN) No periodic timer Oct 4 07:24:55.308971 (XEN) UNIT94 affinities: hard={0-95} soft={0-95} Oct 4 07:24:55.309019 (XEN) VCPU94: CPU64 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:55.320928 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:55.320987 (XEN) GICH_LRs (vcpu 94) mask=0 Oct 4 07:24:55.321031 (XEN) VCPU_LR[0]=0 Oct 4 07:24:55.321073 (XEN) VCPU_LR[1]=0 Oct 4 07:24:55.321114 (XEN) VCPU_LR[2]=0 Oct 4 07:24:55.332910 (XEN) VCPU_LR[3]=0 Oct 4 07:24:55.332965 (XEN) VCPU_LR[4]=0 Oct 4 07:24:55.333007 (XEN) VCPU_LR[5]=0 Oct 4 07:24:55.333048 (XEN) VCPU_LR[6]=0 Oct 4 07:24:55.333088 (XEN) VCPU_LR[7]=0 Oct 4 07:24:55.333129 (XEN) VCPU_LR[8]=0 Oct 4 07:24:55.344918 (XEN) VCPU_LR[9]=0 Oct 4 07:24:55.344974 (XEN) VCPU_LR[10]=0 Oct 4 07:24:55.345017 (XEN) VCPU_LR[11]=0 Oct 4 07:24:55.345058 (XEN) VCPU_LR[12]=0 Oct 4 07:24:55.345099 (XEN) VCPU_LR[13]=0 Oct 4 07:24:55.345139 (XEN) VCPU_LR[14]=0 Oct 4 07:24:55.356916 (XEN) VCPU_LR[15]=0 Oct 4 07:24:55.356972 (XEN) No periodic timer Oct 4 07:24:55.357015 (XEN) UNIT95 affinities: hard={0-95} soft={0-95} Oct 4 07:24:55.357081 (XEN) VCPU95: CPU81 [has=F] poll=0 upcall_pend=00 upcall_mask=01 Oct 4 07:24:55.368923 (XEN) pause_count=0 pause_flags=1 Oct 4 07:24:55.368981 (XEN) GICH_LRs (vcpu 95) mask=0 Oct 4 07:24:55.369026 (XEN) VCPU_LR[0]=0 Oct 4 07:24:55.380916 (XEN) VCPU_LR[1]=0 Oct 4 07:24:55.380972 (XEN) VCPU_LR[2]=0 Oct 4 07:24:55.381014 (XEN) VCPU_LR[3]=0 Oct 4 07:24:55.381055 (XEN) VCPU_LR[4]=0 Oct 4 07:24:55.381096 (XEN) VCPU_LR[5]=0 Oct 4 07:24:55.381136 (XEN) VCPU_LR[6]=0 Oct 4 07:24:55.392903 (XEN) VCPU_LR[7]=0 Oct 4 07:24:55.392959 (XEN) VCPU_LR[8]=0 Oct 4 07:24:55.393001 (XEN) VCPU_LR[9]=0 Oct 4 07:24:55.393042 (XEN) VCPU_LR[10]=0 Oct 4 07:24:55.393083 (XEN) VCPU_LR[11]=0 Oct 4 07:24:55.404918 (XEN) VCPU_LR[12]=0 Oct 4 07:24:55.404975 (XEN) VCPU_LR[13]=0 Oct 4 07:24:55.405018 (XEN) VCPU_LR[14]=0 Oct 4 07:24:55.405058 (XEN) VCPU_LR[15]=0 Oct 4 07:24:55.405099 (XEN) No periodic timer Oct 4 07:24:55.405141 (XEN) Notifying guest 0:0 (virq 1, port 0) Oct 4 07:24:55.416920 (XEN) Notifying guest 0:1 (virq 1, port 0) Oct 4 07:24:55.416979 (XEN) Notifying guest 0:2 (virq 1, port 0) Oct 4 07:24:55.417024 (XEN) Notifying guest 0:3 (virq 1, port 0) Oct 4 07:24:55.428922 (XEN) Notifying guest 0:4 (virq 1, port 0) Oct 4 07:24:55.428981 (XEN) Notifying guest 0:5 (virq 1, port 0) Oct 4 07:24:55.429027 (XEN) Notifying guest 0:6 (virq 1, port 0) Oct 4 07:24:55.440920 (XEN) Notifying guest 0:7 (virq 1, port 0) Oct 4 07:24:55.440980 (XEN) Notifying guest 0:8 (virq 1, port 0) Oct 4 07:24:55.441025 (XEN) Notifying guest 0:9 (virq 1, port 0) Oct 4 07:24:55.452926 (XEN) Notifying guest 0:10 (virq 1, port 0) Oct 4 07:24:55.452985 (XEN) Notifying guest 0:11 (virq 1, port 0) Oct 4 07:24:55.453031 (XEN) Notifying guest 0:12 (virq 1, port 0) Oct 4 07:24:55.464925 (XEN) Notifying guest 0:13 (virq 1, port 0) Oct 4 07:24:55.464984 (XEN) Notifying guest 0:14 (virq 1, port 0) Oct 4 07:24:55.465030 (XEN) Notifying guest 0:15 (virq 1, port 0) Oct 4 07:24:55.476928 (XEN) Notifying guest 0:16 (virq 1, port 0) Oct 4 07:24:55.476987 (XEN) Notifying guest 0:17 (virq 1, port 0) Oct 4 07:24:55.477033 (XEN) Notifying guest 0:18 (virq 1, port 0) Oct 4 07:24:55.488920 (XEN) Notifying guest 0:19 (virq 1, port 0) Oct 4 07:24:55.488980 (XEN) Notifying guest 0:20 (virq 1, port 0) Oct 4 07:24:55.489025 (XEN) Notifying guest 0:21 (virq 1, port 0) Oct 4 07:24:55.500924 (XEN) Notifying guest 0:22 (virq 1, port 0) Oct 4 07:24:55.500984 (XEN) Notifying guest 0:23 (virq 1, port 0) Oct 4 07:24:55.501030 (XEN) Notifying guest 0:24 (virq 1, port 0) Oct 4 07:24:55.512920 (XEN) Notifying guest 0:25 (virq 1, port 0) Oct 4 07:24:55.512981 (XEN) Notifying guest 0:26 (virq 1, port 0) Oct 4 07:24:55.513027 (XEN) Notifying guest 0:27 (virq 1, port 0) Oct 4 07:24:55.513071 (XEN) Notifying guest 0:28 (virq 1, port 0) Oct 4 07:24:55.524940 (XEN) Notifying guest 0:29 (virq 1, port 0) Oct 4 07:24:55.525026 (XEN) Notifying guest 0:30 (virq 1, port 0) Oct 4 07:24:55.536927 (XEN) Notifying guest 0:31 (virq 1, port 0) Oct 4 07:24:55.536987 (XEN) Notifying guest 0:32 (virq 1, port 0) Oct 4 07:24:55.537034 (XEN) Notifying guest 0:33 (virq 1, port 0) Oct 4 07:24:55.548921 (XEN) Notifying guest 0:34 (virq 1, port 0) Oct 4 07:24:55.548980 (XEN) Notifying guest 0:35 (virq 1, port 0) Oct 4 07:24:55.549026 (XEN) Notifying guest 0:36 (virq 1, port 0) Oct 4 07:24:55.560920 (XEN) Notifying guest 0:37 (virq 1, port 0) Oct 4 07:24:55.560980 (XEN) Notifying guest 0:38 (virq 1, port 0) Oct 4 07:24:55.561026 (XEN) Notifying guest 0:39 (virq 1, port 0) Oct 4 07:24:55.572920 (XEN) Notifying guest 0:40 (virq 1, port 0) Oct 4 07:24:55.572980 (XEN) Notifying guest 0:41 (virq 1, port 0) Oct 4 07:24:55.573026 (XEN) Notifying guest 0:42 (virq 1, port 0) Oct 4 07:24:55.584910 (XEN) Notifying guest 0:43 (virq 1, port 0) Oct 4 07:24:55.584970 (XEN) Notifying guest 0:44 (virq 1, port 0) Oct 4 07:24:55.585016 (XEN) Notifying guest 0:45 (virq 1, port 0) Oct 4 07:24:55.585080 (XEN) Notifying guest 0:46 (virq 1, port 0) Oct 4 07:24:55.596926 (XEN) Notifying guest 0:47 (virq 1, port 0) Oct 4 07:24:55.596985 (XEN) Notifying guest 0:48 (virq 1, port 0) Oct 4 07:24:55.597029 (XEN) Notifying guest 0:49 (virq 1, port 0) Oct 4 07:24:55.608926 (XEN) Notifying guest 0:50 (virq 1, port 0) Oct 4 07:24:55.608985 (XEN) Notifying guest 0:51 (virq 1, port 0) Oct 4 07:24:55.609029 (XEN) Notifying guest 0:52 (virq 1, port 0) Oct 4 07:24:55.620921 (XEN) Notifying guest 0:53 (virq 1, port 0) Oct 4 07:24:55.620979 (XEN) Notifying guest 0:54 (virq 1, port 0) Oct 4 07:24:55.621024 (XEN) Notifying guest 0:55 (virq 1, port 0) Oct 4 07:24:55.632918 (XEN) Notifying guest 0:56 (virq 1, port 0) Oct 4 07:24:55.632978 (XEN) Notifying guest 0:57 (virq 1, port 0) Oct 4 07:24:55.633023 (XEN) Notifying guest 0:58 (virq 1, port 0) Oct 4 07:24:55.644924 (XEN) Notifying guest 0:59 (virq 1, port 0) Oct 4 07:24:55.644983 (XEN) Notifying guest 0:60 (virq 1, port 0) Oct 4 07:24:55.645028 (XEN) Notifying guest 0:61 (virq 1, port 0) Oct 4 07:24:55.656930 (XEN) Notifying guest 0:62 (virq 1, port 0) Oct 4 07:24:55.656989 (XEN) Notifying guest 0:63 (virq 1, port 0) Oct 4 07:24:55.668915 (XEN) Notifying guest 0:64 (virq 1, port 0) Oct 4 07:24:55.668977 (XEN) Notifying guest 0:65 (virq 1, port 0) Oct 4 07:24:55.669023 (XEN) Notifying guest 0:66 (virq 1, port 0) Oct 4 07:24:55.669067 (XEN) Notifying guest 0:67 (virq 1, port 0) Oct 4 07:24:55.680924 (XEN) Notifying guest 0:68 (virq 1, port 0) Oct 4 07:24:55.680982 (XEN) Notifying guest 0:69 (virq 1, port 0) Oct 4 07:24:55.681027 (XEN) Notifying guest 0:70 (virq 1, port 0) Oct 4 07:24:55.692929 (XEN) Notifying guest 0:71 (virq 1, port 0) Oct 4 07:24:55.692988 (XEN) Notifying guest 0:72 (virq 1, port 0) Oct 4 07:24:55.693033 (XEN) Notifying guest 0:73 (virq 1, port 0) Oct 4 07:24:55.704928 (XEN) Notifying guest 0:74 (virq 1, port 0) Oct 4 07:24:55.704987 (XEN) Notifying guest 0:75 (virq 1, port 0) Oct 4 07:24:55.705032 (XEN) Notifying guest 0:76 (virq 1, port 0) Oct 4 07:24:55.716928 (XEN) Notifying guest 0:77 (virq 1, port 0) Oct 4 07:24:55.716987 (XEN) Notifying guest 0:78 (virq 1, port 0) Oct 4 07:24:55.717033 (XEN) Notifying guest 0:79 (virq 1, port 0) Oct 4 07:24:55.728927 (XEN) Notifying guest 0:80 (virq 1, port 0) Oct 4 07:24:55.728986 (XEN) Notifying guest 0:81 (virq 1, port 0) Oct 4 07:24:55.729031 (XEN) Notifying guest 0:82 (virq 1, port 0) Oct 4 07:24:55.740924 (XEN) Notifying guest 0:83 (virq 1, port 0) Oct 4 07:24:55.740983 (XEN) Notifying guest 0:84 (virq 1, port 0) Oct 4 07:24:55.741029 (XEN) Notifying guest 0:85 (virq 1, port 0) Oct 4 07:24:55.752904 (XEN) Notifying guest 0:86 (virq 1, port 0) Oct 4 07:24:55.752963 (XEN) Notifying guest 0:87 (virq 1, port 0) Oct 4 07:24:55.753009 (XEN) Notifying guest 0:88 (virq 1, port 0) Oct 4 07:24:55.764924 (XEN) Notifying guest 0:89 (virq 1, port 0) Oct 4 07:24:55.764984 (XEN) Notifying guest 0:90 (virq 1, port 0) Oct 4 07:24:55.765030 (XEN) Notifying guest 0:91 (virq 1, port 0) Oct 4 07:24:55.776910 (XEN) Notifying guest 0:92 (virq 1, port 0) Oct 4 07:24:55.776970 (XEN) Notifying guest 0:93 (virq 1, port 0) Oct 4 07:24:55.777016 (XEN) Notifying guest 0:94 (virq 1, port 0) Oct 4 07:24:55.788894 (XEN) Notifying guest 0:95 (virq 1, port 0) Oct 4 07:24:55.788953 Oct 4 07:25:02.293792 (XEN) *** Serial input to DOM0 (type 'CTRL-x' three times to switch input) Oct 4 07:25:02.312951 Oct 4 07:25:02.314434